JPS60258935A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS60258935A JPS60258935A JP11487584A JP11487584A JPS60258935A JP S60258935 A JPS60258935 A JP S60258935A JP 11487584 A JP11487584 A JP 11487584A JP 11487584 A JP11487584 A JP 11487584A JP S60258935 A JPS60258935 A JP S60258935A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- eliminated
- wiring
- network
- master slice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009826 distribution Methods 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 244000292604 Salvia columbariae Species 0.000 description 1
- 235000012377 Salvia columbariae var. columbariae Nutrition 0.000 description 1
- 235000001498 Salvia hispanica Nutrition 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 235000014167 chia Nutrition 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は集積回路装置に関し、特にマスタースライス型
の大規模集積回路（以下ＬＳＩと記す）の電源配線網の
構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an integrated circuit device, and particularly to the structure of a power supply wiring network of a master slice type large-scale integrated circuit (hereinafter referred to as LSI).
（従来技術）
マスタースライス型ＬＳＩにおいては１例えば２人力Ｎ
ＡＮＤ’を構成できるような複数の素子からなる基本セ
ルが一定数繰シ返し縦横に並べられている。この基本セ
ルを組み合せて作られるマクロブロック（以下単にプロ
、りと記す）に対して電力を供給するための電源配線網
がセルアレイの上に布設される。ブロック間を結ぶ信号
線の配線は。(Prior art) In master slice type LSI, 1, for example, 2 human power N
Basic cells consisting of a plurality of elements that can form an AND' are repeatedly arranged vertically and horizontally a certain number of times. A power supply wiring network is laid over the cell array for supplying power to macroblocks (hereinafter simply referred to as "Pro") made by combining these basic cells. Wiring the signal lines between blocks.
プロ、り内配線や電源配線以外のチップ空領域を用いて
行なわれる。This is done using the empty area of the chip other than internal wiring or power supply wiring.
従来は、セルアレイの規則性に照合して、電源配線網は
第４図のような格子状に、又は第５図のような梯子状に
構成されていた。すなわちＰ！〜Ｐｓは横方向に配置さ
れ、ｐＨ〜ｐｔｓ は縦方向にそれぞれ１または複数の
セル毎のピッチをもって布設された配線でその結果第４
図では格子状。Conventionally, the power supply wiring network has been configured in a grid pattern as shown in FIG. 4 or in a ladder pattern as shown in FIG. 5 in accordance with the regularity of the cell array. In other words, P! ~Ps is arranged in the horizontal direction, and pH~pts is the wiring laid in the vertical direction with a pitch of one or more cells.
In the figure, it is a grid.
第５図では梯子状の電源配線網を形成し、その最外部か
ら電源供給用外部パッド１〜４お工び１１〜１４に接続
されている。又Ｂは基本セル全組み合せて作られるマク
ロブロックである。In FIG. 5, a ladder-like power supply wiring network is formed, and the outermost power supply wiring network is connected to external power supply pads 1 to 4 and 11 to 14. Further, B is a macroblock made by combining all basic cells.
これらは実現しようとする回路の所要ゲート数。These are the required number of gates for the circuit you are trying to implement.
すなわち使用するセル数に関係なく共通に設けられてい
る。従って回路の所要ゲート数が少ない場合にはこの電
源網の一部が不要となる場合もある。That is, it is provided in common regardless of the number of cells used. Therefore, if the required number of gates in the circuit is small, part of this power supply network may be unnecessary.
しかしパターンが固定されているので、チア１面積全電
源網が過剰に占める結果となる。However, since the pattern is fixed, the result is that the chia 1-area full power network occupies an excessive amount.
一方、共通の電源網パターン全般けず、電源線を通常の
信号線と同じように扱って配線する場合もある。この場
合電源線の幅だけは、電流量に応じて変えるものでめる
。したし線幅の異なる配線パターンが、不規則に置かれ
ることになり１通常の信号線に対する配線性を著しく低
下させる結果となる。On the other hand, although there is no common power network pattern in general, there are cases where power lines are handled and wired in the same way as normal signal lines. In this case, only the width of the power supply line can be changed depending on the amount of current. However, wiring patterns having different line widths are arranged irregularly, resulting in a significant deterioration in wiring performance for normal signal lines.
（発明の目的）
本発明の目的は、上記欠点を除去し１回路の電気的特性
全保障しつつ、不要な電源網全部分的に削除し、取り除
かれた領域金も ４Ｈ号線の配線に供して、ＬＳＩのチ
ップ面積の有効利用を計った集積回路装置全提供するこ
とにある。(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks and fully guarantee the electrical characteristics of one circuit, while also partially removing the unnecessary power supply network and using the removed area metal for the wiring of the 4H line. The purpose of the present invention is to provide an integrated circuit device that makes effective use of the LSI chip area.
（発明の構成）
本発明の集積回路装置は、基本セルが水平方向および垂
直方向に繰り返し並べられているセルアレイを持つマス
タースライス型集積回路であって。(Structure of the Invention) The integrated circuit device of the present invention is a master slice type integrated circuit having a cell array in which basic cells are repeatedly arranged in the horizontal and vertical directions.
前記セルアレイには１又は複数のセル毎のピッチを持っ
て水平又は垂ｍの一方又は両方に布設形成された配線に
より構成された梯子状又は格子状の配ａを有し、該配線
網の最外郭部が電源供給用外部パッドに接続された電源
配線網において、最外郭部を除く内部の網の一部が欠損
した構造となることにより構成される。The cell array has a ladder-like or lattice-like arrangement constituted by wiring laid horizontally or vertically or both at a pitch of one or more cells, and the topmost part of the wiring network is In a power supply wiring network whose outer part is connected to an external pad for power supply, a part of the inner network except for the outermost part is missing.
（実施例）
以下１本発明の実施例について１図面’ｅ９ｊ−照して
説明する。(Example) An example of the present invention will be described below with reference to one drawing.
第１図は本発明の第１の実施例の電源配線網の説明図で
ある。第１図に示すように、基本セルが水平方向および
垂直方向に繰り返し並べられているセルアレイを持つマ
スタスライスチップに対し１または複数のセル行に対し
Ｐ１〜Ｐ５が布線され、またセル列に対してはｐＨ〜ｐ
ｔｓが布線され両方向の布線で図示のような格子状の電
源網が設定できる。次に所定の回路を構成するブロック
群（表示されていない）を配置したのちに、上記電源網
の電位分布電流分布全求め、電源網の不要部分全削除す
る。電源網の部分的削除対象部分としては、該当部分か
ら電力を受けるプロ、りがないこと、かつそれを削除し
てもその周辺のブロックに、かける電圧電流利得等の特
性全損なわないものについて行うことができる。FIG. 1 is an explanatory diagram of a power supply wiring network according to a first embodiment of the present invention. As shown in Figure 1, for a master slice chip that has a cell array in which basic cells are arranged repeatedly in the horizontal and vertical directions, P1 to P5 are wired to one or more cell rows, and P1 to P5 are wired to the cell columns. For pH~p
ts is wired, and by wiring in both directions, a grid-like power supply network as shown in the figure can be set up. Next, after placing a group of blocks (not shown) constituting a predetermined circuit, the entire potential distribution and current distribution of the power supply network is determined, and all unnecessary parts of the power supply network are deleted. Parts of the power supply network that are subject to partial deletion should be those that do not receive power from the relevant part, and that even if it is removed, the characteristics such as the voltage and current gain applied to the surrounding blocks will not be lost. be able to.
第１図は、上記条件に合致した部分全削除した格子状の
電源網である。FIG. 1 shows a grid-like power supply network that meets the above conditions and has been completely deleted.
また、第２図は本発明の第２の実施例の電源配線網の説
明図である。第２図に於ては、セル列に対しｐＨ〜Ｔ’
ｔｓ が布設され、その端部はＰｌ及びＰｓで結ばれ、
全体として梯子状電源配線網となシ、上記した条件に合
致した部分の一部の電源網が欠損している。Further, FIG. 2 is an explanatory diagram of a power supply wiring network according to a second embodiment of the present invention. In Figure 2, for the cell row, pH ~ T'
ts is laid, its ends are tied with Pl and Ps,
The power supply network as a whole is a ladder-like power supply network, but some power supply networks that meet the above conditions are missing.
なお、電源網の電圧電流分布を正確にめるには、抵抗回
路網の直流解析によるが、計算機援用５−
による設計自動化技術の進歩にょカこれが芥易になって
いる。In order to accurately determine the voltage and current distribution of the power supply network, DC analysis of the resistance network is required, but this is becoming easier with advances in design automation technology using computer aids.
本発明によ殴削除した部分は信号配線領域として利用で
き、マスタースライス型Ｌ８ＩＫおける配線の自由度及
び配線状容度全向上させることができる。しかも上記条
件に適合した部分を除去しているので特性低下は殆んど
ない。According to the present invention, the removed portion can be used as a signal wiring area, and the degree of freedom and capacity of wiring in the master slice type L8IK can be completely improved. Moreover, since the portions that meet the above conditions are removed, there is almost no deterioration in characteristics.
第３図（ａｌ、 （ｂ）は本発明の第３の実施例並びに
その形成工程を説明するための電源配線網説明図である
。FIGS. 3A and 3B are explanatory diagrams of a power supply wiring network for explaining a third embodiment of the present invention and its formation process.
第３図（ａ）に示すように１本笑施例では基本セルＣ１
が水平方向に繰シ返し並んだセル行Ｃｓ ｔ”、さらに
垂は方向に繰り返し並べたマスタースライス型ＬＳＩが
示されている。セルー行につき電源供給線Ｖ！とグラウ
ンド線Ｇｔｅ行方向に布線し。As shown in FIG. 3(a), in the one cell example, the basic cell C1
A master slice type LSI is shown in which cell rows Cs t" are repeatedly arranged in the horizontal direction, and a master slice type LSI is further arranged repeatedly in the vertical direction. For each cell row, a power supply line V! and a ground line Gte are wired in the row direction. death.
ある間隔を持って、セル列方向に電源供給線■２とグラ
ウンド線Ｇ、の対が布線される。行方向布線と列方向布
線とは異なる層を用いて、それが交差する部分にはスル
ーホールを置いて格子状に電源網が構成される。A pair of power supply line (2) and ground line (G) is wired at a certain interval in the direction of the cell column. Different layers are used for the row direction wiring and the column direction wiring, and through holes are placed at the intersections of the layers to form a grid-like power supply network.
６− 次にブロックＢ１〜Ｂ４の配置状況に応じて。6- Next, depending on the arrangement situation of blocks B1 to B4.
ブロック配置密度が少ない部分の電源網Ｎｌ ｋ削除す
ると第３図（ｂ）に示すような一部電源網が欠除された
本実施例の構造が得られる。By deleting the power supply network Nlk in the portion where the block arrangement density is low, a structure of this embodiment in which a part of the power supply network is deleted as shown in FIG. 3(b) is obtained.
本実施例によ勺削除した部分は第１．第２の実施例と同
様に電気的特性を殆んど低下させることなく、信号配線
領域として利用でき、マスタースライス型ＬＳＩの配線
の自由度並びに配線の収容度全向上させることができる
。The portions deleted in this example are in the first section. As in the second embodiment, it can be used as a signal wiring area with almost no deterioration in electrical characteristics, and the degree of freedom and accommodation of wiring in the master slice type LSI can be completely improved.
なお、本発明をさらに有効に活用するには、ブロックに
おける電源引き込み口金２箇所以上設けておき、ブロッ
クの配線位置の状況により切り換えて、電源網の削除可
能な箇所を増やすことができる。In order to utilize the present invention more effectively, it is possible to increase the number of locations in the power supply network that can be removed by providing two or more power supply lead-in ports in the block and switching them depending on the wiring position of the block.
（発明の効果）
以上説明したとおフ１本発明によれば１回路の電気的特
性を保障しつつ、不要な電源網を部分的； に削除し、
取り除かれた領域をも、信号線の配線に供することによ
Ｊ、ＬＳＩチップの面積の有効利用を計った集積回路が
得られる。(Effects of the Invention) As explained above, according to the present invention, unnecessary power supply networks are partially deleted while guaranteeing the electrical characteristics of one circuit.
By using the removed area for wiring the signal lines, an integrated circuit can be obtained that makes effective use of the area of the LSI chip.
第１図、第２図は本発明の実施例の電源配線網の説明図
、第３図（ａ） 、 （ｂ）は本発明の他の実施例並び
にその形成工程を説明するだめの電源配線網の説明図、
第４図、第５図は従来のマスタスライス型集積回路の電
源配線網の説明図である。
１〜４，１１〜１４・・・・・・電源供給用外部パッド
、Ｂ、Ｂ、〜Ｂ４・・川・ブロック、Ｃ１・・団・基本
セルｓｃ２・・・・・・セル行、Ｇ１．Ｇ、・・・・・
・グラウンド線、Ｎ１・・・・・・電源網欠損部、Ｐ、
−、Ｐｌｌ・・・・・・行方向配線、Ｐｌ、〜Ｐ１！・
・・・・・列方向配線、Ｖ、、Ｖ、・曲・電源。
第３閏
第５閃1 and 2 are explanatory diagrams of a power supply wiring network according to an embodiment of the present invention, and FIGS. 3(a) and 3(b) are diagrams illustrating another embodiment of the present invention and its formation process. Illustration of the net,
FIGS. 4 and 5 are explanatory diagrams of a power supply wiring network of a conventional master slice type integrated circuit. 1-4, 11-14...external pad for power supply, B, B, ~B4...river/block, C1...group/basic cell sc2...cell row, G1. G...
・Ground wire, N1... Power supply network defective part, P,
-, Pll... Row direction wiring, Pl, ~P1!・
・・・Column direction wiring, V,,V,・song・power supply. 3rd Leap 5th Flash
Claims (1)
ているセルアレイを持つマスタースライス型集積回路で
あって、前記セルアレイには１又は複数のセル毎のピッ
チを持って水平又は垂面の一方又は両方に布設形成され
た配線により構成された梯子状又は格子状の配線を有し
、該配線網の最外郭部が電源供給用外部パッドに接続さ
れた電源配線網において、最外郭部を除く内部の網の一
部が欠損した構造となっていることを特徴とする集積回
路装置。A master slice integrated circuit having a cell array in which basic cells are arranged repeatedly in the horizontal and vertical directions, the cell array having a pitch for each one or more cells, and having either a horizontal or vertical surface. Or, in a power supply wiring network, which has a ladder-like or lattice-like wiring composed of wiring laid on both sides, and the outermost part of the wiring network is connected to an external power supply pad, excluding the outermost part. An integrated circuit device characterized by having a structure in which a portion of an internal network is missing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11487584A JPS60258935A (en) | 1984-06-05 | 1984-06-05 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11487584A JPS60258935A (en) | 1984-06-05 | 1984-06-05 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60258935A true JPS60258935A (en) | 1985-12-20 |
Family
ID=14648867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11487584A Pending JPS60258935A (en) | 1984-06-05 | 1984-06-05 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60258935A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01278040A (en) * | 1988-04-30 | 1989-11-08 | Nec Corp | Semiconductor integrated circuit |
| EP1231638A1 (en) * | 2001-02-10 | 2002-08-14 | TOSHIBA Electronics Europe GmbH | Power supply wiring of an integrated circuit |
-
1984
- 1984-06-05 JP JP11487584A patent/JPS60258935A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01278040A (en) * | 1988-04-30 | 1989-11-08 | Nec Corp | Semiconductor integrated circuit |
| EP1231638A1 (en) * | 2001-02-10 | 2002-08-14 | TOSHIBA Electronics Europe GmbH | Power supply wiring of an integrated circuit |
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