JPH05267624A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate a connection wiring between function blocks by a method wherein fundamental cells, which are different from each other in kind, are regularly combined with each other and are arranged in the first direction of a semiconductor chip. CONSTITUTION:A first kind of fundamental cells 13 and a second kind of fundamental cells 14, the positions of input terminals of which and whose wiring layer are different from only those of input terminals of these cells 13 and a wiring layer of the cells 13, are regularly arranged on a semiconductor chip 11 on the form of matrix. That is, the same kind of the fundamental cells are arranged in the direction Y of the chip 11 and the cells 13 and the cells 14 are alternately arranged one piece by one piece in the direction X of the chip 11. Thereby, as input electrodes 24 of the cells 13 and input electrodes 25 of the cells 14 are not positioned on the same lattice 26 and the positions of the input terminals of the cells 13 and 14 are different from each other in each kind of the cells, a connection wiring between function blocks is facilitated and an effect in the improvement of the efficiency of the wiring is great.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a gate array type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In a conventional gate array type semiconductor integrated circuit device, as shown in FIG. 5, an input / output buffer 52 is arranged in the periphery of a semiconductor chip 51, and a basic cell of the same type, that is, the position of an input terminal is located inside thereof. The basic cells 53 identical to each other were regularly arranged in a matrix.

[0003]

In this conventional gate array type semiconductor integrated circuit device, since the input terminals of the basic cells on the semiconductor chip are located on the same grid,
When connecting and wiring the function block composed of the basic cells and the function block by the automatic wiring, there is a problem that the input terminal of the desired function block cannot be connected due to the large amount of wiring and unwiring occurs. ..

[0004]

A feature of the present invention is that it has two or more types of basic cells having different input terminal positions.
A gate array type semiconductor integrated circuit device in which the different types of basic cells are regularly combined and arranged in a first direction of a semiconductor chip. Here, it is preferable that basic cells of the same type are arranged in a second direction perpendicular to the first direction. Also, in the first direction,
The first type basic cells and the second type basic cells may be alternately arranged one by one. Alternatively, a plurality of second type basic cells are arranged between the first type basic cells and the first type basic cells and are regularly arranged in the first direction. it can.

[0005]

The present invention will be described below with reference to the drawings. 1 is a plan view showing a semiconductor chip according to a first embodiment of the present invention.

An input / output buffer 12 is arranged around the semiconductor chip 11, and a first type basic cell (indicated by hatching in the upper right) 13 and an input of the first type basic cell 13 are provided inside the input / output buffer 12. A second type of basic cell (no hatching) which is different only in the position of the terminal and its wiring layer 14
And are regularly arranged in a matrix. That is, basic cells of the same type are arranged in the Y direction of the semiconductor chip, and one basic cell 13 of the first type and one basic cell 14 of the second type are arranged in the X direction perpendicular to the Y direction. They are arranged alternately.

As shown in FIG. 2, a first type basic cell 1
3 and the second type basic cell 14 have the same width W, the same length L, and the same area. However, the distance in the Y direction between the two input electrodes 25, 25 of the second type basic cell 14 is smaller than the distance in the Y direction between the two input electrodes 24, 24 of the first type basic cell 13. Large and input electrode 2
4 and the input electrode 25 are located at different positions in the Y direction.

As a result, as shown in FIG. 3, the input electrode 24 of the first type basic cell 13 and the input electrode 25 of the second type basic cell 14 are not located on the same grid 26. Since the position of the input terminal differs depending on the type of basic cell, the cell usage rate is high in the desired circuit, and even if the wiring density is large, the connection wiring between function blocks can be facilitated and the wiring efficiency is improved. The effect is great. Note that, in FIG. 3, like the GND line 28 and the power supply line 27, the lattice also shows the lattice 26 extending in the X direction at a predetermined position in the Y direction.

FIG. 4 is a plan view of a semiconductor chip according to the second embodiment of the present invention. In FIG. 4, the same parts as those in FIGS. 1 to 3 are indicated by the same reference numerals. In this embodiment, the first
Similar to the embodiment described above, the same type of basic cells are arranged in the Y direction of the semiconductor chip, but X in the direction perpendicular to the Y direction is used.
In the direction, one basic cell 13 of the first type and two basic cells 14 of the second type are alternately arranged. Like the first embodiment, the second embodiment also has a great effect because the input terminals of the respective basic cells on the semiconductor chip are regularly located on different grids so that the wiring efficiency is improved. ..

[0010]

As described above, the present invention has the first type basic cell and the second type basic cell in which the positions of the input terminals are different from each other, and the semiconductor chip has one direction (X direction). By arranging the above-mentioned first type basic cell and second type basic cell with regularity, the input terminals of each basic cell on the semiconductor chip are positioned on different grids with regularity. In the case where a desired circuit is automatically wired, the wiring efficiency is improved, the circuit having a high cell usage rate can be easily wired automatically, and the non-wiring is eliminated, so that the design period can be shortened.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a first type basic cell and a second type basic cell in the first embodiment of the present invention.

FIG. 3 is an enlarged plan view showing a part of the semiconductor chip according to the first embodiment of the present invention.

FIG. 4 is a plan view showing a semiconductor chip according to a second embodiment of the present invention.

FIG. 5 is a plan view showing a conventional semiconductor chip.

[Explanation of symbols]

 11, 51 Semiconductor chip 12, 52 Input / output buffer 13 First type basic cell 14 Second type basic cell 24 First type basic cell input terminal 25 Second type basic cell input terminal 26 Lattice 27 Power line 28 GND line 53 Basic cell

Claims (4)

[Claims] 1. A basic cell having two or more types of basic cells each having a different input terminal position, and the basic cells of the different types are regularly combined and arranged in a first direction of a semiconductor chip. Gate array type semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein basic cells of the same type are arranged in a second direction perpendicular to the first direction. 3. The first type basic cell and the second type basic cell are alternately arranged one by one in the first direction. The semiconductor integrated circuit device according to 1. 4. A plurality of second type basic cells are arranged between the first type basic cells and the first type basic cells, and are regularly arranged in the first direction. The semiconductor integrated circuit device according to claim 1 or 2, wherein