JPH05243533A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make an internal automatic wiring region large without increasing a chip size CONSTITUTION:An internal cell array 1 for a low-power consuming type functional block arrangement is arranged inside of a semiconductor chip 70 and an internal cell array 2 for a high-power consuming type functional block arrangement is arranged on the input/output external block 5 side. On the outside thereof, an input/output external cell 5 and an external pad 4 are arrayed. A power supply wiring 3 is arranged on the periphery of the chip 70 to supply internal cell arrays 1, 2 with electric power. And in the internal cell arrays 1, 2, the power supply wiring 3 has a width which meets the respective consumed powers, so that the width of a wiring 7 on the internal cell 1 for the low-power consuming type functional block arrangement is small and the width of a wiring 6 on the internal cell 2 for a high-power consuming type functional block arrangement is large.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an internal cell array power supply wiring of a master slice type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art An internal cell of a conventional master slice type semiconductor integrated circuit device is a wiring that guarantees a potential shift amount due to a wiring resistance, regardless of the type, position and number of functional blocks arranged and wired in a cell array. It has a width of power wiring.

Such a conventional semiconductor integrated circuit device is
5 and 6 show.

In FIG. 5, the semiconductor chip 50 has a wide grid-like power supply wiring 40 on the internal cell array 36 for low power consumption / high power consumption / functional block.
A power supply wiring 37 is provided around this, and a large number of external pads 38 are arranged on the outside thereof. In addition, the input / output external cell 3
9 are also arranged.

In FIG. 6, the present semiconductor chip 60 has parallel line-shaped power supply lines on the internal cell array 41 for low power consumption / high power consumption / functional block, around which power supply lines 42 and input / output external cells are provided. 44 and the external pad 43 are arranged.

[0006]

The internal cell power supply wiring 4 of this conventional master slice type semiconductor integrated circuit device.
0 and 45 must have power supply wiring widths that can guarantee the amount of power supply potential shift due to wiring resistance even when high power consumption type functional cells are arranged in the entire internal cell array matrix. There is a problem in that it is necessary to increase the area of the wirings 40 and 45, and it is necessary to increase the cell size or reduce the automatic wiring area.

It is an object of the present invention to provide a semiconductor integrated circuit device which solves the above problems and does not require a large power supply wiring area.

[0008]

According to the structure of a semiconductor integrated circuit device of the present invention, a first internal cell having a low power consumption functional block is arranged inside a semiconductor chip, and the first internal cell is outside the inside. A second internal cell in which a functional block of high power consumption is arranged is arranged in the input / output external cell.

[0009]

1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

In FIG. 1, the semiconductor integrated circuit device according to the present embodiment has a low power consumption type functional block arrangement internal cell array 1 inside a semiconductor chip 70, and a high power consumption type functional block arrangement on the input / output external block 5 side. The internal cell array 2 for use is arranged. Input / output external cells 5 and external pads 4 are arranged on the outside thereof. The power supply wiring 3 circulates around the chip 70 and supplies it to the internal cell arrays 1 and 2.

In the internal cell arrays 1 and 2, the power supply wiring 3 has a wiring width corresponding to the power consumption,
The width of the wiring 7 is small on the so-called low power consumption type functional block layout internal cell 1, and the width of the wiring 6 is large on the high power consumption type functional block layout internal cell 2.

When the power ratio of the low power consumption type and the high power consumption type is 1: 2 and the internal cell usage rate is 50%: 50%, the power supply wiring area on the internal cell region is 2 of the conventional semiconductor integrated circuit.
This is one-third, and the conventional power supply wiring occupies 30% of the internal cell array area, but the automatic wiring area is increased by 15%.

As described above, the structure of the semiconductor integrated circuit device of this embodiment has an internal cell array for low power consumption functional blocks on the inside of the chip and an internal cell array for high power consumption type functional blocks on the input / output external cell side. Each of them is arranged, and a power supply wiring width on the internal cell array is provided for each power consumption.

FIG. 2 is a plan view of the second embodiment of the present invention.

In FIG. 2, the semiconductor chip 7 of this embodiment is shown.
1 has internal cell arrays 9 and 10 for a high power consumption type functional block on the upper and lower sides of an internal cell array 8 for a low power consumption type functional block, around which a power supply wiring 11, an input / output external cell 13 and an external pad 12 are arranged. Has been done. here,
The width of the power supply wiring 14 is wider than that of the power supply wiring 15. The effect is the same as in the case of FIG.

FIG. 3 is a plan view of the third embodiment of the present invention.

In FIG. 3, the semiconductor chip 7 of this embodiment is shown.
2 is an internal cell array 16 for low power consumption type functional blocks
An internal cell array 17 for intermediate power consumption type functional blocks around it, an internal cell array 18 for high power consumption type functional blocks around it, an input / output external cell 21, an external pad 20, and a power supply wiring 19. ing. The effect is similar to that of the above embodiment.

FIG. 4 is a plan view of the fourth embodiment of the present invention.

In FIG. 4, the semiconductor chip 7 of this embodiment is shown.
3 is an internal cell array 25 for low power consumption type functional block
And intermediate power consumption type functional block internal cell arrays 26 and 27 on the upper and lower sides thereof, and high power consumption type functional block internal cell arrays 28 and 29 on the upper and lower sides thereof, an input / output external cell 32, and an external pad 31. , And power supply wiring 30. The effect is similar to that of the above embodiment.

[0020]

As described above, according to the present invention, at least the low power consumption type functional block arranging internal cell array is arranged inside the chip, and the high power consumption type functional block arranging internal cell array is arranged at the input / output external cell side. Since the width of the power supply wiring to the internal cells was set to the wiring width suitable for the power supply,
It has the effect that the internal automatic wiring area can be made large without increasing the chip size. Also, even if there are many types of power consumption of the functional block, the power wiring width on the internal cell array can be set to the power consumption type. The same effect can be obtained by preparing the parts.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a second embodiment of the present invention.

FIG. 3 is a plan view of a third embodiment of the present invention.

FIG. 4 is a plan view of a fourth embodiment of the present invention.

FIG. 5 is a plan view showing an example of a conventional semiconductor chip.

FIG. 6 is a plan view showing another example of a conventional semiconductor chip.

[Explanation of symbols]

1,8,16,25 Low power consumption type functional block internal cell array 2,9,10,18,28,29 High power consumption type functional block internal cell array 17,26,27 Intermediate power consumption type functional block internal cell array 36,41 Low power consumption High power consumption dual-purpose function block internal cell array 3,11,19,30,37,42 Power supply wiring 4,12,20,31,38,43 External pad 5,13,21,32, 39,44 Input / output external cells 6,14,22,33 Power wiring on internal cell array for high power consumption type functional block 7,15,24,35 Power supply wiring on internal cell array for low power consumption type functional block 23,34 Intermediate consumption Power supply on internal cell array for power type functional block 40, 45 Low power consumption High power consumption Internal power supply on internal cell array for dual function block

Claims (2)

[Claims] 1. A first internal cell in which a low power consumption functional block is disposed inside a semiconductor chip, and a high power consumption functional block is disposed in an input / output external cell outside the inside. A semiconductor integrated circuit device in which a second internal cell is arranged. 2. The semiconductor integrated circuit device according to claim 1, wherein a third internal cell is arranged as a functional block of intermediate power consumption between the first internal cell and the second internal cell.