JPH0630377B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, regularly disposing unit blocks formed of one or a plurality of semiconductor elements, and between semiconductor elements and unit blocks. The present invention relates to a technique effective when applied to a semiconductor integrated circuit device capable of extracting various logical functions by changing a wiring pattern applied between them.

2. Description of the Related Art A semiconductor integrated circuit device needs to design a large number of products in a small amount within a short time. Therefore, a plurality of unit blocks formed of one or a plurality of semiconductor elements are regularly arranged and wiring patterns of There is a tendency to employ a so-called master slice method capable of extracting various different logical functions only by changing (see, for example, "Nikkei Electronics" published by Nikkei McGraw-Hill, April 13, 1981, p203-p212).

In the semiconductor integrated circuit device that employs this master slice method, in order to efficiently form a logic circuit, automatic placement and routing of automatic placement of unit blocks and wiring that electrically connects them can be performed automatically. You are using the system.

However, as a result of study in such a technique, the present inventor has found that, when an automatic placement and routing system is used, a clock generation circuit that requires a large current and other clock system circuits are concentrated in one unit block row. Because it will be
Due to the unit block row, migration occurs in the reference voltage wiring having a wiring width of about 10 to 20 [μm], and the electrical reliability of the semiconductor integrated circuit device is deteriorated, such as disconnection of the wiring and shortened life. Found out.

[Object of the Invention] An object of the present invention is to provide a technical means capable of reducing the influence of wiring migration due to a clock generation circuit or the like that requires a large current and improving the electrical reliability of a semiconductor integrated circuit device. To provide.

Another object of the present invention is to provide a technical means capable of equalizing and shortening a wiring length between a clock generating circuit and the like and a circuit driven by the clock generating circuit and increasing the operating speed of a semiconductor integrated circuit device. Especially.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the first block extending substantially in the same direction as the unit block row
A second reference voltage wiring having a wiring width larger than that of the reference voltage wiring is provided in a central portion substantially orthogonal to the unit block row, and a plurality of unit blocks are provided below the second reference voltage wiring. By constructing a clock generation circuit or the like requiring a large current in the unit block and using the second reference voltage wiring, the influence of migration due to the clock generation circuit or the like can be reduced, so that the semiconductor integrated circuit The electrical reliability of the device can be improved.

Hereinafter, regarding the configuration of the present invention, the present invention will be described as a three-input N-type with a complementary field effect transistor (hereinafter, referred to as CMIS).
An embodiment applied to a semiconductor integrated circuit device adopting a master slice method having unit blocks capable of forming an AND gate circuit will be described.

[Embodiment I] FIG. 1 is a schematic plan view of a semiconductor integrated circuit device adopting a master slice method for explaining an embodiment I of the present invention, and FIG. 2 is a schematic main part of FIG. It is an enlarged plan view. In order to make the drawings easier to see, FIGS. 1 and 2 do not show insulating films other than the element isolation insulating film provided between the conductive layers.

In all the drawings of the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

In FIGS. 1 and 2, reference numeral 1 is a semiconductor integrated circuit device adopting the master slice method.

A plurality of external input / output terminals 2 are arranged at the most peripheral portion of the semiconductor integrated circuit device 1 for electrically connecting an internal integrated circuit and an external device.

Reference numeral 3 denotes an input / output circuit provided between the external input / output terminal 2 and the internal integrated circuit, which is regularly arranged in the peripheral portion of the semiconductor integrated circuit device 1. It is for controlling the electric signal level transmitted between them.

Reference numeral 4 is a unit block regularly arranged in the central portion of the semiconductor integrated circuit device 1 to form a predetermined logic circuit.

The unit block 4 is defined by an element isolation insulating film 5 and is connected in parallel with three p-channel MISFETs.
Qp and three n-channel MISF connected in parallel
It is configured by CMIS with ETQn, so that a 3-input NAND gate circuit can be configured.

Reference numeral 6 denotes a unit block row provided by regularly arranging a plurality of unit blocks 4 in the column direction, for facilitating the configuration of a logic circuit.

A plurality of the unit block columns 6 are arranged in a row direction at a predetermined interval, and in this embodiment, the unit block column 6 is composed of two rows.

Reference numeral 7 denotes a wiring region provided in the central portion of the semiconductor integrated circuit device 1 between the unit block columns 6 arranged in the row direction,
This is a region for providing wiring that electrically connects the unit blocks 4.

Reference numerals 8A, 8B and 9A denote wirings provided in the peripheral portion of the semiconductor integrated circuit device 1. Wire 8A, the reference voltage _{V SS} (e.g., 0 [V] or -2.5~-3.5 [V]) as it is connected, is to use the input-output circuit 3. Wiring 8B
Is connected to the reference voltage V _{SS and} is used in the internal integrated circuit formed by the unit block 4.
The wiring 9A is connected to the reference voltage V _DD (for example, 5 [V]) and is used by the input / output circuit 3 and the internal integrated circuit.

Reference numerals 8C and 9B denote a wiring 9C for a reference voltage V _DD and a reference voltage V, which are provided in the central portion of the semiconductor integrated circuit device 1 and extend above the unit block row 6 in a column direction substantially the same as that direction.
The wiring has a wiring width larger than that of the wiring 8D for _SS and is provided so as to extend so as to be substantially orthogonal to the unit block row 6, and the reference voltage V _SS and the reference voltage V _DD are connected. It is supposed to be done.

The wirings 8C and 9B are for reducing potential fluctuations in the central portion of the semiconductor integrated circuit device 1 as much as possible.

The wirings 8C and 9B are the wirings 8A, 8B and 9A.
The wiring width is, for example, about 50 to 100 [μm].

Reference numeral 10 is a unit block provided in a plural number below the wirings 8C and 9B, for example, for forming a clock generation circuit or the like which requires a large current. Like the unit block 4, the unit block 10 has three p-channel MISFEs so as to prevent complication of the manufacturing process of the semiconductor integrated circuit device 1 and facilitate formation of various logic circuits.
It is configured by CMIS including TQP and three n-channel MISFETs QN, so that a three-input NAND gate circuit can be configured.

Reference numeral 11 is a unit block row provided by arranging a plurality of unit blocks 10 in the row direction, and is for facilitating the configuration of a logic circuit.

Although the example in which one unit block row 11 is provided is described in the present embodiment, the wirings 8C and 9B are the wiring 8
The wiring width is about 2.5 to 10 times larger than that of D and 9C, and MISFETs QP and QN are connected to MISFETs Qp and Q.
You may make it the size of about n, and may provide the unit block column 11 of several rows.

Next, a case will be described in which the unit block 10 and the unit block row 11 are used to form a clock generation circuit that requires a large current.

FIG. 3 is a circuit diagram showing a clock generation circuit for explaining the embodiment I of the present invention, and FIG. 4 is a schematic diagram of a semiconductor integrated circuit device when the clock generation circuit of FIG. 3 is configured. FIG. Incidentally, in FIG. 4, the wiring is simplified and shown by a solid line, and a connecting portion with the wiring is shown by a dot.

In FIGS. 3 and 4, reference numeral 12 is a clock generation circuit, which drives a plurality of clock driver circuits by one, and thus requires a large current.

Reference numeral 12A is a NAND gate circuit, and 12B to 12E are inverter circuits for constituting the clock generation circuit 12. I ₁ is an input signal of the clock generation circuit 12 output from the input / output circuit (input / output buffer circuit) 3, I ₂ is an input signal terminal of the clock generation circuit 12,
O ₁ , O ₂ , O ₃ , and O ₄ are output signal terminals of the clock generation circuit 12 connected to the clock driver circuit.

As described above, according to the present Example I, the second reference voltage wiring having a wiring width larger than that of the first reference voltage wiring extending substantially in the same direction as the unit block row is used as a unit. The second reference voltage is provided in a central portion substantially orthogonal to the block row, a plurality of unit blocks are provided under the second reference voltage wiring, and the unit block configures a clock generation circuit or the like requiring a large current. Since the wiring for use has a sufficient wiring width, it is possible to reduce the influence of migration due to the clock generation circuit or the like.

Therefore, it is possible to prevent the disconnection of the wiring, the reduction of the life of the wiring, and the like, so that the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, irrespective of whether the automatic placement and routing system is used or not, by arranging the clock generation circuit and the like in the central portion of the semiconductor integrated circuit device, compared to the case where the clock generation circuit is formed centrally at the corners, Since it is possible to equalize and shorten the wiring length that connects the clock generation circuit and the circuits driven by it, it is possible to reduce the difference in signal transmission time and reduce the wiring capacitance and the like.

Therefore, since the signal transmission speed can be increased,
The operating speed of the semiconductor integrated circuit device can be increased.

[Embodiment II] This embodiment shows an example in which a unit block capable of forming a clock generation circuit or the like that requires a large current is arranged in a different arrangement from that of the embodiment I.

FIG. 5 is a schematic enlarged plan view of essential parts of a semiconductor integrated circuit device for explaining an embodiment II of the present invention.

In FIG. 5, 10A is the wiring 8 as in the first embodiment.
A plurality of unit blocks provided under C and 9B, for example, for forming a clock generation circuit or the like that requires a large current.

This unit block 10A is designed to facilitate the formation of the CMIS well region, so that the MISFETs Qp, Qn and the MISF can be easily formed.
ETQP and QN are formed in substantially the same direction,
A plurality of them are arranged in the row direction.

As described above, according to this embodiment,
It is possible to obtain substantially the same effect as.

[Effects] As described above, according to the novel technical means disclosed in the present application, the effects can be obtained as described below.

(1) A second reference voltage wiring having a wiring width larger than that of the first reference voltage wiring extending substantially in the same direction as the unit block row is provided in a central portion substantially orthogonal to the unit block row, A plurality of unit blocks are provided under the second reference voltage wiring, a clock generation circuit or the like requiring a large current is configured in the unit block, and sufficient wiring is obtained by using the second reference voltage wiring. Since it has a width, the influence of migration can be reduced.

(2) Because of the above (1), it is possible to prevent the disconnection of the wiring, prevent the shortening of the life, etc., so that the electrical reliability of the semiconductor integrated circuit device can be improved.

(3) When the clock generating circuit or the like is formed in the central portion of the semiconductor integrated circuit device by arranging the clock generating circuit or the like in the central portion of the semiconductor integrated circuit device regardless of whether the automatic placement and routing system is used or not. On the other hand, since the wiring length connecting the clock generation circuit and the circuits driven by it can be made uniform and shortened, the difference in signal transmission time can be reduced and the wiring capacitance and the like can be reduced.

(4) Since the signal transmission speed can be increased by the above (3), the operation speed of the semiconductor integrated circuit device can be increased.

(5) Due to the above (2) and (1), the electrical reliability of the semiconductor integrated circuit device can be improved and the operating speed thereof can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Of course, you can do that.

For example, the above embodiment uses the semiconductor integrated circuit device having the unit block capable of forming the 3-input NAND gate circuit, but has the unit block capable of forming the 2-input NAND gate circuit. A semiconductor integrated circuit device may be used.

Further, in the above-mentioned embodiment, the unit block column has two rows, and one set of reference voltage wirings (reference voltages V _SS and V _DD ) orthogonal to and extending in the central portion is provided, but the unit block has three rows. It is also possible to provide two sets of reference voltage wirings that are orthogonal to each other and extend in the respective central portions.

Further, although the unit block is composed of CMIS in the above embodiment, the unit block may be composed of p-channel or n-channel MISFET.

Further, although the unit block is formed of a plurality of semiconductor elements in the above embodiment, the unit block may be formed of one semiconductor element.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a semiconductor integrated circuit device adopting a master slice method for explaining an embodiment I of the present invention, and FIG. 2 is a schematic enlarged plan view of essential parts of FIG. FIG. 3 is a circuit diagram showing a clock generation circuit for explaining an embodiment I of the present invention, and FIG. 4 is a schematic main part of a semiconductor integrated circuit device when the clock generation circuit of FIG. 3 is configured. FIG. 5 is an enlarged plan view of a semiconductor integrated circuit device for explaining a second embodiment of the present invention. In the figure, 1 ... Semiconductor integrated circuit device, 2 ... External input / output terminal, 3 ... Input / output circuit, 4, 10, 10A ... Unit block, 5 ... Element isolation insulating film, 6 ... Unit block Row, 7 ... Wiring area, 8A, 8B, 8C, 8D, 9A,
9B, 9C ... Wiring, 11 ... Unit block row, 12 ...
… Clock generator, 12A… NAND gate circuit,
12B to 12E ... Inverter circuit, Qp, Qn, Q
N, QP ... MISFET.

Claims (2)

[Claims] 1. An external input / output terminal, and an input / output circuit provided between the external input / output terminal and an internal integrated circuit for controlling the level of a signal input to the external input / output terminal.
A first unit block including a predetermined number of transistors, and a first unit block column including a plurality of the first unit blocks arranged in the column direction and a plurality of first unit blocks arranged in the row direction at predetermined intervals. And a wiring area provided for setting a logical function by changing a wiring pattern provided between the first unit block rows, and a direction substantially the same as the first unit block row on the first unit block row. A first reference voltage line that extends to the first unit block row and is provided on the first unit block row and extends in substantially the same direction as the first unit block row. A second reference voltage wiring to which a second voltage is supplied, and a predetermined number of wirings which are provided on an extension line of the first unit block row and extend in a direction substantially orthogonal to the first unit block row. Composed of transistors A second unit block column, a second unit block column formed by arranging a plurality of the second unit blocks in the row direction, and a first voltage provided on the second unit block column. A semiconductor integrated circuit device comprising: a third reference voltage wiring for supplying; and a fourth reference voltage wiring for supplying a second voltage, which is provided on the second unit block row. Of the unit block row, the first voltage is supplied to the clock circuit by the third reference voltage wiring, and the second voltage is supplied to the fourth circuit. A semiconductor integrated circuit device, characterized in that wiring is performed for a reference voltage. 2. The third to fourth reference voltage wirings are formed with a wiring width larger than that of the first or second reference voltage wirings. 2. The semiconductor integrated circuit device according to item 1.