JPH03276656A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To test a plurality of chip regions simultaneously irrespective of the number of electrodes inside the chip regions by a method wherein a probe card is formed of a substrate and of a plurality of probe needles planted and installed around respective probe centers. CONSTITUTION:Electrodes 52 inside chip regions 51 arranged in a matrix shape are provided with probe cards 6 used to position probe needles 41 for test use. The probe cards 6 are formed of the following: a substrate 62 on which a plurality of probe centers 61 corresponding to centers of the chip regions 51 are installed so as to sandwich at least one chip region 51; and a plurality of probe needles 41 planted and installed around the respective probe centers 61. Consequently, chip regions which have been held by a plurality of wafer chucks 31 and which have been formed in the same place as a plurality of wafers 5 can be tested at the same time; the number of chip regions which can be tested at the same time is definite irrespective of the chip regions to be tested.

Description

[Detailed Description of the Invention] [Summary] Regarding the structure of a semiconductor testing device for measuring the characteristics of a semiconductor chip before cutting, especially a probe card for simultaneously conducting multiple tests, a probe card with multiple probe needles equivalent to a single type is provided. The purpose of this test is to provide a semiconductor test equipment equipped with a multi-type probe card, which is installed in the probe center of the probe center and can simultaneously test a larger number of chip areas than conventional probe cards. a substrate having a probe card for positioning a test probe needle to an electrode within the substrate, and a plurality of probe centers corresponding to the center of the chip area are provided sandwiching at least one chip area; A probe card 6 is configured to be formed by a plurality of probe needles implanted around a probe center.

[Industrial Field of Application] The present invention relates to a semiconductor testing device for measuring the characteristics of a semiconductor chip before cutting, and particularly to the structure of a probe card for simultaneously conducting a plurality of tests.

A semiconductor device is subjected to a characteristic test on all semiconductor chips before cutting, and in such a characteristic test, as a means of positioning a test probe needle to an electrode within the chip area,
Generally, a probe card is used, which has probe needles embedded in a substrate.

However, conventional probe cards are configured to test one chip area or multiple chip areas with a small number of electrodes, and such probe cards are required for testing recent large wafers with significantly increased chip areas. Using cards requires a long time to test one wafer.

Therefore, there is a need for the development of a test device equipped with a multi-probe card that can simultaneously test multiple chip areas regardless of the number of electrodes within the chip area.

[Conventional technology]

FIG. 4 is a side sectional view showing the main parts of a conventional semiconductor testing device, FIG. 5 is a plan view showing chip areas arranged on a wafer, and FIG. 6 is a perspective view showing a conventional probe card.

In Fig. 4, the conventional semiconductor test equipment is LSI tester 1.
, a test head 2, and a blower main body 3, and the LSI tester 1 and the test head 2 are connected by a signal cable 11.

The test head 2 also has a probe card 4 in which a probe needle 41 is implanted, and the prober body 3 includes a wafer chuck 31 that holds the wafer 5 and an XY child table 2 that moves the wafer chuck 31. There is.

As shown in FIG. 5(a), a plurality of chip regions 51 are arranged in a matrix on the wafer 5.
A plurality of electrodes 52 are formed along each side as shown in FIG. 5(b). Further, the probe card 4 is usually configured such that a plurality of probe needles 41 are implanted on a substrate 42 as shown in FIG. ing.

Modern LSI testers have the ability to test multiple chip areas simultaneously. However, the single type probe card shown in FIG. 6(a) has a problem in that only one chip area can be tested at a time. Therefore, a multi-type probe card shown in FIG. 6(b) has been proposed. That is, two probe centers 43 corresponding to the centers of diagonally adjacent chip regions are provided on the substrate 42, and the tips of the probe needles 41 planted around the probe centers 43 are located at the centers of the respective chip regions. It is configured to come into pressure contact with the electrode.

[Problem to be solved by the invention]

However, the method of providing probe centers corresponding to the centers of adjacent chip areas on a substrate is limited to two, and furthermore, the positions where probe needles can be implanted on the substrate are limited.
It cannot be applied to chip area tests that require 100 or more probe needles.

Furthermore, when testing a chip area arranged at the edge of a wafer, one probe needle often comes into contact with an area outside the chip area on the wafer, resulting in a problem of low efficiency even with multi-type probe cards. Ta.

The object of the present invention is to provide a semiconductor testing device equipped with a multi-type probe card, in which probe needles equivalent to single-type probes are installed in multiple probe centers, and the number of chip areas that can be tested simultaneously is larger than that of conventional probe cards. Our goal is to provide the following.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of a semiconductor testing device according to the present invention.

The same objects are represented by the same symbols throughout the figures.

The above problem involves chip areas 51 arranged in a matrix.
A plurality of probe centers 61 corresponding to the center of the chip area 51 are provided with at least one chip area 51 sandwiched therebetween. board 62
This is achieved by the semiconductor testing apparatus of the present invention in which the probe card 6 is formed by the plurality of probe needles 41 implanted around each probe center 61.

[For production]

In FIG. 1, a probe card is provided for positioning probe needles for testing on electrodes in a chip area arranged in a matrix, and a plurality of probe centers corresponding to the center of the chip area are connected to at least one The semiconductor testing device of the present invention includes a probe card formed by a substrate sandwiching a chip area and a plurality of probe needles implanted around each probe center.
There is no limit to the number of probe centers provided on a single board, and three or four chip areas can be tested simultaneously depending on the capabilities of the LSI tester.

Also, like the single type probe card, there are no restrictions on the implantation position of the probe needles (it is also possible to test chip areas that require 100 or more probe needles. In other words, multiple probe needles equivalent to the single type probe card can be tested). It is possible to realize a semiconductor testing device equipped with a multi-type probe card, which is installed in a probe center of the present invention and can simultaneously test a larger number of chip areas than conventional probe cards.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a side sectional view showing the main parts in one embodiment of the present invention, and FIG. 3 is a side sectional view showing the main parts in another embodiment of the invention.

As shown in FIG. 2, one embodiment of the semiconductor testing device according to the present invention is composed of an LSI tester 1, a test head 2, and a prober body 3, and a signal cable is connected between the LSI tester 1 and the test head 2. It is connected by 11. The prober body 3 incorporates a plurality of wafer chucks 31 that hold wafers 5 and an XY child table 2 that moves a plurality of wafer chunks 31 simultaneously.

The test head 2 has a multi-type probe card 6 shown in FIG. It is formed of a plurality of probe needles 41. Note that the probe card 6 used in one embodiment of the present invention has a probe center 61
The interval is equal to the arrangement pitch of the wafer chucks 31.

The semiconductor testing apparatus having such a configuration can simultaneously test chip regions formed at the same location on a plurality of wafers 5 held by a plurality of wafer chucks 31, and can simultaneously test chip regions formed at the same location on a plurality of wafers 5 held by a plurality of wafer chucks 31, regardless of the positions of the chip regions to be tested. The number of chip areas tested is constant. Furthermore, the respective probe centers 61 are provided at intervals, and probe needles equivalent to those of the single type can be implanted around the probe centers 61.

As shown in FIG. 3, another embodiment of the semiconductor testing device according to the present invention is composed of an LSI tester 1, a test head 2, and a prober main body 3. They are connected by a signal cable 11. The probe car 3 includes one wafer chuck 31 that holds the wafer 5 and an XY child table 2 that moves the wafer chuck 31.

The test head 2 has a multi-type probe card 6 shown in FIG. probe needle 4
It is formed by 1. Note that the probe card 6 used in other embodiments of the present invention is provided with a probe center 61 with at least one chip area in between.

A semiconductor test device having such a configuration can test three or four chip areas at the same time, and since each probe center 61 is provided at intervals, a probe needle equivalent to a single type is placed around the probe center 61. can be planted.

The probe card has a probe card for positioning test probe needles on the electrodes in the chip area arranged in a matrix, and has at least one plurality of probe centers corresponding to the center of the chip area. In the semiconductor test device of the present invention, a probe card is formed by a substrate sandwiching a chip area between the substrates and a plurality of probe needles implanted around each probe center. There is no limit to the number of probe centers provided above, and three or four chip areas can be tested simultaneously depending on the capabilities of the LSI tester.

Also, like the single type probe card, there is no limitation on the implantation position of the probe needles, and it is possible to test a chip area that requires 100 or more probe needles. In other words, a semiconductor testing device equipped with a multi-type probe card is realized, in which probe needles equivalent to a single-type probe are installed in multiple probe centers, and the number of chip areas that can be tested simultaneously is larger than that of a conventional probe card. be able to.

(Effects of the Invention) As described above, the present invention includes a multi-type probe card in which a probe needle equivalent to a single-type probe needle is installed in each probe center, and the number of chip areas that can be tested simultaneously is greater than that of conventional probe cards. A semiconductor test device can be provided.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of a semiconductor testing device according to the present invention, Fig. 2 is a side cross-sectional view showing the main parts in one embodiment of the invention, and Fig. 3 is a diagram showing the main parts in another embodiment of the invention. Fig. 4 is a side sectional view showing the main parts of a conventional semiconductor testing device; Fig. 5 is a plan view showing chip areas arranged on a wafer; Fig. 6 is a perspective view showing a conventional probe card. Figure. In the figure, 1 is an LSI tester, 2 is a test head, 3 is a prober body, 5 is a wafer, 6 is a probe card,
11 is a signal cable, 31 is a wafer chuck, 32 is an XY child table 41 is a probe needle, 51 is a chip area, 52 is an electrode, 61 is a probe center, and 62 is a substrate. A Principle diagram of a cattle support system used as a food sentinel Diagram A practical example of the present invention (= Showing 11 houses in the sky, half 4 of the T-cho-men-zu-zu-zu-zu technique is combined with the t-hei of Hirohiro, g1 cross-sectional figure (θ) (1)) Uniha upper i4+e example Seri A ÷ Preparation 2! Child side map number 6
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Claims (1)

[Claims] It has a probe card (6) for positioning probe needles (41) for testing on electrodes (52) in a chip area (51) arranged in a matrix, and a probe card (6) is provided for positioning probe needles (41) for testing. Multiple probe centers (6
1) comprises a substrate (62) provided with at least one chip region (51) in between, and a plurality of probe needles (41) implanted around each probe center (61). A semiconductor testing device characterized in that the probe card (6) is formed.