CN211856812U - Chip testing machine and testing board - Google Patents
Chip testing machine and testing board Download PDFInfo
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- CN211856812U CN211856812U CN202020293234.0U CN202020293234U CN211856812U CN 211856812 U CN211856812 U CN 211856812U CN 202020293234 U CN202020293234 U CN 202020293234U CN 211856812 U CN211856812 U CN 211856812U
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Abstract
The utility model discloses a chip testing machine and a test board, wherein, a chip testing machine, with the test board phase-match uses for the wafer that awaits measuring of test, including the test machine body, be provided with a plurality of integrated circuit boards in the test machine body, to the wafer that awaits measuring provides test signal, is used for detecting the wafer that awaits measuring; the test head is arranged on the tester and is provided with an annular area, the annular area is distributed into a plurality of test areas at equal intervals, and the board cards are arranged in the test areas; the spring pins are arranged on the test area and are electrically connected with the board cards corresponding to the test area; during testing, the paths from the wafer to be tested placed in the center of the annular area to any one of the test areas are equal in length, when the wafer to be tested is placed on the test board, the signal from the wafer to be tested to each test area is consistent with the path of power supply wiring, and the consistency of multi-path signal design and the consistency of multi-path power supply design are guaranteed.
Description
Technical Field
The utility model relates to a chip test machine technical field especially relates to a chip test machine and survey test panel.
Background
In the chip testing process, the requirement on the consistency of signals and power supplies is high, different power supplies and different signal designs are different, the design is limited by the relative positions of pins of the signals and the power supplies in a chip pin diagram, and the design is also related to the machine resource allocation selected by a customer.
In a conventional wafer test, a timing problem is introduced, and a tester needs to perform timing calibration to perform a normal test, but the calibration effect is general.
SUMMERY OF THE UTILITY MODEL
The utility model discloses to solve among the prior art the wafer that awaits measuring and produce the technical problem of earlier chronogenesis to the inconsistent route in test area, provide a chip test machine and survey test panel.
The utility model provides a technical scheme as follows:
a chip tester, used in conjunction with the test board, for testing a wafer to be tested, includes:
the wafer testing device comprises a testing machine body, wherein a plurality of board cards are arranged in the testing machine body, and are used for providing testing signals for the wafer to be tested and detecting the wafer to be tested;
the test head is arranged on the tester body and provided with an annular area, the annular area is distributed into a plurality of test areas at equal intervals, and the board cards are arranged in the test areas;
the spring pins are arranged on the test area and are electrically connected with the board cards corresponding to the test area;
during testing, the paths of the wafer to be tested placed in the center of the annular area to any one of the test areas are equal in length.
In the scheme, the test areas of the test head are distributed into a plurality of test areas in a ring shape at equal intervals, the spring pins are designed in the test areas, so that the test machine body can provide test signals like the spring pins, in the scheme, each test area corresponds to different board cards to provide different test signals for each test area, each spring pin is in contact with the test board to transmit the test signals to the test board and further to the wafer to be tested to test the wafer to be tested, in the actual test process, the wafer to be tested is positioned at the test center of the test head, so that the path of the wafer to be tested to each test area is consistent, the various test signals transmitted to the wafer to be tested by each test area are consistent, the test result is more accurate, the time sequence problem caused by the inconsistent paths is solved, even if different board cards are used, the test points corresponding to the test areas on the wafer to be tested can be tested by corresponding to each test point on the test board and the test area, the test can be performed by changing the direction of the wafer to be tested without changing the tester itself.
Preferably, different test areas are provided with different boards for providing test signals to each test area.
Preferably, the central position of the annular region is a hollow structure, each test zone is a fan-shaped structure, and a spacing groove is formed between every two adjacent test zones.
In the scheme, the spacing groove is arranged between two adjacent test areas, so that each test area can be better separated, and the adjacent test areas cannot be interfered in the test process.
Preferably, the test head is of cylindrical configuration.
In this scheme, through setting the test head to cylindrical structure to make placing that can be better when the test survey the board, simultaneously also can be better with waiting to become a plurality of required test areas on the test head.
Preferably, the number of test zones is eight.
A test board is used in cooperation with the chip testing machine, a probe is arranged at the center of the test board and used for testing the wafer to be tested, and the test board can be in contact with the spring pins so that the testing machine is electrically communicated with the test board.
In this scheme, survey test panel and test head phase-match, be provided with the signal connection region corresponding with the test area on the test panel, through fixing the test panel in the spring needle region to make the spring needle can transmit the signal in the test machine to the test panel, thereby further transmit for the wafer that awaits measuring through the test panel, and the wafer that awaits measuring can contact with the central part of test panel in order to realize the test, thereby makes the wafer that awaits measuring to walk the line unanimity with the power in each test area's signal.
Preferably, the test board comprises a base substrate, a connecting sheet and a probe, and the base substrate is matched with the test head. The connecting piece is connected to the center of the substrate. One end of each probe is connected to the connecting piece, and the other end of each probe is in contact with the wafer to be tested and used for testing the wafer to be tested.
Preferably, the probe is matched with a point to be measured of the wafer.
Compared with the prior art, the utility model provides a pair of chip test machine and survey test panel have following beneficial effect:
the utility model discloses a regional annular equidistance to the spring pin place distributes into a plurality of the same test areas, every test area is used for testing different signals, the test area that the spring pin is located is isometric to central point position route, when placing the wafer that awaits measuring on the test board, the wafer that awaits measuring this moment is unanimous to the signal of each test area and the route of power line, guarantees multichannel signal design uniformity, the uniformity of multichannel power design, make when beginning the test at the same time, can not produce the chronogenesis problem; meanwhile, in the testing process, the signal time sequence does not need to be calibrated; and when testing signals, inserting loss of multiple paths of signals and the like.
Drawings
The above features, technical features, advantages and implementations of a chip tester and a test board will be further described in the following detailed description of preferred embodiments in a clearly understandable manner, with reference to the accompanying drawings.
FIG. 1 is a schematic structural diagram of a test head according to the present invention;
FIG. 2 is a schematic structural diagram of the present invention during testing;
the reference numbers illustrate: the test device comprises a test head 100, a test area 101, spring pins 102, a test board 200, a substrate 201, a connecting sheet 202, probes 203 and a wafer 300 to be tested.
Detailed Description
In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.
For the sake of simplicity, only the parts relevant to the invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
According to the utility model provides a pair of embodiment, as shown in FIG. 1, a chip testing machine, with survey test panel 200 phase-match and use for the wafer 300 that awaits measuring of test, include: the testing machine comprises a testing machine body 201, a testing head 100 and a spring needle 102 arranged on the testing head 100, wherein the testing machine body 201 is used for providing a testing signal for a wafer 300 to be tested and detecting the wafer 300 to be tested; the test head 100 is arranged on a testing machine, the test head 100 is provided with an annular area, and the annular area is equidistantly distributed into a plurality of test areas 101; the pogo pins 102 are arranged in the test areas 101 and electrically connected to the tester body 201, wherein during testing, the paths from the wafer 300 to be tested, which is placed in the center of the ring-shaped area, to any test area 101 are equal in length, and during specific implementation, different board cards are placed in the tester corresponding to each test area 101 and connected to each test signal, so that when the test board 200 is fixed on the test head 100 during testing, the corresponding signal connection area on the test board 200 is matched with the corresponding test area 101 on the test head 100, so that during testing, even if different board cards are used, the corresponding test signal area on the board cards can be connected to the corresponding test area 101, thereby ensuring that the signals from the wafer 300 to be tested to each test area 101 are consistent with the power supply routing when testing the wafer 300 to be tested, when the wafer 300 to be tested is tested at the same time, the signal receiving time from different spring pins 102 to the wafer 300 to be tested is consistent, so that the timing problem does not exist, the testing paths can be ensured to be consistent when users with different board cards test the same chip, and the wafer 300 to be tested is only changed in direction; for a large number of parallel signals, the design can also ensure that the signal paths have the same electrical performance, including insertion loss, return loss and other indexes. This is mainly because the layout ensures that all designs are from the center to the edge of the circle, i.e. a distance substantially equal to the radius of the circle; in this embodiment, the specific shape of the test head 100 is not limited, and it is only required that the test area 101 on the test head 100 can be equally divided into a plurality of identical test areas 101, so that the signal paths from each test area to the middle wafer 300 to be tested are consistent.
In another embodiment of the present invention, referring to fig. 1 again, the test head 100 has a cylindrical structure, the central position of the annular region has a hollow structure, each test region 101 has a fan-shaped structure, and a spacing groove is disposed between two adjacent test regions 101; the number of test areas 101 is eight, when the implementation is concrete, through setting up test head 100 into cylindrical structure, so that can be better when testing place test board 200, simultaneously also can be better wait into a plurality of required test areas 101 with test head 100, through set up the interval groove between two adjacent test areas 101, so that every test area 101 can better separate, so that can not have the interference between the adjacent test area 101 at the in-process of test, set up the locating part near the edge of test area 101 at the interval groove of symmetry, be used for placing the reinforcement, and when specifically using, need test board 200 after reinforcing through the reinforcement, again test wafer 300 that awaits measuring.
A test board 200 is used in cooperation with a tester, a probe 203 is arranged at the center of the test board 200, so that the center of the test board 200 is electrically communicated with a wafer 300 to be tested, the test board 200 can be in contact with a spring pin 102, the tester can be electrically communicated with the test board 200, the test board 200 is matched with a test head 100, each test area on the test board 200 corresponds to a test area 101, even if different board cards are used, only the test area 101 is replaced, the direction of the wafer 300 to be tested is tested, the final test result is consistent, so that the consistency of the multi-path signal design and the multi-path power supply design is ensured, the relation of insertion loss of multi-path signals and the like time sequence is ensured during testing, and the signal time sequence does not.
Specifically, the test board 200 includes a substrate 201, a connecting sheet 202, and a plurality of probes 203; the substrate 201 is provided with test pins which are matched with the region where the pogo pins 102 on the test head 100 are located, and the substrate 201 is matched with the test head 100; the connecting sheet 202 is connected to the center of the substrate 201, and the connecting sheet 202 is electrically communicated with the body of the substrate 201, so that when the substrate 201 is contacted with the pogo pins 102 in different areas, the test signals from different test areas 101 to the connecting sheet 202 are consistent; one end of each probe 203 is connected to the connecting sheet 202, and the other end of each probe 203 is in contact with the wafer 300 to be tested and used for testing the wafer 300 to be tested. The probe 203 is matched with a point to be measured of the wafer circle 300 to be measured.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A chip tester, used in conjunction with a test board, for testing a wafer to be tested, includes:
the wafer testing device comprises a testing machine body, wherein a plurality of board cards are arranged in the testing machine body, and are used for providing testing signals for the wafer to be tested and detecting the wafer to be tested;
the test head is arranged on the tester body and provided with an annular area, the annular area is distributed into a plurality of test areas at equal intervals, and the board cards are arranged in the test areas;
the spring pins are arranged on the test area and are electrically connected with the board cards corresponding to the test area;
during testing, the paths of the wafer to be tested placed in the center of the annular area to any one of the test areas are equal in length.
2. The chip tester according to claim 1, wherein: different test areas are provided with different boards for providing test signals to each test area.
3. The chip tester according to claim 1, wherein: the central position of the annular area is of a hollow structure, each test area is of a fan-shaped structure, and a spacing groove is formed between every two adjacent test areas.
4. The chip tester according to claim 3, wherein: the test head is of a cylindrical structure.
5. The chip tester according to any one of claims 1 to 4, wherein: the number of test zones is eight.
6. A kind of test board, cooperate with any said chip tester of 1-5 to use, characterized by that: and a probe is arranged at the center of the test board and used for testing the wafer to be tested, and the test board can be in contact with the spring needle so as to electrically communicate the test machine with the test board.
7. A test plate according to claim 6, wherein: the test plate comprises a base:
the testing device comprises a substrate, a testing head and a testing device, wherein a testing pin is arranged on the substrate and is matched with a spring needle area on the testing head;
the connecting sheet is connected to the center of the substrate;
and one end of the probe is connected to the connecting piece, and the other end of the probe is in contact with the wafer to be tested and is used for testing the wafer to be tested.
8. A test plate according to claim 7, wherein: the probe is matched with the point to be measured of the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020293234.0U CN211856812U (en) | 2020-03-11 | 2020-03-11 | Chip testing machine and testing board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020293234.0U CN211856812U (en) | 2020-03-11 | 2020-03-11 | Chip testing machine and testing board |
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| CN211856812U true CN211856812U (en) | 2020-11-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115128312A (en) * | 2022-07-14 | 2022-09-30 | 法特迪精密科技（苏州）有限公司 | Distributed high-power test socket suitable for radio frequency module |
| CN116821045A (en) * | 2023-08-28 | 2023-09-29 | 悦芯科技股份有限公司 | Board card structure for testing 512DUT memory device |
-
2020
- 2020-03-11 CN CN202020293234.0U patent/CN211856812U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115128312A (en) * | 2022-07-14 | 2022-09-30 | 法特迪精密科技（苏州）有限公司 | Distributed high-power test socket suitable for radio frequency module |
| CN115128312B (en) * | 2022-07-14 | 2024-04-02 | 法特迪精密科技（苏州）有限公司 | Distributed high-power test socket applicable to radio frequency module |
| CN116821045A (en) * | 2023-08-28 | 2023-09-29 | 悦芯科技股份有限公司 | Board card structure for testing 512DUT memory device |
| CN116821045B (en) * | 2023-08-28 | 2023-11-14 | 悦芯科技股份有限公司 | Board card structure for testing 512DUT memory device |
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