CN117555738B

CN117555738B - DPS power supply board for memory FT test

Info

Publication number: CN117555738B
Application number: CN202410025972.XA
Authority: CN
Inventors: 薛如军; 徐茂强
Original assignee: Yuexin Technology Co ltd
Current assignee: Yuexin Technology Co ltd
Priority date: 2024-01-09
Filing date: 2024-01-09
Publication date: 2024-04-05
Anticipated expiration: 2044-01-09
Also published as: CN117555738A

Abstract

The invention discloses a DPS power supply board for a memory FT test, which belongs to the technical field of chip test and specifically comprises the following components: the power supply module is used for converting the power supply provided by the test machine into a plurality of different voltage power supplies; the CPU module is used for configuring the programs of all the FPGAs after power-on, receiving the instruction of the upper computer, forwarding the instruction to all the FPGAs, and reading the summarized state and the test result; the control module is used for forwarding the signal instruction sent by the CPU module to other modules after the configuration file is burnt; the program loading module is used for sending the ID to the CPU module according to hardware setting, configuring the IP according to the ID by the CPU module, and upgrading the program of the control module; the analog-to-digital conversion module is used for acquiring analog signals and performing analog-to-digital conversion; the calibration module is used for calibrating the voltage and the current of the output resource in the power panel card; and the DPS module is used for outputting, measuring and controlling the test signals.

Description

DPS power supply board for memory FT test

Technical Field

The invention relates to the technical field of chip testing, in particular to a DPS power supply board for FT testing of a memory.

Background

The DDR memory FT test is the last checkpoint before leaving the factory of the DDR memory chip, and the object of the test is aimed at the packaged chip. The method comprises a read-write test, a data integrity test, a delay test, a time sequence test and a capacity test; by performing the DDR memory FT test, it is possible to find out a defective or defective component in the memory module in advance and ensure reliability and stability thereof in practical use. This is important for various application fields such as computer systems, servers, mobile devices, etc.

The current DDR memory chip FT test has the following requirements or problems:

1. only in a specific high-speed test mode, a large current (3-5A) is required, in addition, the current demand of the chip is not large, and the power panel card is required to be compatible with the current output capacity;

2. the whole machine of the tester is usually limited in size, and a large number of digital cards are required to cause the tester to be incapable of being inserted into excessive power cards, so that a single power card needs to have a high channel number, and higher parallel measurement cannot be realized;

the DDR particle test circuit is required to be loaded with a certain number of capacitors with large capacitance values so as to ensure the stability of test power supply current, and the Socket board is usually limited in space, too many large capacitors cannot be arranged, and a board card is required to provide support;

4. when some DDR particle test items are performed, large capacitors are required to be disconnected to ensure the accuracy of the test items and reduce the test time, but the control resources generally available on a Socket Board are very limited.

Disclosure of Invention

The invention aims to provide a DPS power supply board for a memory FT test, which solves the following technical problems:

the current output range of the existing power panel card is smaller, the number of tests is limited, and most test scenes cannot be met due to limited space.

The aim of the invention can be achieved by the following technical scheme:

the DPS power panel card for the memory FT test comprises a power module, a CPU module, a control module, a program loading module, an analog-to-digital conversion module, a calibration module, a channel output connector, a power input connector, a communication connector and a DPS module, wherein:

the power supply module is used for converting the 48V direct current power supply provided by the test machine into a plurality of voltage power supplies with different specifications and supplying power to the whole power board;

the CPU module is used for configuring the programs of all the FPGAs after power-on, receiving the instructions of the upper computer, forwarding the instructions to all the FPGAs, and reading the summarized state and the test result back to the upper computer;

the control module is used for sending a signal instruction to other modules through the CPU module after the configuration file is burnt;

the program loading module is used for sending the ID to the CPU module according to the hardware setting, the CPU module configures the IP according to the ID, and the CPU module upgrades the program of the control module through the program loading module;

the analog-to-digital conversion module is used for acquiring analog signals and carrying out analog-to-digital conversion, and the whole power panel card comprises 4 analog-to-digital conversion modules which are in one-to-one correspondence with the DPS modules;

the calibration module is used for calibrating the voltage and the current of the output resource in the power panel card;

the DPS module is used for outputting, measuring and controlling test signals and comprises 136 channels, each 34 channels are divided into a group, adjacent channels are connected in parallel, and at most 16 groups of continuous channels are connected in parallel and used for providing output and measurement of 1.2Ax16 current.

As a further scheme of the invention: the power panel card measures the process of the device to be measured:

after the program loading module is powered on, loading codes from the flash, and after loading is completed, loading the program of the control module by the CPU module through the program loading module;

the control module processes the pre-output signal instruction, the control module sends the signal instruction to the DPS module, the DPS module outputs corresponding output signals according to the fresh instruction, the output signals comprise voltage signals and current signals, and the DPS switch devices of the corresponding channels are closed to transmit the output signals to the device to be tested through the output connector;

the sampling signal of the device to be tested, which is acquired by the output end of the DPS module, is transmitted to the analog-to-digital conversion module, the analog-to-digital conversion module carries out analog-to-digital conversion on the sampled signal, the analog-to-digital converted signal is transmitted to the control module, and the control module transmits the signal measurement result to the CPU through the PCIE protocol and displays the signal measurement result in the workstation.

As a further scheme of the invention: the DPS module comprises AD5560 and AD7608;

the AD5560 is internally integrated with 16-bit DAC chips, wherein each DAC chip is used for setting the level required by the programmable input and comprises an output unit and a measuring unit; AD5560 includes clamp and comparator circuits, also including offset and gain correction of the DAC; AD5560 is also used to provide 5 internal programmable measured current ranges and two external selectable current ranges that provide currents up to ±1.2A and ±0.5A, respectively;

the AD7608 includes an 8-channel differential DAS and 18-bit bipolar synchronous sampling.

As a further scheme of the invention: the calibration module specifically comprises:

the calibration circuit includes 4 parts: channels 0-31 and 128-129, channels 32-63 and 130-131, channels 64-95, channels 132-133, channels 96-127 and channels 134-135, wherein the number of channels of each part is identical and is uniformly distributed in 4 groups of ADCs, the ADCs are arranged in an analog-to-digital conversion module, and each channel is switched by a relay arranged on an output pin of a DPS module;

the calibration circuit of the 4 parts is commonly used with a group of calibration resistors Range0-Rnage7, the calibration resistors are switched through a relay, the current Range of Rnage 0-Range6 is +/-5uA gear to +/-1.2A gear, and the calibration circuit is used for realizing the calibration flow inside a single board by controlling the on-off of the relay, wherein Rnage7 is only used for applying voltage measurement voltage during calibration;

the calibration circuit also reserves an external DVM interface, and performs a calibration flow through the external DVM.

As a further scheme of the invention: the calibration flow is as follows:

s1, ADC calibration: the DPS module is internally provided with 3.0V reference voltage, ADC acquisition reference voltage and AGND voltage, the ADC acquisition reference voltage and the AGND voltage are respectively marked as dependent variables y1 and y0, the control module reads the conversion digital quantity of the ADC acquisition voltage, the conversion digital quantity is respectively marked as independent variables x1 and x0, and a Gain value ADC Gain and a deviation value ADC Offset are calculated according to the following formula:

；

wherein the standard value of Offset is 0 and the standard value of gain is 1;

s2, CAL_sensor line calibration: the CAL_S line is switched by a relay, the voltage values of VREF_CAL and GND are read and marked as dependent variables v1 and v0, the voltage values are sent to a calibrated ADC for analog-to-digital conversion, the control module reads the converted digital quantity of the ADC acquisition voltage and marked as independent variables u1 and u0, and a Gain value CAL_S Gain and an Offset value CAL_S Offset are calculated according to the following formula:

；

s3, DPS calibration: the Voltage measurement circuit comprises an applied Voltage measurement Voltage calibration VFVM and an applied Voltage measurement current calibration VFIM, wherein the applied Voltage measurement Voltage calibration comprises a Voltage Force calibration and a Voltage Sense calibration, the Voltage Force calibration is used for judging whether the output Voltage of the DPS module is accurate, and the Voltage Sense calibration is used for judging whether the Voltage Sense Voltage is accurate.

As a further scheme of the invention: the specific process of voltage measurement and voltage calibration applied in S3 is as follows:

the DPS module outputs-0.4V and 3.2V voltages through Force lines, the voltage is output through voltage MEASOUT of the DPS module, the voltage is sent to a calibrated ADC through a multiplexer, the control module reads the converted digital quantity of the acquired voltage of the ADC, the calibrated CAL_Sense line senses and acquires the voltage at the front end of the Rnage7 resistor, the voltage sensed on the CAL_Sense is also sent to the ADC, and finally the voltage reaches the control module and is converted;

marking two Voltage values set by a DPS chip as dependent variables n1 and n0 respectively, marking a perceived value of CAL_Sense as independent variables m1 and m0, and calculating a Gain value VFGain and a deviation value VFOffset of a Voltage Force; the formula is:

；

obtaining a preset test voltage of a device to be tested, multiplying the preset test voltage by VFGain and adding VFOffset to obtain an input voltage value, and writing the input voltage value into an internal register of the DPS module;

marking the perceived value of CAL_Sense as dependent variables m1 and m0, marking the output value of Voltage MEASOUT as independent variables i1 and i0, and calculating the Gain value VSGain and Offset value VSOffset of Voltage Sense; the formula is:

；

。

as a further scheme of the invention: the specific process of voltage measurement current calibration applied in S3 is as follows:

and switching the output signal of the DPS module into Range0-Range6 through a relay, respectively measuring the CAL_sense sensing value and the current MEASOUT value of each resistor, and respectively calculating the corresponding gain value and the corresponding deviation value.

As a further scheme of the invention: DPS calibration also included Current Clamp calibration:

the Current Clamp calibration includes a Clamp Low calibration and a Clamp High calibration, the Current Clamp values are set by corresponding DACs, and the gain values and the bias values of the Clamp Low and the Clamp High are calculated by using the set values of the Clamp Low and the Clamp High as dependent variables and the cal_sense path Sense value or the measurement_i path output value as independent variables.

The invention has the beneficial effects that:

the invention has 136 paths of independent test channels, the single-channel voltage range is-1.5V-4V, the maximum current can reach +/-1.2A, the signal output range is wide, 12 PSU136 slots are arranged, the total number of power channels is 12x136 = 1632, and the requirement of simultaneously testing power supply of 512 DUTs can be met, thereby reducing the test time; the 136 channels can be started from any position channel, and 16 channels are continuously connected in parallel, so that the maximum current of 1.2Ax16 is provided, and most of test scenes can be met; the large capacitor is arranged in the power board, and the switch can be controlled by the control signal in the power board, so that a large amount of space and control resources are saved for the Socket board.

Drawings

The invention is further described below with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of the power supply of the present invention;

FIG. 2 is a schematic diagram of a power panel resource distribution of the present invention;

FIG. 3 is a schematic diagram of a power panel card of the present invention;

FIG. 4 is a schematic diagram of a power panel calibration of the present invention;

FIG. 5 is a schematic diagram of the calibration of a VFVM of the present invention;

FIG. 6 is an exemplary diagram of a calibration coordinate system of the Voltage Force of the present invention;

fig. 7 is a schematic diagram of the calibration of the VFIM of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1-7, the present invention is a DPS power board for testing a memory FT, including a power module, a CPU module, a control module, a program loading module, an analog-to-digital conversion module, a calibration module, a channel output connector, a power input connector, a communication connector, and a DPS module, wherein:

the DPS module is used for outputting, measuring and controlling test signals and comprises 136 channels, wherein each 34 channels are divided into a group, each channel is connected in parallel, and at most 16 groups of continuous channels are connected in parallel and used for providing output and measurement of 1.2Ax16 current;

the signal output and measurement module is used for forming a signal output and measurement circuit by taking the DPS chip as a core, so that the signal output and acquisition and measurement can be performed; the output control module is used for controlling the output and measurement of DPS, the board has 136 channels, each 34 channels are in one group, four groups are in total, and adjacent different channels can be connected in parallel.

In a preferred embodiment of the present invention, the process of measuring the device under test by the power board card is:

The DPS chip AD5560 has FV, MI, MV, FNMV functions, force and Sense functions are independent modules, and Force and Sense are started by instructions. Sense may be measured at the same time as Force is initiated, or may be measured for a period of time selected to be desired. For example, we want to measure the current or voltage level as soon as we give Force, or we can add Sense after we run a specific pattern, so Sense can be added at any time we want, specifically, according to the test requirement.

In another preferred embodiment of the present invention, the DPS module includes AD5560 and AD7608;

compared with the common device, the AD5560 has the characteristics of small volume, low power consumption and high precision, and can integrally improve the performance and the integration level of the whole module.

The AD7608 comprises an 8-channel differential DAS and an 18-bit bipolar synchronous sampling ADC, and the high-precision device ensures the sampling precision and accuracy.

In another preferred embodiment of the present invention, the calibration module specifically includes:

In a preferred case of this embodiment, the calibration procedure is:

s1, ADC calibration: the DPS is internally provided with a 3.0V ultra-low noise and a high-precision reference voltage, the ADC acquires voltages of two points of the reference voltage and the AGND and marks the voltages as dependent variables y1 and y0 respectively, the control module reads the converted digital quantity of the ADC acquired voltage and marks the converted digital quantity as independent variables x1 and x0 respectively, and a Gain value ADC Gain and an Offset value ADC Offset are calculated according to the following formula:

；

wherein the standard value of Offset is 0 and the standard value of gain is 1;

；

s3, DPS calibration: the Voltage measurement method comprises the steps of applying Voltage measurement Voltage calibration VFVM and applying Voltage measurement current calibration VFIM, wherein the Voltage measurement Voltage calibration comprises Voltage Force calibration and Voltage Sense calibration, the Voltage Force calibration is used for judging whether the output Voltage of the DPS module is accurate, and the Voltage Sense calibration is used for judging whether the Voltage of the Voltage Sense is accurate; it should be noted that the Force and Sense calibrations are performed simultaneously.

Referring to fig. 5-7, in fig. 5 and 7, the thickened black line is a path, and in another preferred case of the present embodiment, the specific process of applying the voltage measurement voltage calibration in S3 is as follows:

；

。

Voltage Force：

two values perceived on the CAL_Sset 0 and CAL_Sset 1 sense lines as two points on the abscissa; set0 = -0.4V, set1 = 3.2V, these two values are written in binary form into the DPS chip internal register by FPGA, DPS chip will output the corresponding voltage, this voltage will be given to the calibration resistor through cal_f line, cal_sense will perceive the voltage value at the front end of the calibration resistor when we set DPS internal register to-0.4V and 3.2V, -0.4V and 3.2V as two X-coordinate corresponding points on the ordinate of fig. 7.

Ideally, we consider that the voltage value is written into the DPS internal register, the DPS chip must output the equal voltage value, but in practical situations, the written data will pass through a series of components such as the register, a plurality of groups of operational amplifiers, internal gear resistors, relays, etc., and the final output quantity is not equal to the set value given by us. Furthermore, the DPS output and the DPS input in the DPS chip manual are in a linear relation (the DPS output and the DPS input are not completely linear in practice, but the error is within an acceptable range), so that two set values are given, two corresponding output values are measured, an X-Y curve is fitted, and the slope Gain and the Offset are obtained, and then the value written into the DPS chip register is multiplied by the Gain and then the Offset.

The above figure we give the set values-0.4V and 3.2V, we have the set input value as Y-coordinate and cal_s as X-coordinate; while DVM in the above figure.

The CAL_S line and the ADC are calibrated in the first step and the second step, so that the CAL_S can be identified to accurately read the numerical value, and the ADC can accurately convert the analog quantity into the digital quantity to be sent to the FPGA for processing.

Voltage Sense Calibration:

Above we calibrate the Force line, but the Force line is calibrated externally, but the measurement function of the DPS chip will pass through different paths, and the measurement result will be output through the measurement out pin.

Here we discuss MV mode, we still set Force equal to-0.4V and 3.2V, but the X/Y axis variation is changed, we fit X-Y curves with MEASOUT_V as the X axis and CAL_S as the Y axis, resulting in Gain and Offset.

We get the Gain and offset values by calibration, there are two ways to adjust our DPS inputs, one in software and the other in hardware. The software mode is that when a value is written into the DPS chip, for example, 0x8000 represents 4V voltage, but the value actually written into an internal register of the DPS is processed by software, and the value needs to be multiplied by Gain and added with offset; the hardware mode is that the values of gain and offset are written into an M register and a C register in the DPS chip in advance, and the FPGA directly inputs the 0x8000 value into the DPS internal register to be operated by the DPS chip.

So far, the VFVM is fully calibrated, and the following modes are calibrated, except for the variable setting changes on the X/Y axis.

In another preferred case of the present embodiment, the specific procedure of applying the voltage measurement current calibration in S3 is:

switching an output signal of the DPS module into Range0-Range6 through a relay, respectively measuring a CAL_sense sensing value and a current MEASOUT value of each resistor, and respectively calculating a corresponding gain value and a corresponding deviation value; the parameters of the calibration resistor are shown in the following table:

in another preferred case of the present embodiment, the DPS calibration further includes a Current Clamp calibration:

The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.

Claims

1. The DPS power panel card for the memory FT test is characterized by comprising a power module, a CPU module, a control module, a program loading module, an analog-to-digital conversion module, a calibration module, a channel output connector, a power input connector, a communication connector and a DPS module, wherein:

the control module is used for forwarding the signal instruction sent by the CPU module to other modules after the configuration file is burnt;

the calibration module specifically comprises:

the calibration circuit also reserves an external DVM interface and performs a calibration flow through the external DVM;

the calibration flow is as follows:

；

wherein the standard value of Offset is 0 and the standard value of gain is 1;

；

s3, DPS calibration: the Voltage measurement method comprises the steps of applying Voltage measurement Voltage calibration VFVM and applying Voltage measurement current calibration VFIM, wherein the Voltage measurement Voltage calibration comprises Voltage Force calibration and Voltage Sense calibration, the Voltage Force calibration is used for judging whether the output Voltage of the DPS module is accurate, and the Voltage Sense calibration is used for judging whether the Voltage of the Voltage Sense is accurate;

the specific process of voltage measurement and voltage calibration applied in S3 is as follows:

；

the specific process of voltage measurement current calibration applied in S3 is as follows:

switching an output signal of the DPS module into Range0-Range6 through a relay, respectively measuring a CAL_sense sensing value and a current MEASOUT value of each resistor, and respectively calculating a corresponding gain value and a corresponding deviation value;

2. The DPS power supply board for the memory FT test of claim 1, wherein the power supply board measures the device under test by:

3. The DPS power panel card for the memory FT test of claim 1, wherein the DPS modules include AD5560 and AD7608;

the AD5560 is internally integrated with 16-bit DAC chips, wherein each DAC chip is used for setting the level required by the programmable input and comprises an output unit and a measuring unit; AD5560 includes clamp and comparator circuits, also including offset and gain correction of the DAC; AD5560 is also used to provide 5 internal programmable measured current ranges and 2 external selectable current ranges that provide currents up to ±1.2A and ±0.5A, respectively;

4. The DPS power panel card for the memory FT test of claim 1, wherein the DPS calibration further includes a Current Clamp calibration: