CN107835019B - Factory calibration system and calibration method of high-precision digital-to-analog converter - Google Patents

Factory calibration system and calibration method of high-precision digital-to-analog converter Download PDF

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CN107835019B
CN107835019B CN201710773503.6A CN201710773503A CN107835019B CN 107835019 B CN107835019 B CN 107835019B CN 201710773503 A CN201710773503 A CN 201710773503A CN 107835019 B CN107835019 B CN 107835019B
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dac chip
msb
dac
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CN107835019A (en
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谭博
秦坤
彭新芒
马明朗
张春义
张鑫星
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Mxtronics Corp
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    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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    • H03M1/1009—Calibration

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Abstract

A factory calibration system and a calibration method of a high-precision digital-to-analog converter are disclosed, wherein the calibration system comprises a power supply, a DAC evaluation board to be calibrated, upper computer software, a universal meter, a USB-to-GPIB controller, a USB-to-parallel port controller and a parallel port-to-SPI controller; the DAC evaluation board to be calibrated comprises a reference source circuit, a crystal oscillator, a relay and an FPGA circuit. The calibration method comprises the steps that firstly, a DAC chip to be calibrated is placed on a DAC evaluation board to be calibrated, a relay is controlled by an FPGA to enable a measurement object of the multimeter to be switched between a reference source circuit and the DAC chip to be calibrated, an upper computer controls the DAC to be calibrated to enter a calibration mode through a parallel port-to-SPI (serial peripheral interface) controller, a calibration code is calculated according to the difference value of the output value of the DAC and the MSB ideal value in the calibration mode and fed back to a calibration register of the DAC, calibration is achieved, and static parameters INL and DNL of the DAC chip to be calibrated are calculated until the calibration meets requirements. The invention fills the blank of high-precision digital-to-analog converter calibration and can effectively improve the linearity of the digital-to-analog converter.

Description

Factory calibration system and calibration method of high-precision digital-to-analog converter
Technical Field
The invention designs a factory calibration system and a factory calibration method for a high-precision digital-to-analog converter, and belongs to the technical field of digital-to-analog converters.
Background
In recent years, the demand for high-speed communication systems has increased, and digital-to-analog converters have become more and more important as interface modules for the digital world and the analog world. Because the module determines the precision and speed of the whole system, the communication and remote sensing telemetry system has urgent need for a high-speed high-precision digital-to-analog converter.
Two important issues with digital-to-analog converter design are linearity and resolution. Matching of different elements in the DAC circuit is an important basis for ensuring the linearity of the device, but as the process size of integrated circuits is reduced, the size matching of the DAC elements becomes extremely difficult.
The structure of combining the high-order thermometer code and the low-order binary code is a good method for improving the linearity of the high-precision digital-to-analog converter. For higher thermometer codes, the elements are all the same size, so the element matching is much simpler than the binary case, but the problem of low linearity caused by element mismatch in the digital-to-analog converter circuit still cannot be completely solved.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, and the factory calibration system and the factory calibration method of the high-precision digital-to-analog converter are provided, so that the linearity of the digital-to-analog converter can be effectively improved.
The technical solution of the invention is as follows: a high-precision digital-to-analog converter factory calibration system comprises a power supply, a DAC evaluation board to be calibrated, an upper computer, a universal meter, a USB-to-GPIB controller, a USB-to-parallel port controller and a parallel port-to-SPI controller; the DAC evaluation board to be calibrated comprises a reference source circuit, a crystal oscillator, a relay and an FPGA circuit;
the power supply is used for supplying power to the DAC evaluation board to be calibrated, the DAC chip to be calibrated is arranged on the DAC evaluation board to be calibrated, and the crystal oscillator is connected with the DAC chip to be calibrated and used for providing a working clock for the DAC chip to be calibrated;
the upper computer is connected with the DAC chip to be calibrated through the parallel port-to-SPI controller and is used for detecting whether the read-write functions of an internal register and a calibration register of the DAC chip to be calibrated are normal or not and configuring the working mode of the DAC chip to be calibrated;
the upper computer is connected with the input end of the FPGA circuit through the USB parallel port controller, the output end of the FPGA circuit is connected with the DAC chip to be calibrated and the relay, the output end of the reference source circuit is connected with a voltage reference pin of the DAC chip to be calibrated and used for providing reference voltage for the DAC chip to be calibrated, the output end of the reference source circuit and the voltage analog output end of the DAC chip to be calibrated are both connected with the input end of the relay, and the output end of the relay is connected with the universal meter;
the upper computer can control the FPGA circuit to write data into the DAC chip to be calibrated, and the FPGA circuit controls the relay to enable the multimeter to measure the output voltage of the reference source circuit or the output voltage of the DAC chip to be calibrated, wherein the output voltage of the DAC chip to be calibrated comprises the offset voltage output by the DAC chip to be calibrated and the actual output voltage of each path of MSB; the host computer is connected with the universal meter through a USB-GPIB controller, receives the output voltage of the reference source circuit and the output voltage of the DAC chip to be calibrated, which are sent by the universal meter, obtains the calibration code of the DAC chip to be calibrated, calibrates the DAC chip to be calibrated accordingly, and judges the calibration effect.
The implementation method for obtaining the DAC chip calibration code to be calibrated by the upper computer is as follows:
(2.1) the upper computer calculates the ideal output voltage value MSB of each path of MSBideal；
(2.2) calculating the analog value of each path of MSB calibration code according to the actual output voltage and the ideal output voltage of each path of MSB;
(2.3) converting the analog value of each path of MSB calibration code into a binary code to obtain each path of MSB calibration code;
and (2.4) writing the calibration code of the ith MSB into the ith calibration register through the parallel port-to-SPI controller to realize the calibration of the DAC chip to be calibrated, wherein the total number N of the MSBs is the same as the total number of the calibration registers.
In the step (2.1), the upper computer calculates the ideal output voltage value MSB of each path of MSB by using the following formulaideal：
Figure BDA0001395478550000021
Wherein VLSBFor the DAC chip to be calibrated the lowest effective bit voltage, VoffsetThe output bias voltage of the DAC chip to be calibrated.
In the step (2.2), the analog value V of the i-th MSB calibration code is calculated by using the following formulaadjust-i：
Vadjust-i＝4(MSBactual-i-MSBideal)/VLSB，
In which MSBactual-iIs the actual output voltage, V, of the ith MSBLSBThe minimum effective bit voltage of the DAC chip to be calibrated.
Obtaining the lowest effective bit voltage V of the DAC chip to be calibrated by using the following formulaLSB：
VLSBOutput voltage of reference source circuit/2nAnd 1, n is the number of bits of the DAC chip to be calibrated.
The method for judging the calibration effect by the upper computer comprises the following steps:
and the upper computer calculates the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, if the DNL and the INL meet the range designed in advance, the calibration effect is judged to meet the requirement, and otherwise, the calibration effect does not meet the requirement.
The temperature coefficient of the reference source circuit does not exceed 10 ppm/DEG C.
The calibration method based on the high-precision digital-to-analog converter factory calibration system comprises the following steps:
(1) installing a DAC chip to be calibrated on a DAC evaluation board to be calibrated, and electrifying the DAC chip after the system is connected without errors;
(2) the upper computer writes data into and reads data from the DAC chip internal register to be calibrated through the parallel port-to-SPI controller, tests whether the internal register read-write function is normal, if so, enters the step (3), otherwise, the calibration is finished;
(3) the upper computer sets the DAC chip input to be calibrated into an unidimensional coding format through a parallel port-to-SPI (serial peripheral interface) controller;
(4) the upper computer disables the DAC chip internal reference source to be calibrated through the parallel port-to-SPI controller;
(5) the upper computer writes data into each calibration register and reads the data out through the parallel port-to-SPI controller one by one according to the sequence from 1 to N of the addresses of the DAC chip calibration registers to be calibrated, whether the read-write function of each calibration register is normal is tested, if the read-write function of N calibration registers is normal, the step (6) is carried out, and if one calibration register is abnormal, the calibration is finished; n is the total number of the calibration registers;
(6) the upper computer inputs a reference source circuit switching signal to the FPGA through the USB switching port controller, the FPGA controls a relay to switch a measurement channel of the universal meter according to the switching signal, so that the universal meter measures the output voltage of the reference source circuit, repeatedly measures for multiple times, averages and outputs the average value to the upper computer through the USB switching port GPIB controller;
(7) the upper computer controls the FPGA to provide all-0 input for the DAC chip to be calibrated through the USB parallel port controller;
(8) the upper computer inputs DAC chip switching signals to the FPGA through the USB parallel port controller, the FPGA controls the relay to switch a measurement access of the multimeter according to the switching signals, so that the multimeter measures the offset voltage of the DAC chip to be calibrated, repeated measurement is carried out, multiple averaging values are obtained, and the offset voltage V of the DAC chip to be calibrated is obtainedoffsetAnd output it to the upper computer through USB-GPIB controller;
(9) the method comprises the following steps that an upper computer controls a DAC chip to be calibrated to enter a calibration mode through a parallel port-to-SPI (serial peripheral interface) controller, a universal meter reads an actual output voltage value of each path of MSB (base band bus) of the DAC chip to be calibrated and outputs the actual output voltage value to the upper computer through a USB-to-GPIB controller, and the MSB has N paths;
(10) the upper computer outputs voltage according to the reference source circuit and DAC chip bias voltage V to be calibratedoffsetCalculating the calibration code of the DAC chip to be calibrated according to the actual output voltage value of each MSB, and calibrating the DAC chip to be calibrated according to the calibration code;
(11) and (4) judging the calibration effect by the upper computer, finishing if the calibration effect meets the requirement, and otherwise, repeating the steps (9) - (10) until the calibration effect meets the requirement.
The implementation method of the step (10) is as follows:
(9.1) the upper computer calculates the ideal output voltage value MSB of each path of MSB by using the following formulaideal：
Figure BDA0001395478550000041
Wherein VLSBThe minimum effective bit voltage of the DAC chip to be calibrated is obtained;
VLSBoutput voltage of reference source circuit/2n1, n is the digit of the DAC chip to be calibrated;
(9.2) calculating the analog value of each path of MSB calibration code according to the actual output voltage and the ideal output voltage of each path of MSB by using the following formula:
Vadjust-i＝4(MSBactual-i-MSBideal)/VLSB，
in which MSBactual-iIs the actual output voltage of the ith MSB;
(9.3) converting the analog value of each path of MSB calibration code into a binary code to obtain each path of MSB calibration code;
and (9.4) writing the calibration code of the ith MSB into the ith calibration register through the parallel port-to-SPI controller to realize the calibration of the DAC chip to be calibrated, wherein the total number N of the MSBs is the same as the total number of the calibration registers.
The method for the upper computer to judge whether the calibration effect meets the requirement in the step (11) is as follows:
and the upper computer calculates the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, if the DNL and the INL meet the range designed in advance, the calibration effect is judged to meet the requirement, and if not, the calibration effect is judged not to meet the requirement.
Compared with the prior art, the invention has the beneficial effects that:
(1) the invention fills the blank of high-precision digital-to-analog converter calibration by designing a digital-to-analog converter factory calibration system and method, realizes that the output voltage of the DAC chip to be calibrated closely follows the ideal output voltage, reduces the non-linear defect caused by element mismatching, has good calibration effect, and can effectively improve the linearity of the digital-to-analog converter.
(2) The upper computer judges whether the calibration effect meets the requirement or not by calculating the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, and the calibration precision can be effectively ensured.
(3) Compared with the method for self-calibration inside the digital-to-analog converter, the factory calibration method greatly reduces the use difficulty of users and the popularization and technical support difficulty of digital-to-analog converter manufacturers.
Drawings
FIG. 1 is a schematic diagram of a factory calibration system according to the present invention;
FIG. 2 is a flow chart of a calibration method of the present invention.
Detailed Description
The present invention is described in further detail below with reference to examples and the accompanying drawings.
The invention provides a factory calibration system of a high-precision digital-to-analog converter, which is mainly used for solving the problem of poor linearity caused by mismatching of a current source array due to process technology limitation. As shown in fig. 1, the calibration system includes a power supply, a DAC evaluation board to be calibrated, an upper computer, a universal meter, a USB to GPIB controller, a USB to parallel port controller, and a parallel port to SPI controller; the DAC evaluation board to be calibrated comprises a high-precision reference source circuit, a crystal oscillator, a relay and an FPGA circuit.
The power supply is used for supplying power to the DAC evaluation board to be calibrated, the DAC chip to be calibrated is arranged on the DAC evaluation board to be calibrated, and the crystal oscillator is connected with the DAC chip to be calibrated and used for providing a working clock for the DAC chip to be calibrated.
The upper computer is connected with the DAC chip to be calibrated through the parallel port-to-SPI controller and is used for detecting whether the read-write functions of an internal register and a calibration register of the DAC chip to be calibrated are normal or not and configuring the working mode of the DAC chip to be calibrated (the upper computer writes a specific code into the specific register through the parallel port-to-SPI controller to control the DAC chip to be calibrated to enter the calibration mode); the upper computer is connected with the input end of the FPGA circuit through the USB parallel port controller, the output end of the FPGA circuit is connected with the DAC chip to be calibrated and the relay, the output end of the reference source circuit is connected with a voltage reference pin of the DAC chip to be calibrated, the output end of the reference source circuit and the voltage analog output end of the DAC chip to be calibrated are both connected with the input end of the relay, the output end of the relay is connected with the universal meter, and the upper computer can control the FPGA circuit to write data into the DAC chip to be calibrated and control the relay to switch a measurement access of the universal meter through the FPGA circuit (so that a measurement object of the universal meter is switched between the reference source circuit and the DAC chip; the host computer is connected with the universal meter through a USB-GPIB controller, receives the output voltage of the reference source circuit and the output voltage of the DAC chip to be calibrated, which are sent by the universal meter, obtains the calibration code of the DAC chip to be calibrated, calibrates the DAC chip to be calibrated accordingly, and judges the calibration effect.
The digit of the multimeter is related to the precision of the DAC chip to be calibrated, and the 6.5-digit multimeter is selected. The temperature coefficient of the reference source circuit does not exceed 10 ppm/DEG C.
The implementation method for obtaining the DAC chip calibration code to be calibrated by the upper computer is as follows:
(a) the upper computer calculates the ideal output voltage value MSB of each path of MSB by using the following formulaideal：
Figure BDA0001395478550000061
Wherein VLSBThe minimum effective bit voltage of the DAC chip to be calibrated is obtained;
VLSBoutput voltage of reference source circuit/2n1, n is the digit of the DAC chip to be calibrated;
(b) according to the actual output voltage and the ideal output voltage of each path of MSB, calculating the analog value of each path of MSB calibration code by using the following formula:
Vadjust-i＝4(MSBactual-i-MSBideal)/VLSB，
whereinMSBactual-iIs the actual output voltage of the ith MSB;
(c) converting the analog value of each path of MSB calibration code into a binary code to obtain each path of MSB calibration code;
(d) and writing the calibration code of the ith MSB into the ith calibration register through the parallel port-to-SPI controller to realize the calibration of the DAC chip to be calibrated, wherein the total number N of the MSBs is the same as the total number of the calibration registers.
The method for judging the calibration effect by the upper computer comprises the following steps:
and the upper computer calculates the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, if the DNL and the INL meet the range designed in advance, the calibration effect is judged to meet the requirement, and if not, the calibration effect is judged not to meet the requirement.
FIG. 2 is a calibration flow chart of the DAC chip to be calibrated, and the specific method is as follows
(1) And installing the DAC chip to be calibrated on the DAC evaluation board to be calibrated, and electrifying to reset the DAC chip to be calibrated after the system is connected without errors.
(2) The upper computer writes data into and reads data from the DAC chip internal register to be calibrated through the parallel port-to-SPI controller, tests whether the internal register read-write function is normal, if so, enters the step (3), otherwise, the calibration is finished;
(3) the upper computer sets the DAC chip input to be calibrated into an unidimensional coding format through a parallel port-to-SPI (serial peripheral interface) controller;
(4) the upper computer disables the DAC circuit internal reference source through the parallel port-to-SPI controller;
(5) the upper computer writes data into each calibration register and reads the data out through the parallel port-to-SPI controller one by one according to the sequence from 1 to N of the addresses of the DAC chip calibration registers to be calibrated, whether the read-write function of each calibration register is normal is tested, if the read-write function of N calibration registers is normal, the step (6) is carried out, and if one calibration register is abnormal, the calibration is finished; n is the total number of calibration registers, N is 2M-1, M is the number of bits of the thermometer code in the DAC;
(6) the upper computer inputs a reference source circuit switching signal to the FPGA through the USB switching port controller, the FPGA controls a relay to switch a measurement channel of the universal meter according to the switching signal, so that the universal meter measures the output voltage of the reference source circuit, repeatedly measures for multiple times, averages and outputs the average value to the upper computer through the USB switching port GPIB controller;
the upper computer outputs according to the reference source circuitObtaining the lowest effective bit voltage V of the DAC chip to be calibratedLSBThe formula is as follows: vLSBOutput voltage of reference source circuit/2nAnd 1, n is the number of bits of the DAC chip to be calibrated.
(7) The upper computer controls the FPGA to provide all-0 input for the DAC chip to be calibrated through the USB parallel port controller;
(8) the upper computer inputs DAC chip switching signals to the FPGA through the USB parallel port controller, the FPGA controls the relay to switch a measurement access of the multimeter according to the switching signals, so that the multimeter measures the offset voltage of the DAC chip to be calibrated, repeated measurement is carried out, multiple averaging values are obtained, and the offset voltage V of the DAC chip to be calibrated is obtainedoffsetThe USB-GPIB controller outputs the data to the upper computer;
(9) the upper computer controls the DAC chip to be calibrated to enter a calibration mode through the parallel port-to-SPI controller, the universal meter reads the actual output voltage value of each path of MSB of the DAC chip to be calibrated and outputs the actual output voltage value to the upper computer through the USB-to-GPIB controller, and N paths of MSBs are provided in total;
(10) the upper computer outputs voltage according to the reference source circuit and DAC chip bias voltage V to be calibratedoffsetCalculating the calibration code of the DAC chip to be calibrated according to the actual output voltage value of each MSB, and calibrating the DAC chip to be calibrated according to the calibration code;
(11) and (4) judging the calibration effect by the upper computer, namely calculating the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, judging that the calibration effect meets the requirement if the DNL and the INL meet the range designed in advance, and otherwise, repeating the steps (9) - (10) until the DNL and the INL meet the range designed in advance.
The method fills the blank of high-precision digital-to-analog converter calibration, and has the advantages of good calibration effect, economy, easy realization and easy expansion. Compared with the method for self-calibration inside the digital-to-analog converter, the factory calibration method greatly reduces the use difficulty of users and the popularization and technical support difficulty of digital-to-analog converter manufacturers.
Example (b):
taking a current-mode DAC with a 16-bit 400MSPS, a 7-bit thermometer code structure and a 9-bit binary code structure as an example of a DAC chip to be calibrated, the static parameters INL <5LSB and DNL <3.5LSB of the DAC are required. The specific implementation process of the invention is as follows:
the 16-bit 400MSPS DAC to be calibrated is placed on an evaluation board, the power supply is 5V, the crystal oscillator is 125MHz, the DAC is used for providing a working clock for the DAC, and the voltage V provided by an external reference source circuitrefThe voltage is 1.25V, and a 6.5-bit multimeter is selected as the multimeter. And the upper computer writes 00H and FFH into an internal register of the DAC through the parallel port-to-SPI controller and detects whether the register is read or written normally. And after normal reading and writing, the upper computer sets a corresponding register, sets the coding mode of the DAC to be Unsigned, and uses an external reference source circuit.
In this embodiment, there are 127 calibration registers, and the upper computer sequentially writes 00H, FFH into 127 calibration registers to detect whether the calibration registers work normally one by one.
When the calibration registers work normally, the upper computer enables the FPGA to generate a switching signal through the USB parallel port controller, controls a relay to switch a measurement object of the 6.5-bit universal meter to be an external reference source circuit, measures 15 times and averages to obtain the output voltage of the reference source circuit, and further calculates to obtain the least significant bit voltage V of the DACLSB，VLSB＝Vref/65536. And the upper computer controls the FPGA to provide all-zero input signals for the DAC, and controls the relay to switch the measurement object of the 6.5-bit multimeter into DAC output. Repeatedly measuring for 10 times and averaging to obtain the offset voltage V of the DACoffset. The ideal output voltage of each MSB is
Figure BDA0001395478550000091
The host computer sets DAC through the parallel port to change SPI controller and gets into the calibration mode, 127 total MSB current sources need the calibration. The DAC traverses all the MSB current sources, the upper computer calculates a calibration code according to the difference value between the output value of each path and the ideal value of the MSB, and then the calibration code is fed back to the DAC to calibrate each path of MSB current source respectively.
Finally, the static parameters INL and DNL of the calibrated DAC are calculated, and it is found that INL and DNL are increased from 10LSB and 7LSB before calibration to 4.5LSB and 3LSB, respectively. And the calibration requirements are met.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.

Claims (10)

1. A high accuracy digital-to-analog converter factory calibration system, characterized by: the device comprises a power supply, a DAC evaluation board to be calibrated, an upper computer, a universal meter, a USB-to-GPIB controller, a USB-to-parallel port controller and a parallel port-to-SPI controller; the DAC evaluation board to be calibrated comprises a reference source circuit, a crystal oscillator, a relay and an FPGA circuit;
the power supply is used for supplying power to the DAC evaluation board to be calibrated, the DAC chip to be calibrated is arranged on the DAC evaluation board to be calibrated, and the crystal oscillator is connected with the DAC chip to be calibrated and used for providing a working clock for the DAC chip to be calibrated;
the upper computer is connected with the DAC chip to be calibrated through the parallel port-to-SPI controller and is used for detecting whether the read-write functions of an internal register and a calibration register of the DAC chip to be calibrated are normal or not and configuring the working mode of the DAC chip to be calibrated;
the upper computer is connected with the input end of the FPGA circuit through the USB parallel port controller, the output end of the FPGA circuit is connected with the DAC chip to be calibrated and the relay, the output end of the reference source circuit is connected with a voltage reference pin of the DAC chip to be calibrated and used for providing reference voltage for the DAC chip to be calibrated, the output end of the reference source circuit and the voltage analog output end of the DAC chip to be calibrated are both connected with the input end of the relay, and the output end of the relay is connected with the universal meter;
the upper computer can control the FPGA circuit to write data into the DAC chip to be calibrated, and the FPGA circuit controls the relay to enable the multimeter to measure the output voltage of the reference source circuit or the output voltage of the DAC chip to be calibrated, wherein the output voltage of the DAC chip to be calibrated comprises the offset voltage output by the DAC chip to be calibrated and the actual output voltage of each path of MSB; the host computer is connected with the universal meter through a USB-GPIB controller, receives the output voltage of the reference source circuit and the output voltage of the DAC chip to be calibrated, which are sent by the universal meter, obtains the calibration code of the DAC chip to be calibrated, calibrates the DAC chip to be calibrated accordingly, and judges the calibration effect.
2. A factory calibration system for a high precision digital to analog converter according to claim 1, wherein: the implementation method for obtaining the DAC chip calibration code to be calibrated by the upper computer is as follows:
(2.1) the upper computer calculates the ideal output voltage value MSB of each path of MSBideal；
(2.2) calculating the analog value of each path of MSB calibration code according to the actual output voltage and the ideal output voltage of each path of MSB;
(2.3) converting the analog value of each path of MSB calibration code into a binary code to obtain each path of MSB calibration code;
and (2.4) writing the calibration code of the ith MSB into the ith calibration register through the parallel port-to-SPI controller to realize the calibration of the DAC chip to be calibrated, wherein the total number N of the MSBs is the same as the total number of the calibration registers.
3. A factory calibration system for a high precision digital to analog converter according to claim 2, wherein: in the step (2.1), the upper computer calculates the ideal output voltage value MSB of each path of MSB by using the following formulaideal：
Figure FDA0001395478540000021
Wherein VLSBFor the DAC chip to be calibrated the lowest effective bit voltage, VoffsetThe output bias voltage of the DAC chip to be calibrated.
4. A factory calibration system for a high precision digital to analog converter according to claim 2, wherein: in the step (2.2), the analog value V of the i-th MSB calibration code is calculated by using the following formulaadjust-i：
Vadjust-i＝4(MSBactual-i-MSBideal)/VLSB，
In which MSBactual-iIs the actual output voltage, V, of the ith MSBLSBThe minimum effective bit voltage of the DAC chip to be calibrated.
5. A factory calibration system for a high precision digital to analog converter according to claim 3 or 4, wherein: obtaining the lowest effective bit voltage V of the DAC chip to be calibrated by using the following formulaLSB：
VLSBOutput voltage of reference source circuit/2nAnd 1, n is the number of bits of the DAC chip to be calibrated.
6. A factory calibration system for a high precision digital to analog converter according to claim 1, wherein: the method for judging the calibration effect by the upper computer comprises the following steps:
and the upper computer calculates the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, if the DNL and the INL meet the range designed in advance, the calibration effect is judged to meet the requirement, and otherwise, the calibration effect does not meet the requirement.
7. A factory calibration system for a high precision digital to analog converter according to claim 1, wherein: the temperature coefficient of the reference source circuit does not exceed 10 ppm/DEG C.
8. The calibration method of factory calibration system for high precision digital-to-analog converter according to claim 1, characterized by comprising the following steps:
(1) installing a DAC chip to be calibrated on a DAC evaluation board to be calibrated, and electrifying the DAC chip after the system is connected without errors;
(2) the upper computer writes data into and reads data from the DAC chip internal register to be calibrated through the parallel port-to-SPI controller, tests whether the internal register read-write function is normal, if so, enters the step (3), otherwise, the calibration is finished;
(3) the upper computer sets the DAC chip input to be calibrated into an unidimensional coding format through a parallel port-to-SPI (serial peripheral interface) controller;
(4) the upper computer disables the DAC chip internal reference source to be calibrated through the parallel port-to-SPI controller;
(5) the upper computer writes data into each calibration register and reads the data out through the parallel port-to-SPI controller one by one according to the sequence from 1 to N of the addresses of the DAC chip calibration registers to be calibrated, whether the read-write function of each calibration register is normal is tested, if the read-write function of N calibration registers is normal, the step (6) is carried out, and if one calibration register is abnormal, the calibration is finished; n is the total number of the calibration registers;
(6) the upper computer inputs a reference source circuit switching signal to the FPGA through the USB switching port controller, the FPGA controls a relay to switch a measurement channel of the universal meter according to the switching signal, so that the universal meter measures the output voltage of the reference source circuit, repeatedly measures for multiple times, averages and outputs the average value to the upper computer through the USB switching port GPIB controller;
(7) the upper computer controls the FPGA to provide all-0 input for the DAC chip to be calibrated through the USB parallel port controller;
(8) the upper computer inputs DAC chip switching signals to the FPGA through the USB parallel port controller, the FPGA controls the relay to switch a measurement access of the multimeter according to the switching signals, so that the multimeter measures the offset voltage of the DAC chip to be calibrated, repeated measurement is carried out, multiple averaging values are obtained, and the offset voltage V of the DAC chip to be calibrated is obtainedoffsetAnd output it to the upper computer through USB-GPIB controller;
(9) the method comprises the following steps that an upper computer controls a DAC chip to be calibrated to enter a calibration mode through a parallel port-to-SPI (serial peripheral interface) controller, a universal meter reads an actual output voltage value of each path of MSB (base band bus) of the DAC chip to be calibrated and outputs the actual output voltage value to the upper computer through a USB-to-GPIB controller, and the MSB has N paths;
(10) the upper computer outputs voltage according to the reference source circuit and DAC chip bias voltage V to be calibratedoffsetCalculating the calibration code of the DAC chip to be calibrated according to the actual output voltage value of each MSB, and calibrating the DAC chip to be calibrated according to the calibration code;
(11) and (4) judging the calibration effect by the upper computer, finishing if the calibration effect meets the requirement, and otherwise, repeating the steps (9) - (10) until the calibration effect meets the requirement.
9. The calibration method according to claim 8, wherein: the implementation method of the step (10) is as follows:
(9.1) the upper computer calculates the ideal output power of each path of MSB by using the following formulaPressure value MSBideal：
Figure FDA0001395478540000041
Wherein VLSBThe minimum effective bit voltage of the DAC chip to be calibrated is obtained;
VLSBoutput voltage of reference source circuit/2n1, n is the digit of the DAC chip to be calibrated;
(9.2) calculating the analog value of each path of MSB calibration code according to the actual output voltage and the ideal output voltage of each path of MSB by using the following formula:
Vadjust-i＝4(MSBactual-i-MSBideal)/VLSB，
in which MSBactual-iIs the actual output voltage of the ith MSB;
(9.3) converting the analog value of each path of MSB calibration code into a binary code to obtain each path of MSB calibration code;
and (9.4) writing the calibration code of the ith MSB into the ith calibration register through the parallel port-to-SPI controller to realize the calibration of the DAC chip to be calibrated, wherein the total number N of the MSBs is the same as the total number of the calibration registers.
10. The calibration method according to claim 8, wherein: the method for the upper computer to judge whether the calibration effect meets the requirement in the step (11) is as follows:
and the upper computer calculates the differential nonlinear DNL and the integral nonlinear INL after the DAC chip to be calibrated is calibrated, if the DNL and the INL meet the range designed in advance, the calibration effect is judged to meet the requirement, and if not, the calibration effect is judged not to meet the requirement.
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