JP2014150309A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly improve linearity by adjusting a current additively supplied to a parasitic resistance in accordance with an input code to make a reference voltage applied to an R-2R type D/A converter independent of the input code.SOLUTION: A D/A converter that includes a capacity division type D/A converter connected to reference current wiring to D/A-convert upper k bits of input data and the R-2R type D/A converter connected to the reference current wiring to D/A-convert the remaining lower m bits of the input data, and adds an output voltage of the capacity division type D/A converter and an output voltage of the R-2R type D/A converter to produce an output voltage is provided with a current smoothing circuit connected in parallel with the R-2R type D/A converter to additionally supply a compensation current to a parasitic resistance of the reference current wiring. The current smoothing circuit additionally supplies a compensation current depending on the lower m bits of data to the parasitic resistance.

Description

  The present invention relates to a D / A converter constituted by a CMOS integrated circuit or the like, and more particularly, to a D / A converter required to achieve both high speed and high accuracy (10 bits, 1 MS / s or more) and a small area.

  In recent years, A / D converters and D / A converters are increasingly used in a wide range of applications such as sensor systems and control systems. In particular, successive approximation type A / D converters are widely used from general-purpose A / D converters of individual parts to large-scale integrated circuits such as microcomputers and ASSPs because of their small area and low power consumption. The performance required for the successive approximation type A / D converter is that the differential nonlinearity DNL and the integral nonlinearity INL are good and operate at high speed. The differential nonlinearity DNL indicates the difference between the actual step size between two adjacent input codes and the ideal 1LSB change, and the integral nonlinearity INL is a straight line connecting the negative full scale and the positive full scale. Indicates the magnitude of the maximum deviation from LSB (in LSB units).

  In the successive approximation A / D converter, the performance of the D / A converter is directly reflected in the performance of the entire A / D converter, and thus a high-performance D / A converter is required. The D / A converter is roughly classified into a capacitive type and a resistance type as described in Patent Document 1, but it is simple such as a capacitive voltage dividing type D / A converter alone or a resistive D / A converter alone. If a high-precision D / A converter is to be assembled with such a configuration, the number of capacitors increases or the number of switches increases, leading to an increase in chip area. For example, when a 10-bit D / A converter is configured with only a capacitor, an integrated circuit requires 1024 capacitors with a large area, and when assembled in a resistance division type, at least 1023 or more switches are required. .

  Therefore, as introduced in Patent Document 1, Patent Document 2, and Non-Patent Document 1, separate D / A converters are used for low-accuracy side (upper bit) conversion and high-accuracy side (lower bit) conversion, respectively. There are many methods that avoid the increase in area by using and configuring.

  As a hybrid type D / A converter capable of relatively high speed operation, a capacitive voltage dividing type D / A converter is used for conversion of the upper bits of the input code, and an R-2R type D / A is used for conversion of the lower bits. Some use an A converter. An example is shown in FIG. This D / A converter is a case of 10 bits.

  The capacity-dividing D / A converter 10 receives the input code Din [9: 5], and is binary-weighted five capacitors (C, 2C, 4C, 8C, 16C) and a coupling capacitor Cp (= C ) And switches SW5 to SW9 connected to the five weighted capacitors (C, 2C, 4C, 8C, 16C) and driven by the input code Din [9: 5]. The switches SW5 to SW9 connect one end of each capacitor to the high potential reference voltage VRH or the low potential reference voltage VRL via the parasitic resistance RPH. Here, for the sake of simplicity, the parasitic resistance existing in the reference current wiring is represented by RPH.

The output voltage of the capacitive voltage dividing type D / A converter 10 is determined by the capacitive voltage division. For example, if there are α capacitors connected to the high potential reference voltage VRH, the output voltage Vout is
Vout = Vref × α / 32 (1)
It becomes. Vref is a reference voltage, which is a potential difference between the high-level reference voltage VRH and the low-level reference voltage VRL. Since the capacity is binary weighted, the input code Din [9: 5]
α = Din [9] × 16 + Din [8] × 8 + Din [7] × 4 + Din [6] × 2
+ Din [5] × 1 (2)
Therefore, it operates as a D / A converter.

  On the other hand, the R-2R type D / A converter 20 to which the input code Din [4: 0] is input is configured by connecting resistances of R and 2R in a ladder shape, and the resistance of 2R excludes the terminal portion. Are connected to the switches SW0 to SW4 driven by the input code Din [4: 0]. The switches SW0 to SW4 connect one end of the 2R resistor to the high potential reference voltage VRH or the low potential reference voltage VRL via the parasitic resistance RPH.

The output voltage of the R-2R type D / A converter 20 is VA, the input code Din [4: 0],
VA = Vref × (Din [4] × 16 + Din [3] × 8 + Din [2] × 4
+ Din [1] × 2 + Din [0] × 1) / 32 (3)
Therefore, it operates as a D / A converter.

Further, since the voltage VA is connected to the bottom plate of the capacitor Cp, and the voltage VA is scaled to 1/32, the output voltage Vout is
Vout = (Vref × α / 32) + (Vref × VA / 32) (4)
And operates as a 10-bit D / A converter.

  Since both the capacitive voltage dividing type D / A converter 10 and the R-2R type D / A converter 20 are configured with a small number of passive elements having a large area, they can be mounted in a small area. Specifically, as shown in FIG. 8, when the upper 5 bits are constituted by the capacitive voltage dividing type D / A converter 10 and the lower 5 bits are constituted by the R-2R type D / A converter 20, the capacitance having a large area. 16C, 8C, 4C, 2C, C, CP are 16 units, 8 units, 4 units, 2 units, 1 unit, 32 units when using the capacitance of capacitance value C, and R is connected to the resistor 2R. When two resistors are used, only 16 resistors can be configured.

  The disadvantage of the R-2R type D / A converter 20 is that the linearity deteriorates when the resistance weights of the resistance values R and 2R change. For this reason, in order to improve linearity, it is necessary to devise the layout design so that matching of each resistance is improved, or to consider the ON resistance by adjusting the switch size. On the other hand, in the case of the R-2R type D / A converter 20 used in the hybrid type D / A converter as in the present case, there is no particular problem in performance with respect to the variation in resistance value and the ON resistance of the switch. Relaxed to a degree. For example, in the case of the configuration shown in FIG. 8, the R-2R type D / A converter 20 may be designed to satisfy the accuracy of 5 bits.

JP 2004-80075 A US Pat. No. 7,265,708

G. Promitzer, “12-bit Low-Power Fully Differential Switched Capacitor Non-Calibrating Successive Approximation ADC with lMS / s,” IEEE JSSC, Vol. 36, No. 7, pp. 113-1143, Jul. 2001

  However, the R-2R type D / A converter 20 has a problem that the amount of current flowing through the reference voltage wiring varies depending on the input code. Due to this variation in current amount, the voltage drop due to the parasitic resistance RPH of the reference voltage wiring also varies, and the reference voltage of each input code applied to the R-2R type D / A converter 20 varies. As a result, the integrated nonlinearity INL and the differential nonlinearity DNL as a whole D / A converter are adversely affected. In particular, the degradation of the differential nonlinear DNL is a problem, and when it exceeds 1LSB, the monotonic increase is impaired, and when applied to a successive approximation A / D converter, a missing code is generated. We focused on improving differential nonlinearity DNL.

  This phenomenon will be described with reference to the equivalent circuit for the reference current shown in FIG. 9, taking the configuration shown in FIG. 8 as an example. FIG. 9 shows an equivalent circuit of the R-2R type D / A converter 20 for each input code. In the configuration of the D / A converter shown in FIG. 8, as described above, for simplification, only the parasitic resistance RPH on the high potential reference voltage VRH side is considered, and the capacitive voltage dividing D / A converter is used. Since no current flows through 10, the input code only considers the lower 5 bits.

  In the case of the input code “00000”, all switches are fixed to the high potential reference voltage VRH side through the parasitic resistance RPH, and therefore the current is 0A. Subsequently, in the case of the input code “00001”, only the switch SW0 is switched to the high potential reference voltage VRH side (voltage VH side), so that a current of about Vref / 3R flows. In the case of the input code “00010”, since only the switch SW1 is switched to the high potential reference voltage VRH side (voltage VH side), a current of about Vref / 3R flows. In the case of the input code “00011”, since only the switches SW0 and SW1 are switched to the high potential reference voltage VRH side (voltage VH side), the current changes to a current of about Vref / 2R. In the input code “00100”, since only the switch SW2 is switched to the high potential reference voltage VRH side (voltage VH side), the current becomes Vref / 3R. As described above, since the number of resistors connected to the high potential reference voltage VRH and the low reference voltage VRL side changes according to the input code, the reference current flowing through the parasitic resistance RPH varies depending on the input code. End up.

  Here, FIG. 10A shows a reference current when R = 3 kΩ and Vref = 5.0V. The current value changes most greatly when the input code is switched from “00000” (= 0) to “00001” (= 1) and when the input code is “01111” (= 15) to “10000” (= 16 ), And the amount of change is approximately 0.6 mA (= Vref / 3R). The degradation of the differential non-linear DNL in this portion is the largest, leading to the differential non-linear DNL degradation of (Vref / 3R) × RPH.

  FIG. 11A shows an example of the differential nonlinear DNL and FIG. 12A shows an example of the integral nonlinear INL when the parasitic resistance RPH = 5Ω is set to operate as a 10-bit D / A converter. . In these characteristics, it can be confirmed that the integral nonlinearity INL / differential nonlinearity DNL is 32 code cycles and that the error increases in proportion to the output voltage. The deterioration in 32 input code cycles corresponds to the switching cycle between the R-2R type D / A converter 20 and the capacitive voltage dividing type D / A converter 10. When the waveform of the integral nonlinearity INL is confirmed, it matches the current waveform shown in FIGS. 10A and 10D, and is an error due to the reference current fluctuation of the R-2R type D / A converter 20. Can be confirmed. The reason why the degradation of the differential nonlinearity DNL increases in proportion to the output voltage (corresponding to the input code) is that the higher the output voltage, the greater the influence of the voltage drop due to the parasitic resistance RPH, and the degradation of the differential nonlinearity DNL. Therefore, the maximum is about 0.5 LSB in the portion close to the high potential reference voltage VRH side.

This error voltage Verr is expressed by a mathematical formula.
Verr = Iref × RPH × Vout / Vref (5)
become that way. Iref is a reference current flowing through the parasitic resistance RPH.

From equation (5), the integral nonlinearity INL and the differential nonlinearity DNL are
INL [i] = Iref [i] × RPH × Vout [i] × β × 1024 / Vref ²
(6)
DNL [i] = INL [i] −INL [i−1] (7)
It is expressed by the following formula. Here, i is an integer from 0 to 1023, INL [i] is the integral nonlinearity of the input code i, and DNL [i] is the differential nonlinearity of the input code i. β is a coefficient for fitting the integral nonlinearity INL so that it becomes 0 with the input code 0 and the input code 1023 (both ends fit) and removing the full-scale error from the error voltage Verr (offset error in this case) Is 0).

  In order to reduce the error voltage Verr caused by the reference current fluctuation, a method of reducing the parasitic resistance RPH is conceivable, but the usability is deteriorated or the cost is increased. For example, as one method of reducing the parasitic resistance RPH, there is a method of separating the reference voltage wirings of the R-2R type D / A converter 20 and the capacitive voltage dividing type D / A converter 10. In this method, the reference voltage terminals of the R-2R type D / A converter 20 and the capacitive voltage dividing type D / A converter 10 are separated into two and star-connected on the PCB board. However, this method has a problem in that the number of IC pins must be increased, leading to an increase in cost. Another method is to increase the drive capability of the reference voltage wiring by thickening the wiring or shortening the wire bonding on the package in order to lower the resistance value. However, even in this case, although the problem with the integrated circuit alone can be solved, an expensive reference buffer is required because the impedance of the previous circuit must be sufficiently reduced. As described above, in any of the methods, the problem of cost increase and the improvement of the external circuit are required, so that the usability is deteriorated and it is not a fundamental solution.

  The object of the present invention is to adjust the current to be added to the parasitic resistance according to the input code so that the reference voltage applied to the R-2R type D / A converter does not depend on the input code, and linearity is improved. It is to provide a greatly improved D / A converter.

In order to achieve the above object, according to a first aspect of the present invention, there is provided a capacitive voltage dividing type D / A converter connected to a reference current wiring and performing higher-order k-bit D / A conversion of input data, and the reference current wiring. An R-2R type D / A converter that performs D / A conversion of the remaining lower m bits of the remaining input data, and outputs the output voltage of the capacitive voltage dividing type D / A converter and the R-2R In the D / A converter which adds the output voltage of the type D / A converter to obtain the output voltage, the R-2R type D / A converter is supplied with additional correction current to the parasitic resistance of the reference current wiring. A current smoothing circuit connected in parallel is provided, and the current smoothing circuit additionally supplies a correction current corresponding to the lower-order m-bit data to the parasitic resistance.
According to a second aspect of the present invention, in the D / A converter according to the first aspect, the current smoothing circuit is configured such that the smaller the value of the reference current flowing through the R-2R type D / A converter, the smaller the correction current. It is characterized by increasing the value of.
According to a third aspect of the present invention, in the D / A converter according to the first aspect, when the reference current corresponding to the even-numbered input code flows, the current smoothing circuit decreases the reference current. The value of the correction current is increased.
The invention according to claim 4 is the D / A converter according to claim 1, 2, or 3, wherein the current smoothing circuit is a variable connected in parallel to the R-2R type D / A converter. A resistance circuit and an encoder that switches a resistance value of the variable resistance circuit in accordance with the lower m-bit input code.
The invention according to claim 5 is the D / A converter according to claim 2, wherein the current smoothing circuit is a variable current connected in parallel to the R-2R type D / A converter. A source circuit; and an encoder that switches a current value of the variable current source circuit in accordance with the lower m-bit input data.
According to a sixth aspect of the present invention, in the D / A converter according to the first, second, third, fourth, or fifth aspect, the current smoothing circuit is configured such that the input data when the lower m-bit input data is 3 bits. 3 × IHK correction current when the data is “000”, 2 × IHK correction current when the input data is “100”, and 1 × when the input data is “010” or “110”. A correction current of IHK is additionally supplied to the parasitic resistance as a correction current of 0 × IHK when the input data is “001”, “011”, “101” or “111”, respectively. However, when the value of the unit resistance of the R-2R type D / A converter is R and the reference voltage is Vref, IHK = Vref / 9R.

  According to the present invention, the input current dependent reference current fluctuation of the R-2R type D / A converter can be suppressed by the current smoothing circuit, and the reference voltage applied to the R-2R type D / A converter is It becomes independent of the input code, and the linearity of the D / A converter can be improved. Further, since the current smoothing circuit has a small area and can be simply configured, it can be mounted on a D / A converter with a small area and a low cost. Furthermore, in the circuit configuration of the current smoothing circuit, smoothing is performed with respect to fluctuations in the reference current of the R-2R type D / A converter by using a resistor having a resistance value of 9R and a switch for switching the current value by an input cord. Can be done effectively.

It is a block diagram which shows the structure of the A / D converter of the Example of this invention. It is a figure which shows the current smoothing circuit of a low-order m bit input, (a) is a circuit diagram of a resistance drive type current smoothing circuit, (b) is a circuit diagram of a current drive type current smoothing circuit. It is a figure which shows the current smoothing circuit of a low-order 3 bits input, (a) is a specific circuit diagram of a resistance driving type current smoothing circuit, (b) is a specific circuit diagram of a current driving type current smoothing circuit. It is a circuit diagram. It is explanatory drawing of the characteristic of the input code versus output current in the current smoothing circuit of Fig.3 (a), (b). It is a figure which shows the current smoothing circuit of another example of a low-order 3 bit input, (a) is a specific circuit diagram of a resistance drive type current smoothing circuit, (b) is a current drive type current smoothing circuit It is a specific circuit diagram. It is a figure which shows the current smoothing circuit of another example of low-order 5 bits input, (a) is a specific circuit diagram of a resistance drive type current smoothing circuit, (b) is a current drive type current smoothing circuit It is a specific circuit diagram. It is explanatory drawing of the characteristic of the input code versus output current in the current smoothing circuit of Fig.6 (a), (b). It is a circuit diagram of a conventional 10-bit D / A converter configured by a 5-bit capacity voltage-dividing D / A converter and a 5-bit R-2R type D / A converter. FIG. 9 is an explanatory diagram of an equivalent circuit and a reference current for input codes “00000” to “00100” of the R-2R type D / A converter illustrated in FIG. 8. (A) is a characteristic diagram of a reference current value of an R-2R type D / A converter with a 3-bit input (for input codes of 0 to 32), and (b) is a correction current of a current smoothing circuit with a 3-bit input. Characteristic diagram (for input code of 0 to 32), (c) is a characteristic diagram of corrected composite current (for input code of 0 to 32), and (d) is a characteristic diagram of composite current after correction (all input codes) Min). 10 is a characteristic diagram of differential nonlinear DNL (R = 3 kΩ, RPH = 5Ω, RHK = 27 kΩ, Vref = 5.0 V) in a 10-bit D / A converter, and (a) is no current correction by a current smoothing circuit. (Lower is a partially enlarged view) Characteristic diagram, (b) is a characteristic diagram with current correction by a current smoothing circuit (lower is a partially enlarged view). 10 is a characteristic diagram of integral nonlinearity INL (both ends fit) (R = 3 kΩ, RPH = 5Ω, RHK = 27 kΩ, Vref = 5.0 V) in a 10-bit D / A converter, and (a) is a current smoothing circuit. (B) is a characteristic diagram with current correction by a current smoothing circuit (lower is a partially enlarged view). FIG. 8 is a characteristic diagram of a reference current of the R-2R type D / A converter 20 in the 10-bit D / A converter in the case of FIG. 7, and (a) is a correction current of the current smoothing circuit (input codes of 0 to 32). Min) and (b) are combined currents (for input codes of 0 to 32), and (c) are combined currents (for all input codes). (A) is a characteristic diagram of the differential nonlinearity DNL when designed with the current value of FIG. 7 (the lower part is a partially enlarged view), and (b) is the integral nonlinearity INL when designed with the current value of FIG. It is a characteristic view (the lower part is a partially enlarged view).

  In the present invention, a method for canceling the fluctuation of the current flowing through the reference voltage wiring is proposed in consideration of the above-described problems. In this method, since the current fluctuation itself can be reduced, the above problem can be alleviated by the amount canceled.

  First, FIG. 10A shows a simulation result of the reference current of the R-2R type D / A converter 20 in the circuit configuration shown in FIG. 8 as described above. As can be seen from the results, the reference current of the R-2R type D / A converter 20 tends to be small when the input code is even and large when the input code is odd. Further, it can be confirmed that the fluctuation of the reference current is increased to 1 times, about 2 times, and about 3 times in the order of the input code of a multiple of 2, a multiple of 4, and a multiple of 8. In the present invention, by paying attention to this, a correction current having a pattern as shown in FIG. 10B is added to a parasitic resistance RPH in which a reference current corresponding to an even-numbered input code having a small current flows, thereby making the entire input code parasitic. This is intended to reduce the fluctuation of the current flowing through the resistor RPH.

  In the present invention, in order to solve the above problem, as shown in FIG. 1, in addition to an n-bit D / A converter including a capacitive voltage dividing D / A converter 10 and an R-2R D / A converter 20, R A current smoothing circuit 30 for adding a correction current to the reference current flowing through the -2R type D / A converter 20 at the parasitic resistance RPH is connected to the R-2R type D / A converter 20 in parallel. It is. In FIG. 1, n is an integer of 10 or more, for example, the number of upper bits is k, the number of lower bits is m, and k + m = n.

  The amount of current addition depends on the low-order m-bit input code of the R-2R type D / A converter 20, and when the reference current changes in the negative direction with the adjacent input code, the current is roughly added. As a result, the change in the current flowing through the parasitic resistance RPH between adjacent input codes is reduced, the fluctuation of the reference voltage applied to the R-2R type D / A converter 20 is suppressed, and the error of the differential nonlinear DNL is reduced. It is intended for improvement. Further, since the effect of suppressing current fluctuations throughout the input code can be expected, it can be said that the improvement of the error of the integral nonlinearity INL is also intended.

<Principle configuration>
FIG. 2A shows the principle configuration of a resistance-driven current smoothing circuit 30A that adjusts the correction current by resistance change. In this principle configuration, the lower m bits of the input code Din are input, and the correction current is changed by switching the resistance value Rx of the variable resistor 32A according to the result of encoding it by the encoder 31A. In the case of this method, since the current value fluctuation of the R-2R type DA converter 20 is resistive, it is easy to obtain a smoothing effect regardless of the value of the reference voltage, but when the number of resistance elements increases. Increases area.

  FIG. 2B shows the principle configuration of a current-driven current smoothing circuit 30B that adjusts the correction current by changing the current source current. In this principle configuration, the lower m bits of the input code Din are input, and the correction current is changed by switching the current value Ix of the variable current source 32B according to the result encoded by the encoder 31B. In this method, it is difficult to obtain a smoothing effect when the reference voltage changes. However, since a current source can be configured by a transistor, it is suitable for downsizing.

<Example 1>
FIG. 3A shows a specific example of a resistance-driven current smoothing circuit 30C when the lower bits are 3 bits. The current smoothing circuit 30C includes inverters INV0, INV1, and INV2, three resistors R0, R1, and R2 (resistance values are the same in RHK) and input codes Din [0], Din [1], and Din. It is composed of switches SWH0, SWH1, and SWH2 that are turned off when [2] is 1 and turned on when 0.

  FIG. 4 shows a change in the correction current in the input code Din [2: 0]. Assuming that the current values flowing through the resistors R0, R1, and R2 are the same at IHK, when the input code is “000”, the current is (3 × IHK), and when the input code is “100”, the current is (2 × IHK). When “010” or “110”, the current is (1 × IHK), and in other cases, the current is (0 × IHK), which is added to the current flowing through the parasitic resistance RPH.

  When the R-2R type DA converter 20 is 3 bits, the current difference between the largest adjacent input codes is Vref / 3R, and the resistance value RHK = 9R is set as a result of examination based on the simulation result. It was found that the smoothing effect was optimized. FIG. 10B shows the correction current (output current) by the current smoothing circuit 30C when RHK = 9R, and FIGS. 10C and 10D show the combined current of the reference current and the correction current. As shown in FIGS. 10C and 10D, compared to FIG. 10A before correction, the current fluctuation in the entire input code is less than half, and the current fluctuation between the input codes. It can be seen that is also kept small.

  Further, the conventional A / D converter including the capacitive voltage dividing A / D converter 10 and the R-2R D / A converter 20 shown in FIG. 8, and the current smoothing circuit shown in FIG. FIG. 11B shows a simulation result of the differential nonlinear DNL when the D / A converter of the present invention in which 30C is incorporated as the current smoothing circuit 30 as shown in FIG. 1 is operated. The same conditions (R = 3 kΩ, RPH = 5Ω, RHK = 27 kΩ, Vref = 5.0 V) as in the conventional example of FIG. When there is no current smoothing circuit 30C, as shown in FIG. 11A, the differential nonlinearity DNL increases to a maximum of 0.5LSB. When there is a current smoothing circuit 30C, as shown in FIG. 11B. It can be seen that the differential nonlinearity DNL is reduced to 0.2 LSB at the maximum, and is suppressed to about 40%.

  Further, FIG. 12B shows a simulation result of the integral nonlinearity INL of both end fitting. From the enlarged view, it can be confirmed that the integral nonlinearity INL fluctuates in 32 input code periods having the same tendency as the fluctuation of the reference current in FIGS. 10 (a), (b), and (c). In the case of 12 (b), it can be confirmed that the absolute value of the fluctuation is not more than half that of FIG. Also from the whole integral nonlinearity INL, in the case of FIG. 12B, the + side is suppressed and is suppressed to around 0LSB, and improvement can be confirmed.

  As described above, the current smoothing circuit 30 </ b> C is a circuit that changes the correction current for each input code Din [2: 0] of the R-2R type DA converter 20. By adding this correction current to the reference current of the D / A converter, the dependency of the reference current on each input code can be reduced.

On the other hand, FIG. 3B shows a specific example of the current-driven current smoothing circuit 30D when the lower bits are 3 bits. This current smoothing circuit 30D includes inverters INV0, INV1, and INV2, and switches SWH0, SWH1, and SWH2 that are turned off when the input codes Din [0], Din [1], and Din [2] are 1, and are turned on when 0. And a current mirror composed of NMOS transistors MN0 to MN3 of the same size. In this embodiment, the drain current IHK flowing through the transistor MN3 by the resistor R5 (resistance value is RHK) is mirrored to the drains of the other transistors MN0, MN1, and MN2. In this case, the drain current IHK of the transistor MN3 is
IHK = (VH−VRL−Vgs) / R5 (8)
It becomes. Here, Vgs is a gate-source voltage of the transistor MN3. A drain current having a current value IHK of Expression (8) flows through the transistors MN0 to MN2. By switching the switches SWH0 to SWH2 with the input code Din [2: 0], these current values can be added according to the input code Din [2: 0]. At this time, by setting the current value IHK to a value close to the value of Vref / RHK (= Vref / 9R), the same effect as that of the resistance-driven current smoothing circuit 30C described in FIG. I can expect.

<Example 2>
FIGS. 5A and 5B show current smoothing circuits 30E and 30F according to the second embodiment when the input code is 3 bits. In the resistance-driven current smoothing circuit 30E of FIG. 5A, each resistor R0 to R2 and a series circuit of switches SWH0, SWH1, and SWH2 are connected in parallel, and inverters INV0, INV1, INV2, and AND circuits AND1, AND2 are used. The encoder is configured to realize the same operation as that described in FIG. Also, in the current-driven current smoothing circuit 30F of FIG. 5B, the series circuits of the transistors MN0 to MN2 and the switches SWH0, SWH1, and SWH2 are connected in parallel, and the inverters INV0, INV1, INV2, and the AND circuit AND1, The encoder is configured by AND2, and the same operation as that described in FIG. 4 is realized.

<Example 3>
FIGS. 6A and 6B show current smoothing circuits 30G and 30H according to the third embodiment in the case where the input code of the lower bits is 5 bits. In the resistance-driven current smoothing circuit 30G of FIG. 6A, binary-weighted resistors R00 (= RHK), R01 (= RHK / 2), R02 (= RHK / 4), R03 (= RHK / 8) ) And a series circuit of switches SWH0, SWH1, SWH2, and SWH3 are connected in parallel, the encoder 31G converts the 5-bit input into 4-bit data, and switches the switches SWH0, SWH1, SWH2, and SWH3. is there.

  By setting the target value of the correction current value to the difference between the maximum value of the reference current and the reference current value in each input code, smoothing the current according to the resolution of the variable resistor (here, 4 bits) Can be reduced to 1/16). In other words, since the reference current for each input code of the R-2R type D / A converter 20 is a known value whose resistance value depends on the resistance of R, the current is a known value that depends on the resistance value RHK. By adding the correction current generated by the smoothing circuit 30, the fluctuation can be canceled out.

  It should be noted here that since both current values are functions of resistance, care is taken in matching the resistance value RHK used in the current smoothing circuit 30G and the resistance value R used in the R-2R type DA converter 20. It is necessary to turn on. This can be achieved with considerations such as disposing at close positions in the same direction in layout design and using the same type of resistors.

  FIG. 7 shows the 4-bit encoder output code SW [3: 0] for the 5-bit input code Din [4: 0] of the R-2R type D / A converter 20 and the correction current of the current smoothing circuit 30G. 13A shows a correction current (output current) of the current smoothing circuit 30G, FIG. 13B shows a combined current (up to 0 to 32 input codes) obtained by combining the correction current and the reference current, and FIG. ) Shows the simulation results of the same combined current (from 0 to 1023 input code). In the simulation, the same configuration and conditions as in the case of FIG. 10 described above were used. From these characteristics, it can be confirmed that the original current fluctuation is suppressed to about 1/10 to about 1/20 in the entire input code (0 to 1023 input code).

  For the present embodiment, for reference, the differential nonlinear characteristic DNL obtained by simulation is shown in FIG. 14A and the integral nonlinearity INL is shown in FIG. 14B for the entire 10-bit D / A converter. Show. The conditions are the same as those in FIGS. Compared to the case without the current smoothing circuit shown in FIGS. 11 (a) and 12 (a), both the differential nonlinear DNL characteristic and the integral nonlinear INL characteristic are 1/5 to 1/10. It can be confirmed that it has dropped.

10: Capacitance voltage dividing type D / A converter 20: R-2R type D / A converter 30: Current smoothing circuit 30A, 20C, 20E, 30G: Resistance driving type current smoothing circuit 30B, 20D, 20F, 30H : Current-driven current smoothing circuit

Claims (6)

A capacitive voltage-dividing D / A converter connected to a reference current wiring and performing higher-order k-bit D / A conversion of input data, and a lower-order m-bit D / A of the remaining input data connected to the reference current wiring An R-2R type D / A converter for performing A conversion, and adding an output voltage of the capacitive voltage dividing type D / A converter and an output voltage of the R-2R type D / A converter to obtain an output voltage In the D / A converter
A current smoothing circuit connected in parallel to the R-2R type D / A converter is provided so as to additionally supply a correction current to the parasitic resistance of the reference current wiring, and the current smoothing circuit includes the lower m bits. A D / A converter, wherein a correction current corresponding to data is additionally supplied to the parasitic resistance. The D / A converter according to claim 1, wherein
The D / A converter characterized in that the current smoothing circuit increases the value of the correction current as the value of the reference current flowing through the R-2R type D / A converter decreases. The D / A converter according to claim 1, wherein
When the reference current corresponding to the even-numbered input code flows, the current smoothing circuit increases the value of the correction current as the reference current decreases. The D / A converter according to claim 1, 2, or 3,
The current smoothing circuit includes: a variable resistance circuit connected in parallel to the R-2R type D / A converter; an encoder that switches a resistance value of the variable resistance circuit according to the lower m-bit input code; A D / A converter comprising: The D / A converter according to claim 1, 2, or 3,
The current smoothing circuit switches a current value of the variable current source circuit according to the variable current source circuit connected in parallel to the R-2R type D / A converter and the lower m-bit input data. An D / A converter comprising an encoder. The D / A converter according to claim 1, 2, 3, 4 or 5,
When the lower m-bit input data is 3 bits, the current smoothing circuit generates a 3 × IHK correction current when the input data is “000” and 2 × IHK when the input data is “100”. Correction current of 1 × IHK when the input data is “010” or “110”, and 0 when the input data is “001”, “011”, “101” or “111”. A D / A converter, wherein a correction current of × IHK is additionally supplied to each of the parasitic resistances. However, when the value of the unit resistance of the R-2R type D / A converter is R and the reference voltage is Vref, IHK = Vref / 9R.

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