JP2004056463A - D/a converter circuit, portable terminal equipment having the same, and audio device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a D/A converter circuit of a plurality of stages, which can prevent occurrence of a glitch without specially disposing a circuit for controlling timing and which can obtain high D/A conversion precision so that monotonicity and continuity of an output analog voltage value can easily be secured. <P>SOLUTION: A comparator compares a voltage level of reference voltage V<SB>H</SB>×V<SB>L</SB>that an initial-stage D/A converter 1 generates in accordance with digital data of high-order m-bits, and outputs a comparison signal CS. An inverter 5 outputs digital data of low-order n-bits when reference voltage V<SB>H</SB>is determined to be higher from the comparison signal CS, and inverts and outputs it when it is determined to be lower. A next-stage R-2 ladder resistance-type D/A converter 2 operates a switch changing over reference voltage V<SB>H</SB>×V<SB>L</SB>by digital data from the inverter 5 and outputs an analog output voltage value corresponding to digital input data Din. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a D / A converter circuit using an R-2R ladder resistor network for converting an input digital signal into an analog signal, and in particular, to a two-stage D / A converter for improving resolution by a two-stage D / A conversion process. It relates to an A-converter circuit.
[0002]
[Prior art]
A D / A (digital-to-analog) converter composed of an R-2R ladder resistor network is a circuit that converts a digital input signal into an analog signal and outputs the signal. For example, an R-2R resistor ladder type D / A converter 70 shown in FIG. , A resistor network 71 composed of resistors having a resistance value of R and 2R (series resistance value of R and R), a switch group 73 connected to the resistor network 71, and an offset level control resistor 72. Is done. FIG. 8 shows a 3-bit example in which the digital input signals D3, D4, and D5 are input to the switches SW3, SW4, and SW5 included in the switch group 73, respectively. The digital input signal D3 is MSB, and the digital input signal D5 is LSB. One end of the offset level control resistor 72 is an offset terminal OFFCR.
[0003]
The operation principle of the R-2R resistance ladder type D / A converter 70 will be described more specifically with reference to FIG. The switches SW3 to SW5 of the switch group 73 are switched to input Vdd when the corresponding digital input is HIGH and input Gnd to the resistor network 71 when the corresponding digital input is LOW. By the input of the digital input signals D3 to D5, the analog output voltage Aout becomes
Aout = ｛(D3 × 2 ² Ten D4 × 2 ¹ Ten D5 × 2 ⁰ ) / 2 ³ ｝ Vdd + offset
Can be expressed as Here, Dn (n = 3, 4, 5) is 0 or 1 (depending on the digital input code). The offset varies depending on the voltage input to the offset terminal OFFCR.
[0004]
As shown in FIG. 9A, when Gnd is input to the offset terminal OFFCR, the analog output becomes Gnd to (Vdd-1 LSB), and when Vdd is input to the offset terminal OFFCR as shown in FIG. 9B. Are (Gnd + 1 LSB) to Vdd. Further, as shown in FIG. 9C, when a voltage having an intermediate value between Gnd and Vdd is input to the offset terminal OFFCR, the analog output takes an intermediate value between FIGS. 8A and 8B.
[0005]
This R-2R resistance ladder type D / A converter 70 outputs the analog output Aout of the above equation when the ratio of R to 2R is exactly 1: 2. However, as is clear from FIG. Due to the on-resistance of SW3 to SW5, the 2R side is 2R + α (α is the on-resistance of the switch). In the content disclosed in Japanese Patent Publication No. 138725 and the like, a switch that is always on is also turned on on the R side to compensate for a 1: 2 ratio between the R side and the 2R side. Further, the resistance value on the 2R side can be originally subtracted by the ON resistance of the switch to compensate for the 1: 2 ratio. In Japanese Patent Application Laid-Open No. 3-77430, a voltage input to an input terminal of an offset level control resistor is switched between an upper limit voltage and a lower limit voltage input to an input terminal on the 2R side, thereby achieving high precision of the resistance element. A high-resolution and high-precision D / A converter has been realized without any attempt to realize a high-resolution D / A converter.
[0006]
Also, as can be seen from the R-2R ladder resistance type D / A converter 70 in FIG. 8, this R-2R resistance ladder type D / A converter has a required number of unit resistances R corresponding to the bit number n of the digital input signal. Is calculated as 3n + 1. Therefore, the binary resistance type D / A converter (unit resistance number 2 for bit number n) ⁿ Compared with -1), the range of use of the resistor can be narrowed, and the accuracy of the resistor can be a high-performance D / A converter only by securing the specific accuracy, not the absolute value. is there.
[0007]
However, the ratio accuracy between the resistors used in the ladder resistor network in the above R-2R ladder resistor type D / A converter can be obtained only up to about 0.05% without trimming, so that the D / A converter of 10 bits or more is used. It is difficult to construct only with the R-2R resistance ladder network.
[0008]
In order to increase the resolution without performing costly trimming, there is a method of performing D / A conversion in two stages (generally, a plurality of stages) as in a two-stage D / A converter circuit 90 shown in FIG. The two-stage D / A converter circuit 90 includes a first-stage D / A converter 91, a next-stage R-2R ladder resistance type D / A converter 92, a latch circuit 93, and a reference voltage generation circuit 94. The first-stage D / A converter 91 that performs the first D / A conversion process of the two-stage process receives the digital input of the upper m bits of the digital input data Din latched by the latch circuit 93 in accordance with the clock signal CK. In the first stage D / A converter 91, the analog output voltage corresponding to the upper m bits and the analog output voltage corresponding to the digital input obtained by adding 1 to the upper m bits are converted to the reference voltage VH · Each reference voltage V _L , Reference voltage V _H Is output as
[0009]
The lower-order n bits of the digital input data Din latched by the latch circuit 93 in accordance with the clock signal CK are provided to the next stage R-2R ladder resistance type D / A converter 92 which performs the D / A conversion process following the two-stage process. Digital input is performed. In the next stage R-2R ladder resistance type D / A converter 92, the reference voltage V input from the first stage D / A converter 91 is used. _L ・ V _H And a final analog signal Aout of the digital input data Din from the lower n bits and outputs the same. The above-described R-2R ladder resistance type D / A converter as shown in FIG. 8 is used as the next-stage R-2R ladder resistance type D / A converter 92, and Vdd in FIG. _HH , GND to the reference voltage V _LL It can be.
[0010]
As an example of the first-stage D / A converter 91, a resistor string type (also called a voltage potentiometer type) D / A converter 91a shown in FIG. 11 is used. FIG. 11 shows an example in which the upper bits of the digital input data Din are 3 bits and 8 stages. The resistor string type D / A converter 91a includes a resistor string 101, reference voltage switches 102 and 103, an upper limit reference voltage V _HH Buffer amplifier 104 and lower reference voltage V _LL A buffer amplifier 105 is provided.
[0011]
The resistor string 101 is a voltage dividing circuit in which resistors r0 to r7 are connected in series. The reference voltage VH is input to one end of the resistor r0, and the reference voltage VL is input to one end of the resistor r7. The reference voltage switch 102 includes switches SH0 to SH7. Each switch sequentially changes the voltage at one end of the reference voltage VH input side of the resistors r0 to r7 to the upper limit reference voltage V _HH This is a switch for inputting to the buffer amplifier 104. The reference voltage switch 103 includes switches SL0 to SL7. Each switch sequentially changes the voltage at one end of the resistors r0 to r7 on the input side of the reference voltage VL to the lower limit reference voltage V _LL This is a switch for inputting to the buffer amplifier 105. Although not shown in FIG. 11, each switch is opened and closed by a control signal corresponding to a decoding result of the upper 3 bits by a decoder inside the first stage D / A converter 91 shown in FIG.
[0012]
Upper reference voltage V _HH The buffer amplifier 104 changes the voltage input through one of the reference voltage switches 102 to the upper limit reference voltage V _HH Is output as Lower reference voltage V _LL The buffer amplifier 105 changes the voltage input through one of the reference voltage switches 103 to the lower limit reference voltage V _LL Is output as
[0013]
In the resistor string type D / A converter 91a having the above configuration, for example, when the upper three bits of the digital input data Din are “111”, the voltages at both ends of the resistor r0 are turned on by the switches SH0 and SL0 and the upper limit reference voltage is set. V _HH And lower limit reference voltage V _LL Is output as When the upper three bits are "110", the switches SH1 and SL1 are turned on to change the voltages at both ends of the resistor r1 to the upper limit reference voltage V. _HH And lower limit reference voltage V _LL Is output as Hereinafter, the reference voltage V is calculated by operating a switch in accordance with the digital input up to the upper three bits “000”. _H ・ V _L Upper limit reference voltage V _HH And lower limit reference voltage V _LL Is output.
[0014]
However, the upper limit reference voltage V used here _HH Buffer amplifier 104 and lower limit reference voltage V _LL Since the output voltage of the buffer amplifier 105 usually has an offset due to the variation of the input transistors of the buffer amplifier, the analog output voltage is switched when the upper bit is switched in the first stage D / A converter 91a as shown in FIG. A discontinuity may occur at the boundary of the range. Therefore, in applications requiring monotonicity and continuity, a resistor string type D / A converter 91b in which the connection of switches is devised as shown in FIG. 13 is used.
[0015]
13 includes a resistor string 111, a reference voltage switch 112, and a reference voltage V. _H Buffer amplifier 113 and reference voltage V _L A buffer amplifier 114 is provided. The resistor string 111 has the same configuration as the resistor string 101 in FIG. The reference voltage switch 112 includes switches SH0 to SH7 and switches SL0 to SL7, and the same switch serves as the switch SLk and the switch SH (k + 1) (k = 0, 1, 2,... 6). The switches SH0, SH2 (SL1), SH4 (SL3), and SH6 (SL5) are sequentially connected to the reference voltage VH at one end of the reference voltage VH of the resistors r0, r2, r4, and r6. _H The switch SL7 is a switch for inputting to the buffer amplifier 113. The switch SL7 is connected to one end of the reference voltage VL input side of the resistor r7. _H This is a switch for inputting to the buffer amplifier 113. The switches SH1 (SL0), SH3 (SL4), SH5 (SL4), and SH7 (SL6) are sequentially connected to the reference voltage VH at one end of the reference voltage VH of the resistors r1, r3, r5, and r7. _L This is a switch for inputting to the buffer amplifier 114. Although not shown in FIG. 13, each switch is opened and closed by a control signal corresponding to a decoding result of upper 3 bits by a decoder inside the resistor string type D / A converter 91b shown in FIG.
[0016]
Reference voltage V _H The buffer amplifier 113 converts the voltage input from the reference voltage switch 112 to the reference voltage V _H And outputs the reference voltage V _L The buffer amplifier 114 converts the voltage input from the reference voltage switch 112 to the reference voltage V _L Is output as
[0017]
In the resistor string type D / A converter 91b having the above-described configuration, for example, when the upper three bits of the digital input data Din are “111”, the voltages at both ends of the resistor r0 are turned on by turning on the switches SH0 and SL0 (SH1). Reference voltage V _H And reference voltage V _L Is output as When the upper three bits are "110", the voltages at both ends of the resistor r1 are changed to the reference voltage V by turning on the switches SH1 (SL0) and SL1 (SH2). _L And reference voltage V _H Is output as Hereinafter, by operating a switch according to the digital input up to the upper three bits “000”, the reference voltage V _H ・ V _L Is output. As a result, no discontinuous point occurs at the boundary of the analog output voltage range when the upper bits are switched in the resistor string type D / A converter 91b.
[0018]
Here, the difference from the resistor string type D / A converter 91a of FIG. _H Is always the reference voltage V _L In contrast, the resistor string type D / A converter 91b outputs the reference voltage V in accordance with the digital input. _H And reference voltage V _L Are alternately switched. As a result, an exchanger 122 is added to the two-stage D / A converter using the resistor string type D / A converter 91b in FIG. 13 as in the two-stage D / A converter circuit 121 shown in FIG.
[0019]
This exchanger 122 has a reference voltage V _H Is the reference voltage V _L When the voltage level is higher than the reference voltage V _H Is the upper limit reference voltage V _HH As the reference voltage V _L Is the lower limit reference voltage V _LL Is output as For the above reason, the reference voltage V _H Is the reference voltage V _L When the voltage level is lower than the reference voltage V _L Is the upper limit reference voltage V _HH As the reference voltage V _H Is the lower limit reference voltage V _LL And is used as a reference voltage of the next stage R-2R ladder type D / A converter 92. Whether these voltage levels are determined and actually exchanged with the reference voltage level is determined based on the decoding result of the upper three bits by the resistor string type D / A converter 91b. _H And reference voltage V _L Is controlled by a control signal CE indicating the magnitude relationship between
[0020]
The exchanger 122 is usually composed of switches such as the switches SW11, SW12, SW13, and SW14 shown in FIG. In FIG. 15A, the control signal CE is input to the switches SW11 and SW14, and the inverted signal CEb of the control signal CE is input to the switches SW12 and SW13. When the switches SW11 and SW14 are on (closed), the switches SW12 and SW13 are turned on. When the switches are off (open) and the switches SW11 and SW14 are off, the switches SW12 and SW13 are controlled to be on. The inverted signal CEb is generated by passing the control signal CE through the inverter 131 as shown in FIG.
[0021]
Thus, the reference voltage V _H And reference voltage V _L A two-stage D / A converter circuit that alternately exchanges the voltage levels with the reference voltage of the next stage D / A converter is referred to as “INTEGRATED ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS”, pp233-234, Kluer Academic Publishers, 1994.
[0022]
[Problems to be solved by the invention]
However, in a two-stage D / A converter circuit using an R-2R ladder resistance type D / A converter in the next stage, the switch includes a plurality of switches as described above, and each switch is turned on due to manufacturing variations of the switches. The resistance may vary. Therefore, the reference voltage V shown in FIG. _H Are at the same voltage level, the upper limit reference voltage V _HH Is output as the lower limit reference voltage V via the SW12. _LL The output voltage level of the exchanger may fluctuate due to the different switches that are turned on, such as whether the output is performed as an output.
[0023]
Also, due to the ON resistance (α) of the switch of the exchanger, the resistance value on the 2R side in the next stage R-2R ladder resistance type D / A converter becomes 2R + α equivalently, and the resistance ratio between R and 2R fluctuates. , Α may not operate as a D / A converter with high accuracy.
[0024]
As described above, in the conventional two-stage D / A converter circuit, the D / A conversion accuracy of the next-stage n-bit R-2R ladder resistance type D / A converter is deteriorated. However, there is a problem that it is difficult to ensure the monotonicity and continuity of the output analog voltage value because the D / A conversion accuracy may deteriorate.
[0025]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem, and an object of the present invention is to provide two types of reference voltages used in the next stage n-bit R-2R ladder resistance type D / A converter by m bits. In performing (m + n) -bit D / A conversion by generating with a D / A converter, high D / A conversion accuracy can be obtained so that monotonicity and continuity of an output analog voltage value can be easily ensured. An object of the present invention is to provide a D / A converter circuit, and a portable terminal device and an audio device including the same.
[0026]
[Means for Solving the Problems]
In order to solve the above problem, a D / A converter circuit according to the present invention includes a first reference voltage and a second reference voltage having different voltage levels according to upper m bits of (m + n) bits of digital input data. And a first D / A converter that generates the digital input data by using the lower n bits of information of the digital input data and the first reference voltage and the second reference voltage. And a second D / A converter of the R-2R ladder resistance type for converting the reference voltage and the second reference voltage into analog voltage values within a range in which a higher voltage level is an upper limit and a lower voltage level is a lower limit. The D / A converter circuit is characterized by taking the following measures.
[0027]
That is, the digital data input to the second D / A converter is applied to each input terminal on the digital data input side of the ladder resistor network of the second D / A converter, the first value of the two values. , The first reference voltage is input, and when the digital data input to the second D / A converter is the second of the two values, the second reference voltage is input. Is entered. Further, the D / A converter circuit compares the voltage levels of the first and second reference voltages respectively output by the first D / A converter, and generates a comparison signal according to the level relationship between the two. Comparing means for comparing the lower-order n-bit digital data with the second D / D signal when the comparison signal indicates that the voltage level of the first reference voltage is higher than the voltage level of the second reference voltage; While input to the A converter, if the comparison signal indicates that the voltage level of the first reference voltage is lower than the second reference voltage level, the first value of the lower n bits of digital data is And inverting means for exchanging the second value and inputting the second value to the second D / A converter.
[0028]
According to the above invention, the provided first D / A converter generates the first and second reference voltages having different voltage levels according to the upper m bits of the (m + n) -bit digital input data, It is input to an R-2R ladder resistor type second D / A converter. The comparing means compares the voltage levels of the first and second reference voltages respectively output by the first D / A converter, and generates a comparison signal according to the level relationship between the two. Indicates that the voltage level of the first reference voltage is higher than the voltage level of the second reference voltage, the lower-order n-bit digital data is directly input to the second D / A converter, while the comparison signal is When the voltage level of the first reference voltage is lower than the second reference voltage level, the first value and the second value of the two values of the lower-order n-bit digital data are replaced with each other, and Input to D / A converter.
[0029]
By the above operation of the inverting means, when digital data is input from the inverting means to each input terminal on the digital data input side of the ladder resistor network of the second D / A converter, the voltage levels of the first and second reference voltages are changed. Irrespective of the level of the digital data, the lower reference bit digital data is always input to the corresponding input terminal when the lower bit digital data has the first value, and the lower reference bit digital data has the second value when the lower bit digital data has the second value. The reference voltage having the lower voltage level is always input to the corresponding input terminal. The second D / A converter converts the digital input data to the first reference voltage using the lower n bits of information, that is, the digital data input from the inverting means, and the first reference voltage and the second reference voltage. The analog voltage value is converted into an analog voltage value within a range in which the higher the voltage level of the voltage and the second reference voltage is, the higher the upper limit and the lower the lower the lower limit.
[0030]
Therefore, even if the first D / A converter has a high / low relationship between the voltage level of the first reference voltage and the voltage level of the second reference voltage depending on the high-order m bits, the first D / A converter can operate the switch or the like. The D / A conversion can be performed by the second D / A converter without using it. Since a switch having a plurality of switches is not required, high D / A conversion accuracy can be obtained.
[0031]
Further, the comparison means generates a comparison signal based on the first and second reference voltages output from the first D / A converter. Therefore, when the comparison signal is generated, the comparison means always generates the first and second reference voltages. The second reference voltage is output. Therefore, the level relationship between the voltage level of the first reference voltage and the voltage level of the second reference voltage is estimated based on the upper m bits of the digital input data, and the inversion / non-inversion operation of the inversion means is controlled. Unlike the configuration, a circuit for controlling timing, specifically, for delaying the inversion / non-inversion operation by the inversion means until the first D / A converter generates the first and second reference voltages. Without providing the circuit described above, the glitch is generated, that is, the processing of the second D / A converter before the first and second reference voltages are output from the first D / A converter. Is started, and an undesirable analog voltage value is output when the digital input data is switched.
[0032]
As a result, two types of reference voltages used in the next stage n-bit R-2R ladder resistance type D / A converter are generated by the m-bit D / A converter, and the (m + n) -bit D / A conversion is performed. It is possible to prevent the occurrence of glitches without providing a circuit for controlling the timing, and to obtain a high D / A conversion accuracy so as to easily ensure monotonicity and continuity of the output analog voltage value. A possible D / A converter circuit can be provided.
[0033]
Further, in order to solve the above problem, the D / A converter circuit according to the present invention, wherein the second D / A converter includes switching means for switching a voltage input to an input terminal of an offset level control resistor. It is characterized by.
[0034]
According to the above invention, the second D / A converter switches the voltage input to the input terminal of the offset level control resistor by the switching means, so that the upper m bits of the (m + n) bits of digital data are switched to the second D / A converter. Monotonicity of the output analog voltage value when the voltage levels of the first and second reference voltages are switched can be ensured.
[0035]
Furthermore, in order to solve the above problem, the D / A converter circuit of the present invention is characterized in that the switching means switches a voltage input to an input terminal of the offset level control resistor based on the comparison signal. .
[0036]
According to the above invention, since the switching means switches the voltage input to the input terminal of the offset level control resistor based on the control signal generated by the comparing means, the switching means automatically changes the voltage input to the input terminal of the offset level control resistance. Can be switched.
[0037]
Further, in order to solve the above-mentioned problem, the D / A converter circuit of the present invention is characterized in that the switching means includes the first reference voltage and the second reference voltage as switching voltages.
[0038]
According to the above invention, the switching means can switch the voltage input to the input terminal of the offset level control resistor between the first reference voltage and the second reference voltage. Also, when the voltage level of the second reference voltage is switched, the differential nonlinearity can be suppressed in the same manner as when only the lower n bits are switched.
[0039]
Further, in the D / A converter circuit according to the present invention, in order to solve the above problem, the switching means includes a CMOS transistor for connecting and disconnecting an input terminal of the offset level control resistor and a plurality of connection terminals having different voltages. A switch having a structure is provided corresponding to each connection terminal, and the voltage input to the input terminal of the offset level control resistor is switched by the connection and the cutoff.
[0040]
According to the above invention, one of the plurality of connection terminals having different voltages is connected to the input terminal of the offset level control resistor by the connection and cutoff by the switch having the CMOS transistor structure, and is input to the input terminal of the offset level control resistor. Switch the voltage. Accordingly, a configuration for switching the voltage input to the input terminal of the offset level control resistor can be easily created by the CMOS process.
[0041]
Further, in order to solve the above-mentioned problem, the D / A converter circuit of the present invention is characterized in that the switch is operated in a complementary type of a P-type and an N-type.
[0042]
According to the above invention, each switch operates in a complementary manner of the P-type and the N-type, so that the switch can pass the entire range from the power supply voltage of each connection terminal to the GND level, and the dynamic range of the D / A converter circuit can be improved. The range can be expanded.
[0043]
Further, in order to solve the above problem, the D / A converter circuit of the present invention is arranged so that the signal line is provided in parallel with the signal line between the switch of the signal line provided with the switch and the input terminal of the offset level control resistor. A dummy switch composed of a P-type MOS transistor and an N-type MOS transistor in parallel with each other and having a gate signal input to the MOS transistor of each polarity in opposite phase to a gate signal input to the MOS transistor of the switch of the same polarity. It is characterized by having.
[0044]
According to the above invention, the provision of the dummy switch makes it possible to cancel clock noise generated when each switch shifts from the on state to the off state.
[0045]
Further, in order to solve the above-mentioned problem, the D / A converter circuit of the present invention is formed in one integrated circuit, and the first D / A converter is provided with the first reference voltage and the second reference voltage. And an original reference voltage generating means for generating an original reference voltage for generating the reference voltage.
[0046]
According to the invention, the original reference voltage for the first D / A converter to generate the first reference voltage and the second reference voltage is generated by the original reference voltage generation means in the same integrated circuit. Therefore, there is no need to apply an original reference voltage from outside the integrated circuit.
[0047]
According to another aspect of the invention, there is provided a portable terminal device including any one of the D / A converter circuits.
[0048]
According to the above invention, in a portion that performs D / A conversion, such as a control voltage generation circuit of an analog front end of a portable terminal device, a high D value is provided so that monotonicity and continuity of an output analog voltage value can be easily ensured. / A conversion accuracy can be obtained.
[0049]
According to another embodiment of the invention, there is provided an audio apparatus including any one of the above D / A converter circuits.
[0050]
According to the above invention, high D / A conversion accuracy is obtained in a portion that performs D / A conversion, such as a volume control circuit of an audio device, so that monotonicity and continuity of an output analog voltage value can be easily ensured. be able to.
[0051]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0052]
FIG. 1 shows a configuration of a D / A converter 10 according to the present embodiment. The D / A converter 10 is a two-stage (m + n) -bit D / A converter, and includes a first-stage D / A converter 1, a next-stage R-2R ladder resistance type D / A converter 2, a latch circuit 3, a comparator 4, and an inverter. 5 and a reference voltage generation circuit 6. However, as shown in FIG. 14 and the like, an exchange for exchanging a reference voltage having a higher voltage level with an upper-limit reference voltage and exchanging a reference voltage having a lower voltage level with a lower-limit reference voltage is not used.
[0053]
The upper-order bit number m and the lower-order bit number n of the (m + n) -bit digital input data Din are not particularly limited.
[0054]
The first stage D / A converter (first D / A converter) 1 generates a first reference voltage and a second reference voltage having different voltage levels according to the upper m bits of the digital input data Din. Here, in order to ensure that the D / A converter 10 can ensure monotonicity and continuity with a high resolution of, for example, 10 bits or more, the first-stage D / A converter 1 has an analog output when the upper m bits are switched. The resistor string type D / A converter 91b of FIG. 14 which does not generate a discontinuity at the boundary of the voltage range is used, _H Is the first reference voltage, the reference voltage V _L Is the second reference voltage.
[0055]
The next stage R-2R ladder resistance type D / A converter 2 will be described later.
[0056]
The latch circuit 3 latches the digital input data Din according to the input clock signal CK, outputs the upper m bits of digital data, inputs the digital data to the first stage D / A converter 1, and outputs the lower n bits of digital data. And input to the inverter 5.
[0057]
The comparator (comparing means) 4 is provided with a reference voltage V input from the first stage D / A converter 1. _H Voltage level and reference voltage V _L Is determined, and a comparison signal CS corresponding to the determined height relationship is generated and output. Reference voltage V _H Voltage level is the reference voltage V _L Higher than the voltage level (V _H > V _L ), The comparison signal CS = HIGH, and the reference voltage V _H Voltage level is the reference voltage V _L Lower than the voltage level (V _H <V _L ), The comparison signal CS = LOW. The output comparison signal CS is input to the inverter 5 and the next stage R-2R ladder resistance type D / A converter 2.
[0058]
The inverter (inverting means) 5 inputs the lower-order n-bit digital data as it is to the next stage R-2R ladder resistance type D / A converter 2 when the comparison signal CS is HIGH, while when the comparison signal CS is LOW. The first value and the second value of the two values of the lower-order n-bit digital data are exchanged and input to the next stage R-2R ladder resistance type D / A converter 2. Here, the first value is 1 and the second value is 0.
[0059]
The reference voltage generation circuit (original reference voltage generation means) 6 is configured such that the first-stage D / A converter 1 _H And reference voltage V _L Are generated and output using, for example, a band gap reference circuit or the like, which is an original reference voltage for generating the first reference voltage, and input to the first-stage D / A converter 1.
[0060]
The next stage R-2R ladder resistance type D / A converter (second D / A converter) 2 is configured to output information of the lower n bits of the digital input data Din and the reference voltage V _H And reference voltage V _L Is used to convert the digital input data Din to the reference voltage V _H And reference voltage V _L Is converted to an analog voltage value within a range in which the higher voltage level is the upper limit and the lower voltage level is the lower limit, and is output. The information of the lower n bits is digital data input from the inverter 5, and is the lower n bits of digital data itself when the comparison signal CS is HIGH, and is lower n bits when the comparison signal CS is LOW. Are digital data in which 1 and 0 are interchanged.
[0061]
As shown in FIG. 2, the next-stage R-2R ladder resistance type D / A converter 2 includes a resistance network 21, an offset level control resistance 22, a switch group 23, and a connection switching unit 24. The resistance network 21 and the offset level control resistance 22 form a ladder resistance network.
[0062]
The resistor network 21 includes eight resistors having a resistance value R, nodes N3, N4, and N5 where the resistors are ladder-connected in accordance with the number n of lower bits, and the most significant bits of the lower n bits (four bits of the digital input data Din). I) The input terminal P3 on the input side, the input terminal P4 on the fifth bit input side of the digital input data Din, and the input terminal P5 on the input side of the least significant bit of the lower n bits (the sixth bit of the digital input data Din) Have. The nodes N3 and N4, and the nodes N4 and N5 are connected by resistors having a resistance value R, respectively. The node N3 and the input terminal P3, the node N4 and the input terminal P4, and the node N5 and the input terminal P5 are connected by a resistor having a resistance value of 2R (a series resistance of two resistors having a resistance value R). Further, an analog output voltage Aout corresponding to the digital input data Din is output from the node N3.
[0063]
The offset level control resistor 22 includes two resistors having a resistance value R and an input terminal PC to which an offset level control voltage is input. The node N5 and the input terminal PC are connected by a resistor having a resistance value of 2R (a series resistance of the two resistors having the resistance value R).
[0064]
The switch group 23 includes switches SW3, SW4, and SW5. The switch SW3 connects the node P3 to the reference voltage V _H Is applied to the connection terminal Q3 and the reference voltage V. _L Is a switch that connects to and disconnects from the connection terminal R3 to which is applied. The switch SW4 connects the node P4 to the reference voltage V _H Is applied to the connection terminal Q4 and the reference voltage V. _L Is a switch that connects to and disconnects from the connection terminal R4 to which is applied. The switch SW5 connects the node P5 to the reference voltage V _H Is applied to the connection terminal Q5 and the reference voltage V. _L Is a switch that connects to and disconnects from the connection terminal R5 to which is applied. To the switches SW3, SW4, and SW5, digital data D3, D4, and D5 of the lower n bits output from the inverter 5 are input as control signals for switching the connection and cutoff. When the digital data is 1, the nodes P3, P4, P5 are connected to the connection terminals Q3, Q4, Q5, and when the digital data is 0, the nodes P3, P4, P5 are connected to the connection terminals R3, R4, R5. Connect to
[0065]
The connection switching unit (switching means) 24 includes a switch SWC. The switch SWC is a switch that connects and disconnects the input terminal PC to a plurality of connection terminals, here, the connection terminal V1 and the connection terminal V2. In the present embodiment, the connection terminal V1 has the reference voltage V _H Is applied, and the reference voltage V is applied to the connection terminal V2. _L Is applied. In addition, the reference voltage V _H And reference voltage V _L May be connected to a connection terminal to which an intermediate voltage is applied. The switch SWC can switch between the connection and the cutoff by the comparison signal CS, thereby switching the offset level control voltage.
[0066]
Next, the operation of the D / A converter 10 having the above configuration will be described.
[0067]
Here, the operation of the first-stage D / A converter 1 will be described again with reference to FIG. 13 includes a resistor string 111, a reference voltage switch 112, and a reference voltage V. _H Buffer hum 113 and reference voltage V _L A buffer amplifier 114 is provided. For example, when the digital input of the high-order m bits is “111”, the switches SH0 and SL0 (same as SH1) are turned on by turning on the switches SH0 and SL0 (reference voltage V). _H And reference voltage V _L Is output as When the upper m bits are “110”, the voltages at both ends of the resistor r1 are changed to the reference voltage V by turning on the switches SH1 (same as S10) and SL1 (same as SH2). _L And reference voltage V _H Is output as Hereinafter, by operating a switch according to the digital input up to the upper m bits “000”, the reference voltage V _H ・ V _L Is output.
[0068]
Here, the difference from the resistor string type D / A converter 91a of FIG. _H Is always the reference voltage V _L On the other hand, the resistor string type D / A converter 91b outputs the reference voltage V in accordance with the m-bit digital input. _H And reference voltage V _L Are alternately switched. That is, in the case of a digital input of upper m bits in which the even switches SHx and SLx (x is an even number) are turned on, the reference voltage V _H Voltage level is the reference voltage V _L Higher than the level. Therefore, the comparison signal CS output from the comparator 4 becomes HIGH. On the other hand, in the case of a high-order m-bit digital input in which the odd switches SHy and SLy (y is an odd number) are turned on, the reference voltage V _L Voltage level is the reference voltage V _H , The comparison signal CS = LOW. By this operation, as shown in FIG. 3, in the resistor string type D / A converter 91b, no discontinuity point occurs at the boundary of the analog output voltage range when the upper m bits are switched.
[0069]
The analog output voltage range of the next stage R-2R ladder resistance type D / A converter 2 for a certain upper m bits is such that a reference voltage V _H Is input to the connection terminal V2. _L Is input to the input terminal PC by the comparison signal CS. _L Is input as shown in FIG. 4 (a). _L ~ (V _H -1 LSB), and the reference voltage V is applied to the input terminal PC by the comparison signal CS. _H Is input as shown in FIG. 4B. _L +1 LSB) to V _H Range.
[0070]
The switch SWC connects the input terminal PC to the V2 terminal (reference voltage V _L 5) shows the analog output voltage range of the next-stage R-2R ladder resistance type D / A converter 2 for each upper m bits when fixedly connected to FIG.
[0071]
When the digital input of the upper m bits is "111", the switches SH0 and SL0 (same as SH1) are turned on by turning on the switches SH0 and SL0 in FIG. _H And reference voltage V _L Is output as In this case, the reference voltage V _H Is the reference voltage V _L Therefore, the comparison signal CS output from the comparator 4 becomes HIGH, and the lower-order n-bit digital data is input to the next stage R-2R ladder resistance type D / A converter 2 without being inverted by the inverter 5. Is done. When the input upper m bits are “111”, the analog output voltage in the range of the lower n bits of digital data “111” to “000” is “switch state 0 (SH0 / SL0)” in FIG. Reference voltage range to be selected in "."
[0072]
Next, when the input high-order m-bit digital data is “110”, the switches SH1 (same as SL0) and SL1 (same as SH2) are turned on to change the respective voltages at both ends of the resistor r1 in FIG. V _L And reference voltage V _H Is output as In this case, the reference voltage V _H Is the reference voltage V _L Therefore, the comparison signal CS output from the comparator 4 becomes LOW, and the lower n bits of digital data are inverted by the inverter 5 and input to the next stage R-2R ladder resistance type D / A converter 2. You. When the input high-order m bits are “110”, the analog output voltage in the low-order n-bit digital data range “111” to “000” is “switch state 1 (SH1 / SL1)” in FIG. Reference voltage range to be selected in "."
[0073]
Next, when the input high-order m-bit digital data is "101", the voltages at both ends of the resistor r2 in FIG. 13 are set by turning on the switches SH2 (same as SL1) and SL2 (same as SH3). Voltage V _H And reference voltage V _L Is output as In this case, the reference voltage V _H Is the reference voltage V _L Therefore, the comparison signal CS output from the comparator 4 becomes HIGH, and the lower-order n-bit digital data is input to the next stage R-2R ladder resistance type D / A converter 2 without being inverted by the inverter 5. Is done. When the input upper m bits are “101”, the analog output voltage in the range of the lower n bits of digital data “111” to “000” is “switch state 2 (SH2 / SL2)” in FIG. Reference voltage range to be selected in "."
[0074]
Here, looking at the analog output voltage range in FIG. 5A, when the upper m bits are “111” and the lower n bits are “000”, the upper m bits are “110” and the lower n bits are “111”. ”, The same analog output voltage value is taken (the difference is 0 LSB), and when the upper m bits are“ 110 ”and the lower n bits are“ 000 ”, and when the upper m bits are“ 101 ”and the lower n It can be seen that the analog output voltage value has a difference of 2 LSB when the bit is “111”. From this figure, the analog output voltage value of the next stage R-2R ladder resistance type D / A converter 2 when the switch state is odd with respect to the upper m bits (for example, the upper m bits are “110”) is lowered by 1 LSB. It can be seen that by changing to (1), as shown in FIG. 5 (b), at every bit, an even change of 1 LSB is obtained (that is, differential nonlinearity: DNL = 0).
[0075]
That is, when the switch state is an even number for the upper m bits, that is, when the comparison signal CS is HIGH, the switch SWC of the connection switching unit 24 connects the input terminal PC of the offset level control resistor 22 to the connection terminal V2 (reference voltage V2). _L ), And when the switch state is an even number for the upper m bits, that is, when the comparison signal CS = LOW, the input terminal PC of the offset level control resistor 22 is connected to the connection terminal V1 ( Reference voltage V _H ) Is switched between connection and disconnection of the switch SWC. Therefore, the upper m bits are “111”, “101”, “011”, “001” and the reference voltage V _H Is the reference voltage V _L When the comparison signal CS = HIGH, the reference voltage V is applied to the input terminal PC of the offset level control resistor 24. _H And the upper m bits are “110”, “100”, “010”, “000” and the reference voltage V _H Is the reference voltage V _L When the comparison signal CS is low, that is, when the comparison signal CS is LOW, the reference voltage V is applied to the input terminal PC of the offset level control resistor 24. _L Switch to input. As described above, by switching the switch SWC of the connection switching unit 24 according to the value of the digital data of the upper m bits, a change of 1 LSB as shown in FIG. 5B (differential nonlinearity: DNL = 0) and the discontinuity is compensated.
[0076]
Note that the reference voltage V _H ・ V _L Is input to the switch group 23 and the connection switching unit 24 without passing through an exchange or the like, and therefore, when it receives a fluctuation, monotonicity until input to these is ensured. Further, since the resistances of the switches SW3 to SW5 of the switch group 23 can be adjusted as described later, monotonicity can still be ensured even after passing through the switch group 23. On the other hand, only the input voltage to the offset level control resistor 22 receives a change due to the switch SWC of the connection switching unit 24, and the offset level control resistor 22 is used not for the D / A conversion itself but for the offset control. When the input voltage to the control resistor 22 is the reference voltage V _H ・ V _L No matter which of the values is taken, the analog output voltage Aout is affected only by 1 LSB or less. Therefore, the D / A conversion accuracy does not deteriorate due to the ON resistance of the switch SWC.
[0077]
As described above, according to the D / A converter circuit 10 according to the present embodiment, the first-stage D / A converter 1 _H Voltage level and reference voltage V _L D / A conversion by the next stage R-2R ladder resistance type D / A converter 2 without using an exchange or the like, even if the relationship between the voltage level and the voltage level changes according to the upper m bits. Can be. Since a switch having a plurality of switches is not required, high D / A conversion accuracy can be obtained.
[0078]
Further, the comparator 4 detects both reference voltages V output by the first-stage D / A converter 1. _H ・ V _L Are compared to generate the comparison signal CS. Therefore, when the comparison signal CS is generated, the two reference voltages V _H ・ V _L Is output.
[0079]
Here, for example, based on the upper m bits of the digital input data Din, both reference voltages V _H ・ V _L When the inversion / non-inversion operation of the inverter 5 is controlled based on the estimation result, the operation speed of the circuit to be estimated is higher than the operation speed of the first-stage D / A converter 1. When the digital input data Din is switched, the correct reference voltage V _H ・ V _L Before is output, there is a possibility that a control signal indicating the estimation result is output. In this case, a circuit for controlling the timing (for example, a latch circuit for delaying the control signal, etc.) is provided, and the inversion / non-inversion operation of the inverter 5 is not delayed unless both reference voltages are supplied from the first stage D / A converter 1. V _H ・ V _L Is output before the D / A conversion process of the next stage R-2R ladder resistance type D / A converter 2 starts, and when the digital input data Din is switched, an undesired analog output voltage Aout (D / A The converter may output "glitch").
[0080]
On the other hand, in the D / A converter circuit 10 according to the present embodiment, the comparator 4 uses the two reference voltages V output from the first-stage D / A converter 1. _H ・ V _L Are compared to generate the comparison signal CS. Therefore, when the comparison signal CS is generated, the two reference voltages V _H ・ V _L Is output. As a result, it is possible to prevent the occurrence of glitches when switching the digital input data Din, especially without providing a circuit for controlling the timing.
[0081]
As a result, two types of reference voltages used in the next-stage n-bit R-2R ladder resistance type D / A converter are generated by the m-bit D / A converter and the (m + n) -bit D / A conversion is performed. To prevent the occurrence of glitches without particularly providing a circuit for controlling timing, and to obtain high D / A conversion accuracy so that monotonicity and continuity of an output analog voltage value can be easily ensured. And a D / A converter circuit capable of performing the above.
[0082]
Further, according to the D / A converter circuit 10, the next stage R-2R ladder resistance type D / A converter 2 switches the voltage input to the input terminal PC of the offset level control resistor 22 by the connection switching unit 24. When the upper m bits of the (m + n) -bit digital data are switched, the reference voltage V _H ・ V _L , The monotonicity of the output analog voltage value when the voltage level changes.
[0083]
Further, according to the D / A converter circuit 10, the connection switching unit 24 switches the voltage input to the input terminal PC of the offset level control resistor 22 based on the comparison signal CS generated by the comparator 4, so that the input terminal PC Can be automatically switched.
[0084]
Further, according to the D / A converter circuit 10, the reference voltage V _H And reference voltage V _L And the voltage inputted to the input terminal PC is changed to the reference voltage V _H And reference voltage V _L Can be switched to the reference voltage V by switching the upper m bits. _H And reference voltage V _L , The differential non-linearity can be suppressed in the same manner as when only the lower n bits are switched.
[0085]
Also, the D / A converter circuit 10 has been described as being provided with the resistor string type D / A converter circuit 91b as the first stage D / A converter 1, but the first stage for the next stage R-2R ladder resistance type D / A converter 2 is provided. As the D / A converter 1, the reference voltage V _H ・ V _L Can be provided as long as it is a D / A converter that outputs. Reference voltage V _H ・ V _L May be constant.
[0086]
In FIG. 2, the offset level control voltage switching unit 24 is added to the most basic R-2R resistance ladder type D / A converter as the next stage D / A converter of the first stage D / A converter 1 as described above. The added configuration is shown. The R-2R resistor ladder type D / A converter used in the D / A converter of the next stage has a switch which is always on on the R side in order to surely make the ratio between the resistance value R and the resistance value 2R 1: 2. The connection is switched to the R-2R resistance ladder type D / A converter which compensates the ratio of 1: 2 by forming the inserted configuration or the resistance as the resistance value 2R by subtracting the ON resistance of the switches of the switch group 23 from the beginning. It is also possible to use a configuration that realizes a ratio of 1: 2 including the ON resistance of the switch, such as a configuration in which the unit 24 is added.
[0087]
Further, the switches SW3 to SW5 constituting the switch group 23 of the next stage R-2R resistance ladder type D / A converter 2 and the switch SWC of the connection switching unit 24 have a CMOS transistor structure as shown in FIG. Is preferred. According to this, a configuration for switching the voltage input to the input terminal PC of the offset level control resistor 22 can be easily created by the CMOS process. When a signal D is given as a signal for controlling the operation of these switches, an inverted signal DB is generated from the signal D by the inverter 31 as shown in FIG. 6A, and as shown in FIG. The signal D is input to the gates of the N-type MOS transistor 32 and the P-type MOS transistor 35, and the inverted signal DB is input to the gates of the P-type MOS transistor 33 and the N-type MOS transistor 34. In the case of the switches SW3 to SW5, the signal D corresponds to digital data D3 to D5 input from the inverter 5, and in the case of the switch SWC, the signal D corresponds to a signal obtained by inverting the comparison signal CS. The terminal OUT is the input terminal P3 to P5 in the case of the switches SW3 to SW5, and is the input terminal PC in the case of the switch SWC.
[0088]
In the case of FIG. 6, the N-type MOS transistor 32 and the P-type MOS transistor 33, the N-type MOS transistor 34 and the P-type MOS transistor 35 are analog switches that operate in pairs, and each switch is a P-type MOS transistor. The transistor operates in a complementary manner with the N-type MOS transistor. Reference voltage V _H , V _L Is at a level close to the power supply voltage, the N-type MOS transistors 32 and 34 are turned on, and the reference voltage V _H , V _L Is at a level close to the ground, the P-type MOS transistors 33 and 35 are turned on. Therefore, the connection terminals Q3 to Q5 and QC and the connection terminals R3 to R5 and RC pass through the entire range from the power supply voltage to the ground level. Therefore, the dynamic range of the D / A converter circuit 10 can be expanded.
[0089]
Further, as shown in FIG. 7B, an N-type MOS transistor 41 and a P-type MOS transistor 42 and an N-type MOS transistor 43 and a P-type MOS transistor 44 may be provided as dummy switches. FIG. 7A shows a state where the inverted signal DB is generated from the signal D by the inverter 31 as in FIG. 6A. The N-type MOS transistor 41 and the P-type MOS transistor 42 are parallel to each other, and are connected between the N-type MOS transistor 32 and the P-type MOS transistor 33 and the terminal OUT. It is provided so as to be in parallel with the provided signal line. The N-type MOS transistor 41 and the P-type MOS transistor 32, which have the same polarity, are input to the N-type MOS transistor 32 and the P-type MOS transistor 33 having the same polarity, respectively, with their gate signals having opposite phases. The relationship between the N-type MOS transistor 41 and the P-type MOS transistor 42 with respect to the N-type MOS transistor 34 and the P-type MOS transistor 35 is the same as that of the N-type MOS transistor 41 and the P-type MOS transistor 42. This is the same as the relation for the transistor 33.
[0090]
Thus, the dummy switch including the N-type MOS transistor 41 and the P-type MOS transistor 42 is connected in series with the analog switch including the N-type MOS transistor 32 and the P-type MOS transistor 33, and the N-type MOS transistor 43 and the P-type MOS transistor The dummy switch composed of the type MOS transistor 44 is connected in series with the analog switch composed of the N-type MOS transistor 34 and the P-type MOS transistor 35. Therefore, the charge accumulated between the source-bulk and the drain-bulk when the analog switch is turned on cancels the noise (clock noise) generated by clock feedthrough distributed when the analog switch transitions from the on state to the off state. Can be.
[0091]
Further, the above-described D / A converter circuit 10 can be formed in one integrated circuit. At this time, since the first-stage D / A converter 1 is provided with the reference voltage generating circuit 6 that supplies the reference voltages VH and VL, the reference voltages VH and VL can be generated in the same integrated circuit. There is no need to provide an external reference voltage.
[0092]
Further, the above-described D / A converter circuit 10 can be used as a control voltage generation circuit in an analog front end (AFE: Analog Front End) in a portable terminal device of W-CDMA (Wideband-Code Division Multiple Access) specification, for example. it can. Accordingly, high D / A conversion accuracy can be obtained in the portion of the control voltage generation circuit that performs D / A conversion so that monotonicity and continuity of the output analog voltage value can be easily ensured.
[0093]
Further, the above-described D / A converter circuit 10 can also be used for a volume control circuit or the like of an audio device. This makes it possible to obtain high D / A conversion accuracy in a portion of the volume control circuit that performs D / A conversion so that monotonicity and continuity of the output analog voltage value are easily ensured.
[0094]
【The invention's effect】
As described above, in the D / A converter circuit of the present invention, each input terminal on the digital data input side of the ladder resistor network of the second D / A converter is input to the second D / A converter. The first reference voltage is input when the digital data is the first of the two values, and the digital data input to the second D / A converter is the first of the two values. 2, the second reference voltage is input, and the first and second D / A converters compare the voltage levels of the first and second reference voltages, respectively. Comparing means for generating a corresponding comparison signal; and when the comparison signal indicates that the voltage level of the first reference voltage is higher than the voltage level of the second reference voltage, the lower-order n-bit digital data is output. The second The first value of the lower-order n-bit digital data when the comparison signal indicates that the voltage level of the first reference voltage is lower than the second reference voltage level. And an inverting means for replacing the second value with the second value and inputting the second value to the second D / A converter.
[0095]
Therefore, even if the first D / A converter has a high / low relationship between the voltage level of the first reference voltage and the voltage level of the second reference voltage in accordance with the high-order m bits, The D / A conversion can be performed by the second D / A converter without using such a method. Since a switch having a plurality of switches is not required, high D / A conversion accuracy can be obtained. Further, since the comparison means generates a comparison signal based on the first and second reference voltages output from the first D / A converter, the comparison signal can be obtained without providing a circuit for controlling timing. Are generated, the first and second reference voltages are always output.
[0096]
As a result, two types of reference voltages used in the next stage n-bit R-2R ladder resistance type D / A converter are generated by the m-bit D / A converter, and the (m + n) -bit D / A conversion is performed. It is possible to prevent the occurrence of glitches without providing a circuit for controlling the timing, and to obtain a high D / A conversion accuracy so as to easily ensure monotonicity and continuity of the output analog voltage value. There is an effect that a D / A converter circuit that can be provided can be provided.
[0097]
Further, in the D / A converter circuit of the present invention, as described above, the second D / A converter is provided with switching means for switching the voltage input to the input terminal of the offset level control resistor.
[0098]
Therefore, there is an effect that the monotonicity of the output analog voltage value can be secured when the voltage level of the first and second reference voltages is switched by switching the upper m bits of the (m + n) -bit digital data. .
[0099]
Further, in the D / A converter circuit of the present invention, as described above, the switching means switches the voltage input to the input terminal of the offset level control resistor based on the comparison signal.
[0100]
Therefore, there is an effect that the voltage input to the input terminal of the offset level control resistor can be automatically switched.
[0101]
Further, as described above, the D / A converter circuit of the present invention has a configuration including the first reference voltage and the second reference voltage as the voltage to be switched by the switching means.
[0102]
Therefore, even when the voltage levels of the first and second reference voltages are switched by switching the upper m bits, the differential nonlinearity can be suppressed in the same manner as when only the lower n bits are switched. To play.
[0103]
Further, in the D / A converter circuit of the present invention, as described above, the switching means switches the CMOS transistor structure for connecting and disconnecting the input terminal of the offset level control resistor and a plurality of connection terminals having different voltages. Corresponding to each connection terminal, and the voltage input to the input terminal of the offset level control resistor is switched by the connection and the cutoff.
[0104]
Therefore, there is an effect that the configuration for switching the voltage input to the input terminal of the offset level control resistor can be easily created by the CMOS process.
[0105]
Further, the D / A converter circuit of the present invention has a configuration in which the switch operates in a complementary manner of the P-type and the N-type as described above.
[0106]
Therefore, it is possible to pass the entire range from the power supply voltage of each connection terminal to the GND level, and it is possible to expand the dynamic range of the D / A converter circuit.
[0107]
Further, as described above, the D / A converter circuit according to the present invention is arranged such that the signal line is provided between the switch of the signal line provided with the switch and the input terminal of the offset level control resistor in parallel with the signal line. A dummy switch which is comprised of a parallel P-type MOS transistor and an N-type MOS transistor and has a gate signal input to the MOS transistor of each polarity having a phase opposite to that of the gate signal input to the MOS transistor of the switch having the same polarity is provided. is there.
[0108]
Therefore, it is possible to cancel clock noise generated when each switch changes from the on state to the off state.
[0109]
Further, as described above, the D / A converter circuit of the present invention is formed in one integrated circuit, and the first D / A converter generates the first reference voltage and the second reference voltage. Reference voltage generating means for generating an original reference voltage for use.
[0110]
Therefore, there is an effect that there is no need to supply the original reference voltage from outside the integrated circuit.
[0111]
Further, the portable terminal device of the present invention has a configuration including any one of the D / A converter circuits as described above.
[0112]
Therefore, in a portion that performs D / A conversion, such as a control voltage generation circuit of an analog front end of a portable terminal device, a high D / A conversion accuracy such that monotonicity and continuity of an output analog voltage value are easily ensured. Is obtained.
[0113]
Further, the audio device of the present invention has a configuration including any one of the D / A converter circuits as described above.
[0114]
Therefore, in a portion that performs D / A conversion, such as a volume control circuit of an audio device, high D / A conversion accuracy can be obtained so that monotonicity and continuity of an output analog voltage value can be easily ensured. It works.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a D / A converter according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a next stage R-2R ladder resistance type D / A converter provided in the D / A converter of FIG. 1;
3 is an input-output correspondence diagram showing a range of an analog output voltage with respect to an upper bit digital input of a first stage D / A converter included in the D / A converter of FIG. 1;
4 (a) and 4 (b) show an example of a range of an analog output voltage with respect to a lower bit digital input in a specific upper bit of a next stage R-2R ladder resistance type D / A converter of FIG. 2; It is an output correspondence diagram.
5 (a) and 5 (b) are input-output correspondence diagrams showing a range of an analog output voltage with respect to a lower bit digital input in each upper bit of a next stage R-2R ladder resistance type D / A converter of FIG. 2; It is.
FIGS. 6A and 6B are circuit diagrams showing a circuit used when each switch of the next stage R-2R ladder resistance type D / A converter in FIG. 2 is configured by a CMOS switch;
7 (a) and 7 (b) show circuits used when each switch of the next stage R-2R ladder resistance type D / A converter of FIG. 2 is constituted by a CMOS switch and further provided with a dummy switch. It is a circuit diagram.
FIG. 8 is a circuit diagram showing a configuration of a conventional R-2R ladder resistance type D / A converter.
FIGS. 9A to 9C are input-output correspondence diagrams showing a range of an analog output voltage with respect to digital input data of the R-2R ladder resistance type D / A converter of FIG. 8;
FIG. 10 is a block diagram showing a configuration of a conventional two-stage D / A converter.
11 is a circuit diagram showing a configuration of a first-stage D / A converter included in the two-stage D / A converter of FIG. 10;
12 is an input-output correspondence diagram showing a range of an analog output voltage with respect to an upper bit digital input of the first stage D / A converter of FIG. 11;
FIG. 13 is a circuit diagram showing a configuration of another initial stage D / A converter included in a conventional two-stage D / A converter.
14 is a block diagram showing a configuration of a conventional two-stage D / A converter including the first-stage D / A converter of FIG.
FIGS. 15 (a) and (b) are circuit diagrams showing a circuit used when configuring an exchange included in the two-stage D / A converter of FIG. 14;
[Explanation of symbols]
1 First-stage D / A converter (first D / A converter)
Secondary stage R-2R ladder resistance type D / A converter (second D / A converter)
Inverter)
4 Comparator (comparing means)
5 Inverter (inversion means)
6. Reference voltage generation circuit (Original reference voltage generation means)
10 D / A converter circuit
22 Offset level control resistor
24 connection switching unit (switching means)
32, 34 N-type MOS transistor
33, 35 P-type MOS transistor
41, 43 N-type MOS transistors
42,44 P-type MOS transistor
91b Resistor string type D / A converter (first D / A converter)
CS comparison signal
D3 to D5 Digital data
P3 to P5 input terminal
PC input terminal
QC, RC connection terminal
SWC switch
VH, VL Original reference voltage
V _H Reference voltage (first reference voltage)
V _L Reference voltage (second reference voltage)

Claims (10)

A first D / A converter for generating a first reference voltage and a second reference voltage having different voltage levels according to upper m bits of (m + n) -bit digital input data;
Using the lower n bits of information of the digital input data and the first reference voltage and the second reference voltage, the digital input data is converted to the voltage level of the first reference voltage and the second reference voltage. In a D / A converter circuit including an R-2R ladder resistance type second D / A converter that converts an analog voltage value within a range in which a higher one is an upper limit and a lower one is a lower limit,
At each input terminal on the digital data input side of the ladder resistor network of the second D / A converter, the digital data input to the second D / A converter is the first of two values. When the first reference voltage is input, and when the digital data input to the second D / A converter is the second of the two values, the second reference voltage is input. And
Comparing means for comparing the voltage levels of the first and second reference voltages respectively output by the first D / A converter and generating a comparison signal according to the level relationship between the first and second reference voltages;
When the comparison signal indicates that the voltage level of the first reference voltage is higher than the voltage level of the second reference voltage, the lower-order n-bit digital data is directly input to the second D / A converter. On the other hand, if the comparison signal indicates that the voltage level of the first reference voltage is lower than the second reference voltage level, the first value of the lower-order n-bit digital data and the second value A D / A converter circuit comprising: inverting means for inputting a value to the second D / A converter after replacing the value. 2. The D / A converter circuit according to claim 1, wherein the second D / A converter includes switching means for switching a voltage input to an input terminal of the offset level control resistor. 3. The D / A converter circuit according to claim 2, wherein said switching means switches a voltage input to an input terminal of said offset level control resistor based on said comparison signal. 4. The D / A converter circuit according to claim 2, wherein the switching means includes the first reference voltage and the second reference voltage as voltages to be switched. 5. The switching means includes a switch having a CMOS transistor structure for connecting and disconnecting an input terminal of the offset level control resistor and a plurality of connection terminals having different voltages, corresponding to each connection terminal. 5. The D / A converter circuit according to claim 2, wherein a voltage input to an input terminal of the offset level control resistor is switched. 6. The D / A converter circuit according to claim 5, wherein said switch is operated in a complementary type of a P-type and an N-type. A P-type MOS transistor and an N-type MOS transistor are connected in parallel with the signal line between the switch of the signal line on which the switch is provided and the input terminal of the offset level control resistor. 7. The D / A converter circuit according to claim 6, further comprising a dummy switch in which the gate signal input to the MOS transistor has the opposite phase to the gate signal input to the MOS transistor of the switch having the same polarity. Formed in one integrated circuit,
2. The apparatus according to claim 1, wherein said first D / A converter includes an original reference voltage generating means for generating an original reference voltage for generating said first reference voltage and said second reference voltage. 8. The D / A converter circuit according to any one of claims 1 to 7. A portable terminal device comprising the D / A converter circuit according to claim 1. An audio device comprising the D / A converter circuit according to any one of claims 1 to 8.

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