WO2023182278A1

WO2023182278A1 - Da converting device, display driver, and display device

Info

Publication number: WO2023182278A1
Application number: PCT/JP2023/010904
Authority: WO
Inventors: 宏嘉一倉; 剛野坂
Original assignee: ラピステクノロジー株式会社
Priority date: 2022-03-25
Filing date: 2023-03-20
Publication date: 2023-09-28

Abstract

A DA converting device according to the present invention includes: a pre-stage DAC which outputs, as first and second selected voltages, a maximum voltage and a minimum voltage of one divided range corresponding to a higher-order bit group in a data signal, from among a plurality of divided ranges obtained by dividing a voltage range from a reference voltage to a prescribed voltage higher than the reference voltage; a level shifter for generating a shifted lower-order bit signal group obtained by level-shifting binary signal levels representing each bit in a lower-order bit group in the data signal respectively to the first and second selected voltages output from the pre-stage DAC; and a post-stage DAC which, on the basis of the first and second selected voltages output from the pre-stage DAC, outputs as an output voltage a voltage which is between the first selected voltage and the second selected voltage and which has a voltage value corresponding to the shifted lower-order bit signal group.

Description

DA converter, display driver and display device

The present invention relates to a DA conversion device, a display driver that drives a display panel according to a video signal, and a display device.

Active matrix display devices such as liquid crystal display devices or organic EL display devices include a display panel in which multiple data lines and multiple scanning lines are wired in an intersecting manner, and the display panel is driven based on video signals. A display driver is included.

The display driver converts gradation data representing the brightness indicated by the video signal as a low-voltage digital value into an analog high-voltage signal that can drive the display panel, amplifies this signal, and sends it to the display panel. A digital-to-analog conversion circuit (hereinafter referred to as DAC) for output is included.

As such a DAC, one having the following level converter, first and second DA converters, and amplifier is known (see, for example, Patent Document 1).

In the DAC described in Patent Document 1, first, the signal level of low-voltage gradation data is increased to a voltage that can drive the display panel using a level converter. Next, the first DA converter compatible with high voltage selects two reference voltages corresponding to the values of the upper bit group of the high-voltage gradation data signal from among the plurality of reference voltages having different voltage values. Select and output. The second DA converter compatible with high voltage includes a plurality of switch elements that are on/off controlled based on the value of the lower bit group of the gradation data signal, and a plurality of switch elements that are controlled to turn on and off based on the value of the lower bit group of the gradation data signal. It includes a plurality of capacitors whose charging and discharging are controlled by one or both of two reference voltages. With this configuration, the second DA converter supplies the amplifier with one of the two reference voltages supplied from the first DA converter, or a voltage that is a combination of both. The amplifier outputs a signal obtained by amplifying the voltage supplied from the second DA converter.

Japanese Patent Application Publication No. 2011-239378

However, in the DAC described in Patent Document 1 mentioned above, since the first and second DA converters are compatible with high voltages, the elements constituting these first and second DA converters, especially transistors, are capable of high voltages. It is necessary to use the following. This causes a problem in that the scale of the DAC increases, and the size of the IC chip on which the display driver is constructed increases accordingly.

Further, in the DAC described in Patent Document 1, the switching element (transistor) that controls charging and discharging of the capacitor is also compatible with high voltage, so switching noise is larger than that of a switching element compatible with low voltage. This causes variations in the amount of charge held in the capacitor, leading to a decrease in DA conversion accuracy, and as a result, a problem arises in that the displayed image deteriorates.

Therefore, the present invention provides a DA conversion device that can improve the accuracy of DA conversion and reduce the size, and a display driver and display device that can improve the quality of display images and reduce the size. The purpose is to provide.

The DA conversion device according to the present invention is a digital-to-analog conversion circuit that converts a digital data signal consisting of a plurality of bits from a reference voltage to an output voltage having an analog voltage value within a voltage range of a predetermined voltage higher than the reference voltage. a pre-stage DAC that outputs a maximum voltage and a minimum voltage of one division range corresponding to a group of upper bits in the data signal as first and second selection voltages among a plurality of division ranges obtained by dividing the voltage range; , a shifted lower bit in which a binary signal level representing each bit of a lower bit group other than the upper bit group in the data signal is level-shifted to the first and second selection voltages output from the previous stage DAC, respectively; A voltage between the first selection voltage and the second selection voltage, based on the level shifter that generates the signal group and the first and second selection voltages output from the previous stage DAC, and the lower shift voltage. The second stage DAC generates a voltage having a voltage value corresponding to a bit signal group and outputs the generated voltage as the output voltage.

The display driver according to the present invention sends n (n is an integer of 2 or more) display data signals representing the brightness level of each pixel using a plurality of bits, each within a voltage range from a reference voltage to a predetermined voltage higher than the reference voltage. A data driver including first to n-th DA conversion circuits that convert into n drive signals having analog voltage values and supply the signals to n data lines of a display panel, the first to n-th DA conversion circuits Each of the DA conversion circuits sets the maximum voltage and the minimum voltage of one division range corresponding to the upper bit group in the data signal as first and second selection voltages, among a plurality of division ranges obtained by dividing the voltage range. and a binary signal level representing each bit of a lower bit group other than the upper bit group in the data signal to the first and second selection voltages output from the previous stage DAC, respectively. a level shifter that generates a level-shifted shifted lower bit signal group; and a level shifter that generates a level-shifted shifted lower bit signal group; a second-stage DAC that generates a voltage having a voltage value corresponding to the shift lower bit signal group and outputs the generated voltage as an output voltage; and an amplifier that outputs a signal obtained by amplifying the output voltage as the drive signal. ,including.

Further, the display device according to the present invention includes a display panel including n data lines each having a plurality of pixels (n is an integer of 2 or more), and a display panel including n data lines each having a plurality of pixels formed therein, and n data lines representing the brightness level of each pixel using a plurality of bits. (n is an integer of 2 or more) display data signals are converted into n drive signals each having an analog voltage value within a voltage range from a reference voltage to a predetermined voltage higher than the reference voltage, and the display panel The display device includes first to n-th DA conversion circuits that supply data to the n data lines, each of the first to n-th DA conversion circuits having a plurality of divisions into which the voltage range is divided. a pre-stage DAC that outputs the maximum voltage and minimum voltage of one divided range corresponding to the upper bit group in the data signal as first and second selection voltages; a level shifter that generates a shifted lower bit signal group in which a binary signal level representing each bit of the lower bit group is level-shifted to the first and second selection voltages output from the previous stage DAC; and the previous stage DAC; a voltage that is between the first selection voltage and the second selection voltage and has a voltage value corresponding to the shifted lower bit signal group, based on the first and second selection voltages output from and an amplifier that outputs a signal obtained by amplifying the output voltage as the drive signal.

The DA converter according to the present invention converts a digital data signal into an output voltage having an analog voltage value higher than the signal level of the data signal using the following front-stage DAC (digital analog converter), level shifter, and rear-stage DAC. Convert.

The front-stage DAC calculates the lowest voltage and highest voltage of the divided range corresponding to the upper bit group in the digital data signal among the divided ranges in which the range from a reference voltage based on a high voltage power supply to a predetermined voltage higher than the reference voltage is divided into a plurality of divided ranges. are output as the first and second selection voltages, respectively. The level shifter generates a shifted lower bit signal group by level-shifting the binary signal level representing each bit of the lower bit group in the data signal to the first and second selection voltages output from the previous stage DAC, respectively. The latter-stage DAC generates a voltage having a voltage value corresponding to the shifted lower bit signal group from the first and second selection voltages output from the former-stage DAC, and outputs the generated voltage as the output voltage.

According to such a configuration, it is possible to use circuit elements such as transistors constituting the latter-stage DAC that have a lower breakdown voltage (first selection voltage - second selection voltage) than the voltage from the high-voltage power supply.

Therefore, according to the DA converter including this latter-stage DAC, the size of the device when converted into a semiconductor IC chip can be reduced. Furthermore, since the withstand voltage of the plurality of transistors that are circuit elements constituting the subsequent stage DAC can be lowered, switching noise is reduced and DA conversion accuracy is increased.

Furthermore, by employing the DA conversion device according to the present invention including the above-mentioned post-stage DAC as the DA conversion circuit included in the display driver (data driver), it is possible to improve the quality and reduce the size of the displayed image. becomes possible.

FIG. 1 is a block diagram showing the configuration of a display device including a display driver according to the present invention. FIG. 2 is a block diagram showing the internal configuration of a data driver 130 as a display driver according to the present invention. FIG. 1 is a block diagram showing an example of the configuration of a DA conversion circuit according to the present invention. FIG. 3 is a diagram for explaining the operation of the front-stage DAC 32. FIG. 3 is a diagram illustrating an example of conversion processing results of the front-stage DAC 32 and the rear-stage DAC 34. FIG. 7 is a diagram showing another example of the conversion processing results of the front-stage DAC 32 and the rear-stage DAC 34. FIG. 7 is a diagram showing still another example of the conversion processing results of the front-stage DAC 32 and the rear-stage DAC 34. FIG. FIG. 3 is a block diagram showing another example of the configuration of the DA conversion circuit according to the present invention.

FIG. 1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention.

As shown in FIG. 1, the display device 100 includes a display controller 10, a scan driver 110, a data driver 130 as a display driver, and a display panel 200.

The display panel 200 is made of, for example, a liquid crystal or organic EL panel, and has m scanning lines SL1 to SLm (m is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and scanning lines SL1 to SLm extending in the vertical direction of the two-dimensional screen. n data lines DL1 to DLn (n is a natural number of 2 or more). A display cell PC serving as a pixel is formed at each intersection of the scanning line and the data line.

The display controller 10 receives the video signal VD and supplies the scan driver 110 with a scan timing signal for generating a horizontal scan pulse to be supplied to each scan line according to the video signal VD.

Further, the display controller 10 generates various control signals (clock signal, synchronization signal, data acquisition signal, polarity inversion signal, etc.) and a display data piece representing the brightness level of each pixel in 12 bits, for example, based on the video signal VD. A video digital signal DVS including a sequence of is generated. Note that the video digital signal DVS is a signal representing a signal level corresponding to binary logic levels 0 and 1 by a logic power supply VDD for driving a logic circuit. The display controller 10 supplies the video digital signal DVS to the data driver 130.

The scan driver 110 sequentially applies a horizontal scan pulse synchronized with the scan timing signal supplied from the display controller 10 to each of the scan lines SL1 to SLm of the display panel 200.

In response to the video digital signal DVS, the data driver 130 first takes in a series of display data pieces corresponding to each pixel included in the video digital signal DVS by the number of data lines, that is, n pieces. Next, the data driver 130 converts each of the n captured display data pieces into a drive signal having an analog voltage value corresponding to the brightness level indicated by the display data piece.

The drive signal is an analog voltage that is generated based on the high voltage power supply VDDH for driving the display panel 200 and changes each brightness level within the range from the lowest brightness to the highest brightness that can be expressed by the display panel 200 in stages. It is a signal expressed as a value.

The data driver 130 supplies the n drive signals generated as described above, each corresponding to the n display data pieces, to the data lines DL1 to DLn of the display panel 200 as drive signals G1 to Gn.

FIG. 2 is a block diagram schematically showing the internal configuration of the data driver 130.

As shown in FIG. 2, the data driver 130 includes a latch circuit 131 and a DA (digital to analog) converter 132.

The latch circuit 131 captures n series of display data pieces included in the video digital signal DVS supplied from the display controller 10, and supplies them to the DA converter 132 as display data signals P1 to Pn, respectively. Note that each of the display data signals P1 to Pn is, for example, a 12-bit signal, as described above. At this time, each bit is a binary signal representing logic levels 0 and 1 depending on the reference voltage VSS and the low voltage LV.

The DA converter 132 individually converts each of the display data signals P1 to Pn into an analog voltage value within the range of a predetermined high voltage HV from the reference voltage VSS, corresponding to the brightness level indicated by the display data signal. . Note that the high voltage HV is a DC voltage based on the high voltage power supply VDDH or a voltage slightly lower than the voltage.

Then, the DA converter 132 outputs drive signals G1 to Gn, each of which has the n analog voltage values obtained by the conversion.

As shown in FIG. 2, the DA conversion unit 132 includes a reference voltage generation circuit VG and DA conversion circuits DC1 to DCn provided corresponding to display data signals P1 to Pn, respectively.

The reference voltage generation circuit VG generates, for example, nine reference voltages GS1 to GS9 having different voltage values from each other based on the high voltage power supply VDDH. Reference voltage generation circuit VG supplies reference voltages GS1 to GS9 to DA conversion circuits DC1 to DCn.

Each of the DA conversion circuits DC1 to DCn receives reference voltages GS1 to GS9, and also receives one of the display data signals P1 to Pn supplied from the latch circuit 131, which corresponds to the one corresponding to the DA conversion circuit DC1 to DCn. That is, for example, the DA conversion circuit DC1 receives the display data signal P1, the DA conversion circuit DC2 receives the display data signal P2, and the DA conversion circuit DCn receives the display data signal Pn.

Each of the DA conversion circuits DC1 to DCn converts the display data signal received as a digital data signal into an analog voltage value corresponding to the brightness level indicated by the display data signal, based on the reference voltages GS1 to GS9. do. Each of the DA conversion circuits DC1 to DCn outputs the amplified analog voltage value as a drive signal. That is, the DA conversion circuits DC1 to DCn output the drive signals generated by each of them as drive signals G1 to Gn. Note that each of the DA conversion circuits DC1 to DCn has the same internal configuration.

FIG. 3 is a circuit diagram showing an example of the internal configuration of the DA conversion circuit according to the present invention, with DC1 extracted from the DA conversion circuits DC1 to DCn.

As shown in FIG. 3, the DA conversion circuit DC1 includes

level shifters

31 and 33, a DA converter 32 (hereinafter referred to as a front-stage DAC 32), a DA converter 34 (hereinafter referred to as a rear-stage DAC 34), and an amplifier 35.

The level shifter 31 receives the high-voltage power supply VDDH and, for example, a group of upper bits [11:9] consisting of the upper 3 bits of the 12-bit display data signal P1 [11:0]. The level shifter 31 converts the amplitude of the binary (logic level 0, 1) signal level (LV, VSS) representing each bit of the upper bit group [11:9] into a high voltage HV based on the high voltage power supply VDDH and a reference level. The level is shifted to the amplitude based on the voltage VSS.

The level shifter 31 level-shifts the signal level of each of the upper three bits of the display data signal P1 as described above and supplies it to the preceding stage DAC 32 as the upper bit signal group MS.

The front-stage DAC 32 receives the high-voltage power supply VDDH, the upper bit signal group MS, and the reference voltages GS1 to GS9. Note that the reference voltages GS1 to GS9 are obtained by dividing the voltage range provided by the high voltage power supply VDDH by the number of all bit patterns [000] to [111] that can be expressed by the upper bit signal group MS, as shown in FIG. These are the highest and lowest voltages in each divided range when Here, the total number of bit patterns in the upper bit signal group MS is eight. As a result, as shown in FIG. 4, the range of the high voltage power supply VDDH is divided into eight divided ranges DV1 to DV8, and each divided range is associated with a bit pattern [000] to [111] corresponding to that divided range. be done.

The front-stage DAC 32 converts the upper bit signal group MS as digital data into two systems of analog voltages as described below, and outputs them as selection voltages Va and Vb, respectively.

That is, the front-stage DAC 32 selects a division range corresponding to the bit pattern represented by the upper bit signal group MS from among the division ranges DV1 to DV8, and selects the highest voltage and lowest voltage of the selected division range, respectively. Output as voltages Va and Vb.

For example, when the bit pattern represented by the upper bit signal group MS is [010], the pre-stage DAC 32 uses the reference voltage that is the highest voltage in the division range DV3 corresponding to the bit pattern [010] as shown in FIG. The voltage GS4 is outputted as a selection voltage Va, and the reference voltage GS3, which is the lowest voltage, is outputted as a selection voltage Vb.

The level shifter 33 receives the lower bit group [8:0] consisting of the lower 9 bits of the 12-bit display data signal P1 [11:0] together with the selection voltages Va and Vb output from the previous stage DAC 32. The level shifter 33 levels-shifts each binary (logic level 0, 1) signal level (LV, VSS) representing each bit of the lower bit group [8:0] to selection voltages Va and Vb, respectively. The level shifter 33 supplies a 9-bit signal obtained by level-shifting the signal level of each bit of the lower bit group [8:0] to the subsequent stage DAC 34 as a shifted lower bit signal group LS.

The latter stage DAC 34 receives the shift lower bit signal group LS together with the selection voltages Va and Vb outputted from the former stage DAC 32.

The latter-stage DAC 34 is a so-called ladder resistance type DAC that is composed of a ladder resistance LDR and a selector SEL.

The ladder resistor LDR is a voltage divided by the voltage between the selection voltages Va and Vb by the number (512) of all bit patterns [000000000] to [111111111] that can be expressed by the 9-bit shift lower bit signal group LS. It generates piezoelectric voltages VP1 to VP512. It is assumed that among the divided voltages VP1 to VP512, VP512 has the maximum voltage value, and VP1 has the minimum voltage value.

The selector SEL selects only one divided voltage from among the divided voltages VP1 to VP512 based on the shifted lower bit signal group LS, and supplies this as the output voltage V0 to the amplifier 35 via the line L0.

Selector SEL includes switch elements Q1 to Q512 and a decoder DEC.

Switch elements Q1 to Q512 individually receive divided voltages VP1 to VP512 at one end of each. The other ends of each of the switching elements Q1 to Q512 are commonly connected to the line L0.

The decoder DEC individually performs on/off control for the switching elements Q1 to Q512 to set one of the switching elements Q1 to Q512 in an on state and all other switch groups to be in an off state based on the shifted lower bit signal group LS. give to

For example, when the shift lower bit signal group LS is a bit pattern [000000000] indicating the lowest value, the decoder DEC turns on only Q1 of the switch elements Q1 to Q512 and turns on the other switch elements Q2 to Q512. All controls are turned off. Thereby, the selector SEL selects the divided voltage VP1 from among the divided voltages VP1 to VP512, and outputs the divided voltage VP1 as the output voltage V0 via the line L0. Further, when the shifted lower bit signal group LS is a bit pattern [111111111] showing the highest value, the decoder DEC turns on only Q512 of the switching elements Q1 to Q512 and turns on the other switching elements Q1 to Q511. All controls are turned off. Thereby, the selector SEL selects the divided voltage VP512 from among the divided voltages VP1 to VP512, and outputs the divided voltage VP512 as the output voltage V0 via the line L0.

The amplifier 35 is a voltage follower operational amplifier whose output terminal is connected to its inverting input terminal. The amplifier 35 receives the output voltage V0 output from the selector SEL at its own non-inverting input terminal via the line L0, and outputs a signal obtained by amplifying the output voltage V0 from its own output terminal as a drive signal G1.

The bit pattern of the display data signal P1 is shown below.
First state: [111111001101]
Second state: [111000110011]
Third state: [000000110011]
Taking as an example the case where the state changes to , the operations of the front-stage DAC 32 and the rear-stage DAC 34 in each state will be described with reference to FIGS. 5A to 5C.

Note that each of the reference voltages GS1 to GS9 is a voltage at each boundary when the range of 0.5 volts to 8.5 volts is divided into 1 volt units as shown below.

GS1: 0.5 volts GS2: 1.5 volts GS3: 2.5 volts GS4: 3.5 volts GS5: 4.5 volts GS6: 5.5 volts GS7: 6.5 volts GS8: 7.5 volts GS9: 8.5 volts First, according to the bit pattern [111111001101] in the first state, as shown in FIG. 5A, [111] is supplied to the previous stage DAC 32 as the upper bit signal group MS, and [111] is supplied as the shifted lower bit signal group LS. 111001101] is supplied to the subsequent DAC 34.

As a result, the previous stage DAC 32 selects a selection voltage Va of 8.5 volts as GS9, which is the highest voltage of the division range DV8, and GS8, which is the lowest voltage of the division range DV8, in accordance with the upper bit signal group MS[111]. A selection voltage Vb of 7.5 volts is supplied to the subsequent stage DAC 34.

On the other hand, the rear DAC 34 is
7.5+(8.5-7.5)×[111001101]/[111111111]
The voltage of 8.4 volts determined by is outputted as the output voltage V0.

Next, the bit pattern of the display data signal P1 transitions from the first state to the second state bit pattern [111000110011]. In this case, as shown in FIG. 5B, [111] of the upper bit signal group MS is continuously supplied to the preceding stage DAC 32, and [000110011] is supplied to the latter stage DAC 34 as the shifted lower bit signal group LS.

As a result, the front-stage DAC 32 continues to output the selection voltage Va of 8.5 volts as GS9, which is the highest voltage of the division range DV8, and the selection voltage Vb of 7.5 volts, as GS8, which is the lowest voltage of the division range DV8, to the rear stage. Supplied to DAC34.

On the other hand, the rear DAC 34 is
7.5+(8.5-7.5)×[000110011]/[111111111]
The voltage of 7.6 volts determined by is outputted as the output voltage V0.

Next, the bit pattern of the display data signal P1 transitions from the second state to the third state bit pattern [000000110011]. In this case, as shown in FIG. 5C, [000] of the upper bit signal group MS is supplied to the preceding stage DAC 32, and [000110011] is subsequently supplied to the latter stage DAC 34 as the shifted lower bit signal group LS.

As a result, the front-stage DAC 32 selects a selection voltage Va of 1.5 volts as GS2, which is the highest voltage of the division range DV1, and GS1, which is the lowest voltage of the division range DV1, according to the upper bit signal group MS[000]. A selection voltage Vb of 0.5 volts is supplied to the subsequent stage DAC 34.

On the other hand, the rear DAC 34 is
0.5+(1.5-0.5)×[000110011]/[111111111]
The voltage of 0.6 volts determined by is outputted as the output voltage V0.

Therefore, as shown in FIGS. 5A to 5C, by amplifying the output voltage V0 output from the subsequent stage DAC 34 with the amplifier 35, the DA conversion circuit DC1 outputs the drive signal G1 having the output voltage V0.

In this way, the DA conversion circuit DC1 shown in FIG. 3 converts the 12-bit data signal (P1) as digital data into an analog voltage value of a high voltage (VDDH) higher than the signal level (VDD) of the data signal. It is converted into an output voltage V0 having a value of V0.

By the way, in the configuration shown in FIG. 3, the pre-stage DAC 32 handles the high voltage signal between the reference voltage VSS and the high voltage HV as a processing target, so the high voltage signal that is at least the voltage between the reference voltage VSS and the high voltage HV is processed. A voltage power supply VDDH is used. Therefore, as each circuit element such as a transistor constituting the front-stage DAC 32, one having a high breakdown voltage compatible with the high voltage power supply VDDH is used.

On the other hand, the second-stage DAC 34 uses a selected voltage Va which is the highest voltage of each of the divided ranges DV1 to DV8 obtained by dividing the voltage between the reference voltage VSS and the high voltage HV by the high voltage power supply VDDH into eight divided ranges as shown in FIG. and the selection voltage Vb, which is the lowest voltage, is treated as a processing target. Therefore, in the latter stage DAC 34, the voltage between the selection voltages Va and Vb is set using a bit signal (LS) in which the binary signal level of each of the lower 8 bits of the display data signal P1 is level-shifted to the selection voltages Va and Vb, respectively. The selector SEL is controlled to select one of the divided voltages VP1 to VP512.

As a result, the circuit elements constituting the subsequent stage DAC 34, for example, the switch elements S1 to S512 included in the selector SEL, the transistors constituting the decoder DEC, etc., have a withstand voltage (Va-Vb), that is, approximately 1 of the high voltage power supply VDDH (HV). It becomes possible to use one with a breakdown voltage of /8.

Therefore, according to the latter-stage DAC 34, it is possible to reduce the size when it is made into a semiconductor IC chip, compared to the case of using one that operates on the high-voltage power supply VDDH. Furthermore, in the latter-stage DAC 34, the transistors used have lower breakdown voltages, which reduces switching noise and improves DA conversion accuracy.

Therefore, according to the DA conversion circuit according to the present invention including the latter-stage DAC 34, it is possible to improve the DA conversion accuracy and reduce the size.

Furthermore, by employing a DA conversion circuit including the rear-stage DAC 34 as the DA conversion circuit included in the display driver (data driver), it is possible to improve the quality and reduce the size of the displayed image.

Note that in the DA conversion circuit DC1 shown in FIG. 3, a ladder resistance type DAC is used as the subsequent stage DAC 34, but a capacitance type DAC may be used.

FIG. 6 is a circuit diagram showing another example of the internal configuration of the DA conversion circuit DC1, which was created in view of this point.

Note that the DA conversion circuit DC1 shown in FIG. 6 has a different configuration (31 , 32, 35) are the same as shown in FIG.

The latter-stage DAC 44 includes

voltage protection circuits

11 and 12, a sample circuit 13, a hold circuit 14, and an output circuit 15.

The breakdown voltage protection circuit 11 includes

switch elements

11a and 11b that protect the sample circuit 13 from a voltage higher than the voltage difference (Va-Vb) between the selection voltage Va and the selection voltage Vb.

When in the on state, the switch element 11a supplies the selection voltage Va output from the previous stage DAC 32 to the sample circuit 13 via the line La. On the other hand, in the off state, the switch element 11a prevents a voltage higher than the voltage (Va-Vb) from being applied to the sample circuit 13 via the line La by cutting off the connection between the pre-stage DAC 32 and the line La. do.

When in the on state, the switch element 11b supplies the selection voltage Vb output from the previous stage DAC 32 to the sample circuit 13 via the line Lb. On the other hand, in the off state, the switch element 11b cuts off the connection between the pre-stage DAC 32 and the line Lb, thereby avoiding a state in which a voltage higher than the voltage (Va-Vb) is applied to the sample circuit 13 via the line Lb. do.

The level shifter 43 includes a parallel-to-serial conversion circuit 43a (hereinafter referred to as a PS conversion circuit 43a), a first level shifter 43b, and a second level shifter 43c.

The PS conversion circuit 43a receives the lower bit group [8:0] consisting of the lower 9 bits of the 12-bit display data signal P1 [11:0]. The PS conversion circuit 43a converts the lower bit group [8:0] in the 9-bit parallel format into a bit series in the 1-bit serial format, and supplies a serial bit signal SD representing the bit series to the first level shifter 43b.

The first level shifter 43b receives selection voltages Va and Vb via the withstand voltage protection circuit 11 and lines La and Lb, along with the serial bit signal SD representing the lower bit group [8:0]. The first level shifter 43b converts each binary signal level (LV, VSS) of each bit (logic level 0, 1) of the 9-bit series represented by the serial bit signal SD to selection voltages Va and Vb, respectively. Shift levels. The first level shifter 43b supplies a serial bit signal representing the level-shifted shifted lower bit signal group to the second level shifter 43c and the sample circuit 13 of the subsequent stage DAC 44 as a serial bit signal SSD.

Note that the first level shifter 43b cannot receive the selection voltages Va and Vb while the breakdown voltage protection circuit 11 cuts off the connection between the preceding stage DAC 32 and the line La (Lb), so in this case, The level shift operation described above and the output of the serial bit signal SSD are stopped.

The second level shifter 43c receives selection voltages Va and Vb via lines La and Lb along with the serial bit signal SSD. The second level shifter 43c converts each binary signal level (LV, VSS) of each bit (logic level 0, 1) of a 9-bit series in a 1-bit serial format represented by the serial bit signal SSD to a selected voltage. Level shift to Va and Vb. The second level shifter 43c supplies a serial bit signal representing the level-shifted shifted lower bit signal group to the hold circuit 14 of the subsequent stage DAC 44 as a serial bit signal SSDa.

The sample circuit 13 of the latter stage DAC 44 includes

switch elements

13a, 13b and a capacitor 13c.

The

switch elements

13a and 13b are turned on or off in a complementary manner for each bit of the serial bit signal SSD consisting of a bit sequence of the lower 9 bits of the display data signal P1, depending on the logic level of that bit signal. For example, when each bit in the serial bit signal SSD indicates a logic level 0, the switch element 13a is turned off and the switch element 13b is turned on, and when each bit indicates a logic level 1, the switch element 13a is turned on and the switch element 13b is turned on. is in the off state. When the switch element 13a is turned on, the selection voltage Va received via the line La, that is, the divided range (DV1 to DV8) corresponding to the value of the upper 3 bits (MS) of the display data signal P1. Apply the highest voltage to line Lc. On the other hand, when the switch element 13b is turned on, the selection voltage Vb received via the line Lb, that is, the division range (DV1 to DV8) corresponding to the value of the upper 3 bits (MS) of the display data signal P1. ) is applied to line Lc.

The capacitor 13c has one end connected to the line Lc, and is charged according to the selection voltage Va or Vb supplied via the

switch element

13a or 13b. As a result, an amount of charge corresponding to the value represented by the lower 9 bits of the display data signal P1 between the selection voltages Va and Vb is accumulated in the capacitor 13c. As a result, a voltage Vj corresponding to the amount of charge, that is, a voltage Vj having a voltage value corresponding to the value represented by the lower 9 bits of the display data signal P1 between the selection voltages Va and Vb is generated on the line Lc. Ru.

The breakdown voltage protection circuit 12 includes a switch element 12a that protects the sample circuit 13 from a voltage higher than the above voltage (Va-Vb).

When in the on state, the switch element 12a supplies the voltage Vj output from the sample circuit 13 to the hold circuit 14 via the line Ld. On the other hand, in the off state, the switch element 12a cuts off the connection between the sample circuit 13 and the line Ld, so that a voltage higher than the voltage (Va-Vb) accumulated in the hold circuit 14 is passed to the sample circuit via the line Ld. 13 is avoided.

The hold circuit 14 includes a switch element 14a and a capacitor 14b.

The switch element 14a is turned on or off by the serial bit signal SSDa output from the level shifter 43c at a timing opposite to the timing at which the

switch elements

13a and 13b are turned on according to the serial bit signal SSD output from the level shifter 43b. state. For example, when each bit in the serial bit signal SSDa indicates a logic level 0, it becomes an OFF state, and when it indicates a logic level 1, it becomes an ON state. When the switch element 14a is turned on, it applies the voltage Vj received via the line Ld to the line Le.

The capacitor 14b has one end connected to the line Le, and is charged by the voltage Vj applied to the line Le via the switch element 14a. As a result, an amount of charge corresponding to the value of the lower 9 bits of the display data signal P1 between the selection voltages Va and Vb is accumulated in the capacitor 14b.

As a result, the capacitor 14b has the lowest voltage (Vb) and the highest voltage in the divided range corresponding to the upper three bits (MS) of the display data signal P1, that is, one of the divided ranges DV1 to DV8 shown in FIG. A voltage VQ between voltages (Va) and having a voltage value corresponding to the lower 9 bits (LS) of the display data signal P1 is held. At this time, voltage VQ held in capacitor 14b is supplied to output circuit 15 via line Le.

The output circuit 15 includes a switch element 15a that connects the line Le and the line L0 when in the on state, and cuts off the connection between the line Le and the line L0 when in the off state. That is, when the switch element 15a is in the on state, the voltage VQ held in the capacitor 14b of the hold circuit 14 is supplied to the amplifier 35 via the line L0.

The operation of the DA conversion circuit DC1 shown in FIG. 6 will be explained below.

First, the front-stage DAC 32 selects the lowest voltage of the division range (one of DV1 to DV8) corresponding to the bit pattern represented by the upper three bits [11:9] of the display data signal P1, the selected voltage Vb, and the highest voltage. is output as the selection voltage Va.

Next, the

switch elements

11a and 11b of the voltage protection circuit 11 are turned on.

Next, by turning on both the switch element 13b of the sample circuit 13 and the switch element 14a of the hold circuit 14, the capacitor 14b of the hold circuit 14 is reset to the state where the selection voltage Vb is held.

Next, the

switch elements

13a, 13b of the sample circuit 13 and the switch element 14a of the hold circuit 14 repeat on and off according to the logic level of each bit of the series of lower 9 bits [8:0] of the display data signal P1. As a result, the voltage VQ corresponding to the luminance level represented by the 12-bit display data signal P1[11:0] is held in the capacitor 14b of the hold circuit 14. For example, first, the switch element 13a is turned on, and the potential of Va is held at Vj. Next, the switch element 13a is turned off and the switch element 14a is turned on, so that the potential of Vj (=Va) and the potential of Le (=Vb) are averaged, and Vj=Ld=Le=(Va+Vb)/ The potential becomes 2. The switch element 14b is turned off, and the switch element 13b is then turned on, so that the potential of Vb is held at Vj. Next, the switch element 13b is turned off and the switch element 14a is turned on, so that the potential of Vj (=Vb) and the potential of Le{=(Va+Vb)/2} are averaged, and Vj=Ld=Le= The potential becomes {(Va+Vb)/2+Vb}/2=(Va+Vb)/4. By repeating this operation as many times as the lower 9 bits [8:0] of the display data signal P1, the holding voltage of Le changes to a desired potential between Va and Vb.

Then, when the switch element 15a of the output circuit 15 is turned on, the amplifier 35 outputs the drive signal G1 having the voltage VQ corresponding to the brightness level represented by the display data signal P1[11:0]. .

By the way, in the capacitive DA converter circuit shown in FIG. 6, the subsequent stage DAC 44 selects the highest voltage in the division range obtained by dividing the voltage between the reference voltage VSS and the high voltage HV by the high voltage power supply VDDH into eight as shown in FIG. The voltage between the voltage Va and the selection voltage Vb, which is the lowest voltage, is treated as a processing target. Therefore, the subsequent DAC 44 sets the selection voltage to the sample circuit 13 and the hold circuit 14 based on the bit signals (SSD, SSDa) obtained by level-shifting the binary signal level of the display data signal P1 to the selection voltages Va and Vb, respectively. The charging and discharging of the capacitors (13c, 14b) is controlled by Va and Vb.

As a result, as transistors forming the circuit elements forming the latter-stage DAC 44 shown in FIG. In other words, it is possible to use a device with a withstand voltage of about 1/8 of the high voltage power supply VDDH (HV).

Therefore, according to the latter-stage DAC 44, it is possible to reduce the size when it is made into a semiconductor IC chip, compared to the case of using one that operates on the high-voltage power supply VDDH. Furthermore, in the latter-stage DAC 44, the switching noise is reduced because the withstand voltage of the transistor used is lowered, and the DA conversion accuracy is increased.

Therefore, in the DA conversion circuit shown in FIG. 6 including the subsequent stage DAC 44, it is possible to improve the DA conversion accuracy and reduce the size, similarly to the circuit shown in FIG.

In addition, by adopting a capacitive DA conversion circuit including a subsequent stage DAC 44 as the DA conversion circuit included in the display driver (data driver), it is possible to improve the quality and reduce the size of the displayed image. becomes.

Furthermore, in the above embodiment, a configuration was explained in which a ladder resistance type and a capacitance type were adopted as the DA conversion method of the rear-stage DAC, but the DA conversion method of the rear-stage DAC was limited to the ladder resistance type and the capacitance type. Alternatively, for example, an inverting amplifier may be used.

In the above embodiment, the configuration of the DA conversion circuit shown in FIG. 3 or 6 was explained by taking as an example the DA conversion circuit included in the data driver 130 that drives the display panel. The present invention may also be applied to a DA conversion circuit.

In short, the DA conversion circuit according to the present invention that converts a data signal into an output voltage (V0) having an analog voltage value within a voltage range of a predetermined voltage (HV) from a reference voltage (VSS) includes the following pre-stage DAC. , a level shifter, and a post-stage DAC.

The front-stage DAC (32) divides one of the divided ranges (DV1 to DV8) into which the voltage range from the reference voltage to the predetermined voltage (HV) is divided, corresponding to the upper bit group (MS) in the data signal. The maximum voltage and minimum voltage are output as first and second selection voltages (Va, Vb). The level shifters (33, 43) convert the binary signal levels representing each bit of the lower bit group other than the upper bit group (MS) in the data signal to the first and second signals output from the previous stage DAC (32), respectively. A shifted lower bit signal group (LS, SSD, SSDa) whose level is shifted to the selection voltage (Va, Vb) is generated. The second stage DAC (34, 44) has a voltage between the first selection voltage (Va) and the second selection voltage (Vb) based on the first and second selection voltages output from the previous stage DAC. , and a voltage having a voltage value corresponding to the shifted lower bit signal group (LS, SSD, SSDa), and outputs this as an output voltage (V0).

31, 33 Level shifter 32 Front stage DAC
34 Second stage DAC
100 Display device 130 Data driver 132 DA converter 200 Display panel DC1-DCn DA converter circuit

Claims

A digital-to-analog conversion circuit that converts a digital data signal consisting of a plurality of bits from a reference voltage to an output voltage having an analog voltage value within a voltage range of a predetermined voltage higher than the reference voltage,
a pre-stage DAC that outputs a maximum voltage and a minimum voltage of one division range corresponding to a group of upper bits in the data signal as first and second selection voltages among a plurality of division ranges obtained by dividing the voltage range;
a shifted lower bit signal in which a binary signal level representing each bit of a lower bit group other than the upper bit group in the data signal is level-shifted to the first and second selection voltages output from the previous stage DAC, respectively; a level shifter that generates a group;
A voltage value corresponding to the shift lower bit signal group, which is a voltage between the first selection voltage and the second selection voltage, based on the first and second selection voltages output from the previous stage DAC. 1. A digital-to-analog conversion circuit comprising: a second-stage DAC that generates a voltage having a value of 1, and outputs the generated voltage as the output voltage.
The latter-stage DAC includes a ladder resistor that generates a plurality of divided voltages obtained by dividing a voltage between the first selection voltage and the second selection voltage output from the former-stage DAC;
Claim comprising: a selector that selects one divided voltage based on the shifted lower bit signal group from among the plurality of divided voltages and outputs the selected divided voltage as the output voltage. 1. The digital-to-analog conversion circuit according to 1.
The latter stage DAC is
a parallel-serial conversion circuit that converts the shifted lower bit signal group into a 1-bit serial serial bit signal;
a first capacitor, which selects one of the first selection voltage and the second selection voltage outputted from the previous-stage DAC in order according to the logic level of each bit in the serial bit signal; a sample circuit that applies voltage to the capacitor No. 1;
a second capacitor, the voltage of the first capacitor is applied to the second capacitor in order according to the logic level of each bit in the serial bit signal, so that the voltage of the first capacitor is applied to the second capacitor in response to the data signal; a hold circuit that holds a voltage having the analog voltage value;
The digital-to-analog conversion circuit according to claim 1, further comprising: an output circuit that outputs the voltage held in the second capacitor as an output voltage.
4. The digital-to-analog conversion circuit according to claim 1, further comprising a voltage generation section that generates the maximum voltage and the minimum voltage of each of the plurality of divided ranges and supplies the generated voltages to the pre-stage DAC. .
5. The digital-to-analog conversion circuit according to claim 1, wherein the latter-stage DAC includes a plurality of transistors, each of which has a withstand voltage greater than or equal to a voltage between a maximum voltage and a minimum voltage in the division range. .
n (n is an integer of 2 or more) display data signals representing the brightness level of each pixel in multiple bits, each having an analog voltage value within a voltage range from a reference voltage to a predetermined voltage higher than the reference voltage. A data driver including first to n-th DA conversion circuits that convert the driving signals into n data lines of a display panel and supply the converted signals to n data lines of a display panel,
Each of the first to n-th DA conversion circuits,
a pre-stage DAC that outputs a maximum voltage and a minimum voltage of one division range corresponding to a group of upper bits in the data signal as first and second selection voltages among a plurality of division ranges obtained by dividing the voltage range;
a shifted lower bit signal in which a binary signal level representing each bit of a lower bit group other than the upper bit group in the data signal is level-shifted to the first and second selection voltages output from the previous stage DAC, respectively; a level shifter that generates a group;
A voltage value corresponding to the shift lower bit signal group, which is a voltage between the first selection voltage and the second selection voltage, based on the first and second selection voltages output from the previous stage DAC. a latter-stage DAC that generates a voltage having a
A display driver comprising: an amplifier that outputs a signal obtained by amplifying the output voltage as the drive signal.
The latter-stage DAC includes a ladder resistor that generates a plurality of divided voltages obtained by dividing a voltage between the first selection voltage and the second selection voltage output from the former-stage DAC;
Claim comprising: a selector that selects one divided voltage based on the shifted lower bit signal group from among the plurality of divided voltages and outputs the selected divided voltage as the output voltage. 6. The display driver described in 6.
The latter stage DAC is
a parallel-serial conversion circuit that converts the shifted lower bit signal group into a 1-bit serial serial bit signal;
a first capacitor, which selects one of the first selection voltage and the second selection voltage outputted from the previous-stage DAC in order according to the logic level of each bit in the serial bit signal; a sample circuit that applies voltage to the capacitor No. 1;
a second capacitor, the voltage of the first capacitor is applied to the second capacitor in order according to the logic level of each bit in the serial bit signal, so that the voltage of the first capacitor is applied to the second capacitor in response to the data signal; a hold circuit that holds a voltage having the analog voltage value;
7. The display driver according to claim 6, further comprising: an output circuit that outputs the voltage held in the second capacitor as an output voltage.
The display driver according to any one of claims 6 to 8, further comprising a voltage generation unit that generates the maximum voltage and the minimum voltage of each of the plurality of divided ranges and supplies the generated voltages to the pre-stage DAC.
The display driver according to any one of claims 6 to 9, wherein the latter-stage DAC includes a plurality of transistors, each of which has a withstand voltage greater than or equal to a voltage between the maximum voltage and minimum voltage of the division range.
a display panel including n (n is an integer of 2 or more) data lines each having a plurality of pixels;
n (n is an integer of 2 or more) display data signals representing the brightness level of each pixel in multiple bits, each having an analog voltage value within a voltage range from a reference voltage to a predetermined voltage higher than the reference voltage. A display device comprising first to nth DA conversion circuits that convert the driving signals into n driving signals and supply the n data lines of the display panel,
Each of the first to n-th DA conversion circuits,
a pre-stage DAC that outputs a maximum voltage and a minimum voltage of one division range corresponding to a group of upper bits in the data signal as first and second selection voltages among a plurality of division ranges obtained by dividing the voltage range;
a shifted lower bit signal in which a binary signal level representing each bit of a lower bit group other than the upper bit group in the data signal is level-shifted to the first and second selection voltages output from the previous stage DAC, respectively; a level shifter that generates a group;
A voltage value corresponding to the shift lower bit signal group, which is a voltage between the first selection voltage and the second selection voltage, based on the first and second selection voltages output from the previous stage DAC. a latter-stage DAC that generates a voltage having a
A display device comprising: an amplifier that outputs a signal obtained by amplifying the output voltage as the drive signal.