KR20160028030A - Ditigal to analog converting device, data driver and display device using the same - Google Patents

Abstract

The present invention provides a digital to analog converting device for reducing the size of a data driving part, a data driver using the same, and a display device using the same. The digital to analog converting device includes a digital to analog converting part which converts a digital signal including a first digital signal and a second digital signal into an analog signal, a first digital analog converter which converts the first digital signal into a first voltage based on a reference gamma voltage, a voltage calculation part which receives the first voltage, a first and a second reference voltage and outputs them to a second voltage, and a second digital to analog converter which receives the first and the second voltage and outputs them into the second digital signal.

Description

TECHNICAL FIELD [0001] The present invention relates to a digital-to-analog converter, a data driver using the same, and a display using the same.

The present invention relates to a data driver and a display using the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display (EPD), and a plasma display panel (PDP) ) Have been increasingly used.

In recent years, in order to realize a high resolution of a display device, the size of the data driver has been increased, and it has been required to improve the manufacturing cost and the power consumption.

According to an aspect of the present invention, there is provided a digital-to-analog (D / A) converter for reducing a size of a data driver and reducing a production cost by reducing the number of components constituting a size and a digital- And a display device using the same.

The present invention also provides a digital-to-analog converter capable of reducing power consumption, a data driver using the same, and a display device using the same.

The present invention also provides a digital-to-analog converter capable of reducing the time for converting digital data into an analog signal and reducing the driving time of the data driver, a data driver using the same, and a display using the same.

According to an aspect of the present invention, there is provided a digital-to-analog converter comprising: a first digital-to-analog converter for converting a first digital signal into a first voltage in a digital signal including a first digital signal and a second digital signal based on a reference gamma voltage; A digital-to-analog converter including a voltage calculator for receiving the first voltage and the first and second reference voltages and outputting the second voltage, and a second digital-to-analog converter for receiving the first and second voltages and outputting the second digital signal as an analog signal, to provide.

In another aspect, the present invention includes a digital-analog converter for converting a digital signal into an analog signal and an output buffer for outputting an analog signal as an output signal. The digital-to-analog converter includes a first digital-to-analog converter for converting a first digital signal to a first voltage based on a reference gamma voltage, a first digital-to-analog converter for receiving a first voltage and first and second reference voltages, And a second digital-to-analog converter that receives the first and second voltages and outputs an analog signal to the second digital signal.

According to another aspect of the present invention, there is provided a display panel driving method comprising: driving a display panel and a display panel, converting a first digital signal to a first voltage based on a reference gamma voltage, receiving a first voltage and first and second reference voltages, A data driver for receiving the first and second voltages and outputting an analog signal to the second digital signal, and a timing controller for controlling the data driver.

The present invention has the effect of reducing the size of the data driver by reducing the size of the digital-analog converter.

The present invention has the effect of reducing the size of the data driver by reducing the number of components constituting the digital-to-analog converter.

In addition, the present invention has the effect of reducing the number of components constituting the digital-to-analog converter and reducing the power consumption of the data driver.

In addition, the present invention has the effect of reducing the number of components constituting the digital-to-analog converter and reducing the production cost of the data driver.

In addition, the present invention has the effect of reducing the time required to convert digital data of a digital-to-analog converter into an analog signal.

Further, the present invention has the effect of reducing the time for converting digital data into an analog signal, thereby reducing the driving time of the data driver.

1 is a schematic block diagram of an organic light emitting display according to an embodiment of the present invention.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a schematic configuration diagram of the data driver of FIG.
4 shows a part of the configuration of the data driver.
5 is a configuration diagram of a part of the configuration of the gamma voltage generator and the data driver and the output circuit.
FIG. 6 is a diagram illustrating a comparison between a part of a conventional data driver and a part of a data driver according to an embodiment of the present invention.
FIG. 7 is a diagram showing a configuration example of the voltage operation unit of FIG. 5 according to the first embodiment. FIG.
FIG. 8 is a driving example of the voltage calculating unit of FIG. 5 according to the first embodiment. FIG.
FIG. 9 is a configuration diagram of the voltage calculator of FIG. 5 according to the second embodiment. FIG.
10 is a driving example of the voltage calculator of FIG. 5 according to the second embodiment.
Fig. 11 is an output waveform (a) of the voltage operation unit according to the first embodiment shown in Fig. 7 and an output waveform (b) of the voltage operation unit according to the second embodiment shown in Fig.
12 shows areas of a general data driver and a data driver according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic configuration diagram of an organic light emitting display according to an embodiment of the present invention, and FIG. 2 is a schematic circuit configuration diagram of a subpixel.

1, a display device according to an exemplary embodiment of the present invention includes a timing controller 140 (T-CON), a data driver 150 (SD-IC), a scan driver 160 (GD-IC) A panel 170 (PANEL) is included.

The system board 130 receives a video data signal from the outside and converts it into a digital data signal, and outputs a drive signal such as a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The system board unit 130 converts the video data signal into a digital data signal. The timing control unit 140 may convert the video data signal into a digital data signal.

The timing controller 140 receives a color data signal DDATA from the system board 130 in addition to a driving signal such as a data enable signal, a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 140 generates a gate timing control signal GDC for controlling the operation timing of the scan driver 160 and a data timing control signal DDC for controlling the operation timing of the data driver 150 based on the driving signal. . The timing controller 140 outputs the color data signal DDATA in response to the gate timing control signal GDC and the data timing control signal DDC generated based on the driving signal.

The data driver 150 samples and latches the color data signal DDATA in response to the data timing control signal DDC supplied from the timing controller 140 and converts it into an analog data signal corresponding to the gamma reference voltage. The data driver 150 is formed in the form of an IC (Integrated Circuit).

The scan driver 160 outputs a scan signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 140. The scan driver 160 outputs a scan signal through the scan lines SL1 to SLm. The scan driver 160 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 170.

The display panel 170 is implemented with a subpixel structure including a red subpixel SPr, a green subpixel SPg, and a blue subpixel SPb (hereinafter abbreviated as RGB subpixels). The display panel 170 includes a red subpixel SPr, a green subpixel SPg, a blue subpixel SPb, and a white subpixel SPw to prevent luminance decline and color degradation of pure- And RGBW subpixel). That is, one pixel P is composed of RGB subpixels (SPr, SPg, SPb) or RGBW subpixels (SPr, SPg, SPb, SPw). These pixels P are formed in a number corresponding to the resolution of the display panel 170.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR. The switching transistor SW performs a switching operation so that the color data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to the scan signal supplied through the first scan line SL1 . The driving transistor DR operates so that the driving current flows between the first power supply line VDD and the ground line GND in accordance with the data voltage stored in the capacitor Cst.

The compensation circuit CC is a circuit added to compensate the threshold voltage of the driving transistor DR and the like. Thus, the compensation circuit CC may be omitted depending on the configuration of the subpixel, but is usually composed of one or more transistors and capacitors. The configuration of the compensation circuit (CC) is very various, and a detailed illustration and description thereof are omitted.

One subpixel is composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, and an organic light emitting diode (OLED). However, when the compensation circuit (CC) is added, it is composed of 3T1C, 4T2C, 5T2C, and the like. The subpixels having the above-described structure may be formed by a top emission method, a bottom emission method, or a dual emission method according to the structure.

3 is a schematic configuration diagram of the data driver of FIG. 4 shows a part of the configuration of the data driver. 5 is a configuration diagram of a part of the configuration of the gamma voltage generator and the data driver and the output circuit.

As shown in FIG. 3, the timing controller 140 and the data driver 150 are connected by data communication interfaces IF1 and IF2. The timing control unit 140 transmits the color data signal DDATA together with the data timing control signal DDC via its first interface IF1. The data driver 150 receives the color data signal DDATA in addition to the data timing control signal DDC transmitted from the timing controller 140 through the second interface IF2.

The data driver 150 includes a shift register unit 151, a latch unit 152, a gamma voltage generator 154, a digital-to-analog converter (hereinafter referred to as DA converter) 153 and an output circuit unit 155 do.

A source sampling clock (SSC), a source output enable signal (SOE), and the like are input to the data timing control signal (DDC) ) And the like. The source start pulse SSP controls the data sampling start timing of the data driver 150. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver 150 based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver 150.

The shift register unit 151 outputs a sampling signal SAM in response to the source start pulse SSP and the source sampling clock SSC output from the timing controller 140.

The latch unit 152 sequentially samples the digital data signal DDATA in response to the sampling signal SAM output from the shift register unit 151 and outputs the sampled data signal DDATA in response to the source output enable signal SOE And simultaneously outputs sampled color data signals DDATA for one line. The latch portion 152 may be composed of at least two latches, but only one of them has been shown and described for convenience of explanation.

The gamma voltage generator 154 generates first to n-th reference gamma voltages GMA1 to GMAn corresponding to voltages or signals supplied from the outside or the inside. The liquid crystal display device The first to n-th reference gamma voltages GMA1 to GMAn include a positive reference gamma voltage and a negative reference gamma voltage. That is, the gamma voltage generating unit 154 may include a positive gamma voltage generating unit for generating the positive reference gamma voltage and a negative gamma voltage generating unit for generating the negative reference gamma voltage according to the characteristics of the display device.

The DA converter 153 converts the color data signal DDATA for one line in accordance with the first to the nth reference gamma voltages GMA1 to GMAn output from the gamma voltage generator 154 into analog color data signals (ADATA).

As shown in FIG. 4, the DA conversion unit 153 is composed of two or more conversion units (DACs).

5, the DA converter 153 converts digital data in a digital form for one line corresponding to the first to n-th reference gamma voltages (GMA1 to GMAn) output from the gamma voltage generator 154, Converts the signal DDATA into an analog type color data signal ADATA. The digital data signal DDATA may be composed of a first digital signal LSB and a second digital signal MSB. For example, when the digital data signal DDATA is a 10-bit digital signal, the lower 7 bits may correspond to the first digital signal LSB and the upper 3 bits may correspond to the second digital signal MSB .

The DA converter 153 converts the first digital signal LSB to the first voltage V _L based on the reference gamma voltages GMA1 to GMAn supplied from the gamma voltage generator 154, A voltage operation unit 153c that receives the first voltage V _L and the first and second reference voltages V _ADD1 and V _ADD2 and outputs the second voltage V _H , And a second digital-to-analog converter (D / A converter) 153b that receives the first and second voltages V _L and V _H and outputs an analog signal to the second digital signal MSB. Although the first and second reference voltages V _ADD1 and V _ADD2 are shown to be supplied from the gamma voltage generator 154 to the voltage calculator 153c in FIG. 5, the first and second reference voltages V _ADD1 and V _ADD2 are And may be supplied from any external power supply.

Voltage calculating section (153c) is capacitor coupled to output the first voltage (V _L) and a first reference voltage (V _ADD1) and the second reference voltage a second voltage (V _H) by adding the difference value (V _ADD1) de But it may be any circuit that receives two or more voltages, such as a general voltage adder, a voltage subtracter, and a multiplier, and outputs a new output voltage. Therefore, although a capacitor coupled adder having a simple structure is described below as an example of the voltage operation unit 153c, the present invention is not limited thereto.

The output conversion unit 155 may include two or more amplification units (OPs). Each amplifier unit OP is connected to an output terminal of the DAC converter DAC and amplifies the analog signal output from the DA converter 153. [

FIG. 6 is a diagram illustrating a comparison between a part of a conventional data driver and a part of a data driver according to an embodiment of the present invention.

6 (a), a general data driver includes a gamma voltage generator 154, a DA converter 153, and an output circuit 155.

The DA converter 153 converts the first digital signal into the first voltage V _L and the second voltage V _H based on the reference gamma voltages GMA1 to GMAn supplied from the gamma voltage generator 154 And a second digital analog converter (a second DAC) 153b that receives the first and second voltages and outputs an analog signal of the second digital signal.

The DA converter 153 of the general data driver outputs the first voltage V _L and the second voltage V _H using, for example, two first DACs 153a, for example, 7-bit DACs And outputs the final analog signal ADATA using the first voltage and the second voltage in a subsequent 2DAC 153b, for example, a 3-bit interpolation DAC.

Recently, the area of the data driver for driving the display device has been reduced as the display device has changed to high resolution. Accordingly, the area of the DA conversion unit 153 included in the data driver unit must also be reduced. However, since the DA converter 153 of the general data driver must use the two first DACs 153a to convert the first digital signal into the first voltage V _L and the second voltage V _H , There is a big problem.

A data driver 150 according to an exemplary embodiment of the present invention includes a gamma voltage generator 154, a DA converter 153, and an output circuit 155, as shown in FIG. 6 (b).

The DA converter 153 of the data driver 150 according to an embodiment of the present invention includes one first DAC 153a and a voltage calculator 153c for outputting the first voltage and the second voltage, And a second DAC 153b interpolating the voltage and the second voltage to finally output an analog signal.

The DA converter 153 converts one of the first digital signal LSB to the first voltage V _L based on the reference gamma voltages GMA1 to GMAn supplied from the gamma voltage generator 154, The first DAC 153a receives the first voltage V _L output from the first DAC 153a and the first and second reference voltages V _ADD1 and V _ADD2 supplied from the gamma voltage generator 154, receives the voltage voltage calculating section (153c) and the first and second voltage (V _L, V _H) for outputting (V _H) comprise a first 2DAC (153b) for outputting the analog signal to a second digital signal (MSB) . First and second reference voltage (V _ADD1, V _ADD2) is one described as being supplied to the voltage calculating section (153c) from the gamma voltage generator 154, first and second reference voltage (V _ADD1, V _ADD2), as described above May be supplied from any external power supply.

The voltage calculator 153c outputs three inputs and a second voltage to which the first voltage outputted from the first DAC 153a and the first and second reference voltages supplied from the gamma voltage generator 154 are inputted Output terminals. The output terminal of the voltage calculation unit 153c is connected to the input terminal of the output circuit unit 155. [

The voltage calculator 153c compares the first difference V _L -V _ADD1 between the first voltage V _L output from the first DAC 153a and the first reference voltage V _ADD1 and the first difference V _{L- ADD1)} and the second difference value (V _L -V _ADD1), respectively, and sampling the first voltage (V _L) and a first reference voltage and the difference between the second reference voltage of the second reference voltage (V _ADD2) value (V _ADD1- V _ADD2 ) and outputs it as a second voltage.

The voltage operation unit 153c may output the first voltage before adding the first voltage and the difference between the first reference voltage and the second reference voltage and outputting the second voltage.

For example, in the case of a 10-bit digital data signal (DDATA) composed of a lower 7-bit first digital signal (LSB) and a higher 3-bit second digital signal (MSB) The first DAC 153a outputs the first voltage and the voltage calculator 153c outputs the second voltage according to the LSB of the second DAC 153b and the second DAC 153b outputs the second digital signal MSB of 3 bits, Interpolates the first voltage and the second voltage by 3 bits, and finally outputs an analog signal. As a result, the DA converter 153 outputs an analog signal for the 10-bit digital data signal DDATA.

Hereinafter, embodiments of the capacitor-coupled adder will be described in detail with the voltage calculator 153c.

FIG. 7 is a diagram showing a configuration example of the voltage operation unit of FIG. 5 according to the first embodiment. FIG.

Referring to FIG. 7, the capacitor-coupled adder 153c 'according to the first embodiment of the voltage calculator of FIG. 5 includes an amplifier Amp and two capacitors C1 and C2.

The two capacitors (C1, C2) are respectively connected to a first input terminal of the amplifier (Amp), a first difference value between the first voltage (V _L) and a first reference voltage _{(V ADD1) (V L -V} ADD1 And the second difference value V _L -V _ADD1 between the first reference voltage V _ADD1 and the second reference voltage V _ADD2 , respectively. One of the capacitors C1 and C2 of the two capacitors C1 and C2 adds the first voltage V _L and the difference value V _{ADD1 to} V _ADD2 between the first reference voltage and the second reference voltage, And outputs the second voltage (V _H ) to the output terminal.

The capacitor coupled adder 153c 'includes an amplifier Amp, a first capacitor C1 to which a first voltage VL is input and which is located between a first input of the amplifier Amp and the first DAC 153a, A second capacitor C2 to which a first reference voltage VADD1 is inputted and connected to a first input terminal of the amplifier Amp, a first switch SW1 for inputting a first voltage VL to the first capacitor C1, A second switch SW2 for inputting the first reference voltage VADD1 to the second capacitor C2 and a second switch SW2 for switching between the node between the first switch SW1 and the first capacitor C1 and the output terminal of the amplifier Amp A fifth switch SW5 located between the first input terminal and the output terminal of the amplifier Amp and a sixth switch SW6 connected to the output terminal of the amplifier Amp; And a seventh switch SW7 positioned between the input terminal of the reference voltage VADD1 and the second input terminal of the amplifier Amp.

The second reference voltage V _ADD2 is supplied to the second input terminal of the amplifier Amp.

FIG. 8 is a driving example of the voltage calculating unit of FIG. 5 according to the first embodiment. FIG. In FIG. 8, the first capacitor C1 and the second capacitor C2 are illustratively described as being, for example, 300 nF.

8, the first voltage outputted from the first DAC 153a and the first and second reference voltages supplied from the gamma voltage generator 154 are input to the three input terminals of the capacitor coupled adder 153c ' do.

At this time, the first switch SW1, the second switch SW2 and the fifth switch SW5 are turned on and the fourth switch SW4, the sixth switch SW6 and the seventh switch SW7 are turned off The first difference value VL-VADD2 between the first voltage VL and the second reference voltage VADD2 is sampled at both ends of the first capacitor C1 and the first difference between the first reference voltage VADD1 and the second reference voltage VADD2, The second difference value VADD1-VADD2 of the voltage VADD2 is sampled at both ends of the second capacitor C2 (hereinafter referred to as a sampling step).

Next, the fourth switch SW4, the sixth switch SW6 and the seventh switch SW7 are turned on, and the first switch SW1, the second switch SW2, the third switch SW3, When the fifth switch SW5 is turned off, the first voltage VL and the difference value VADD1-VADD2 between the first reference voltage and the second reference voltage are added to the second voltage VH (VADD1-VADD2) ) (Hereinafter referred to as " addition step ").

As a result, the capacitor coupled adder 153c 'outputs VL + (VADD1-VADD2) to the second voltage (VH) through the sampling step and the adding step. The capacitor coupled adder 153c 'outputs the second voltage only through the sampling step and the adding step, thereby simplifying the voltage calculation process.

FIG. 9 is a configuration diagram of the voltage calculator of FIG. 5 according to the second embodiment. FIG.

Referring to FIG. 9, the capacitor-coupled adder 153c " according to the second embodiment of the voltage calculator includes an amplifier Amp, two capacitors C1 and C2, and a bypass switch.

The two capacitors (C1, C2) are respectively connected to a first input terminal of the amplifier (Amp), a first difference value between the first voltage (V _L) and a first reference voltage _{(V ADD1) (V L -V} ADD1 And the second difference value V _L -V _ADD1 between the first reference voltage V _ADD1 and the second reference voltage V _ADD2 , respectively. One of the capacitors C1 and C2 of the two capacitors C1 and C2 adds the first voltage V _L and the difference value V _{ADD1 to} V _ADD2 between the first reference voltage and the second reference voltage, And outputs the second voltage (V _H ) to the output terminal.

The capacitor coupled adder 153c 'includes an amplifier Amp, a first capacitor C1 to which a first voltage VL is input and which is located between a first input of the amplifier Amp and the first DAC 153a, A second capacitor C2 to which a first reference voltage VADD1 is inputted and connected to a first input terminal of the amplifier Amp, a first switch SW1 for inputting a first voltage VL to the first capacitor C1, A second switch SW2 for inputting the first reference voltage VADD1 to the second capacitor C2 and a second switch SW2 for inputting the first reference voltage VADD1 between the node between the first switch SW1 and the first capacitor C1 and the output terminal of the amplifier Amp A fourth switch SW4, a fifth switch SW5 located between the first input and output of the amplifier Amp, a sixth switch SW6 connected to the output of the amplifier Amp, And a seventh switch SW7 positioned between the input terminal of the first reference voltage VADD1 and the second input terminal of the amplifier Amp.

The second reference voltage V _ADD2 is supplied to the second input terminal of the amplifier Amp.

The capacitor coupled adder 153c " according to the second embodiment of the voltage operation unit adds the third switch SW3 as a bypass switch located between the input terminal of the first voltage (VL) and the output terminal of the second voltage . The third switch SW3 is located between the input terminal of the first voltage VL and the second output terminal and is connected to the first voltage VL and the first reference voltage VADD1 and the second reference voltage VADD2 And outputs the first voltage VL before outputting the second voltage VH to the output terminal of the amplifier.

10 is a driving example of the voltage calculator of FIG. 5 according to the second embodiment. In FIG. 10, the first capacitor C1 and the second capacitor C2 are illustratively described as being, for example, 300 nF.

The first voltage output from the first DAC 153a and the first and second reference voltages supplied from the gamma voltage generator 154 are input to the three input terminals of the capacitor coupled adder 153c '.

10A, the first switch SW1, the second switch SW2, the third switch SW3, and the fifth switch SW5 are turned on in the sampling step and the fourth switch The first difference value V _L -V _ADD2 between the first voltage V _L and the second reference voltage V _ADD2 is applied to the first switch SW4, the sixth switch SW6, and the seventh switch SW7, And the second difference value V _ADD1 -V _{ADD2 of} the first reference voltage V _ADD1 and the second reference voltage V _ADD2 is sampled at both ends of the first capacitor C1, Sampled at both ends. In the sampling step, voltages necessary for voltage addition are applied to both terminals of the two capacitors to charge the charges. The third switch SW3 is turned on to output the first voltage V _L before outputting the second voltage V _H to the output terminal of the amplifier Amp.

As shown in FIG. 10 (b), when the fifth switch SW5 is turned off in the sampling step, in order to prevent discharging when switching to the adding step in the sampling step, one node of the capacitor Floating is allowed to fix the amount of charge (hereinafter referred to as a "pruning step").

The third switch SW3, the fourth switch SW4, the sixth switch SW6 and the seventh switch SW7 are turned on in the adding step as shown in Fig. 10 (c) (V _ADD1 -V _ADD2 ) between the first voltage (V _L ) and the first reference voltage and the second reference voltage when the first switch (SW1), the second switch (SW2) and the fifth switch (SW5) And outputs V _L + (V _ADD1 -V _ADD2 ) as the second voltage (V _H ). And outputs a voltage value obtained by serially adding voltage values sampled in the sampling step in the adding step.

The DA converter 153 precharges the first voltage to the second DAC 153b when a second voltage is sampled and added, and when the second voltage is added to the second DAC 153b, And the addition delay time can be reduced.

Fig. 11 is an output waveform (a) of the voltage operation unit according to the first embodiment shown in Fig. 7 and an output waveform (b) of the voltage operation unit according to the second embodiment shown in Fig.

Since the voltage operation unit 153c 'according to the first embodiment shown in FIG. 7 does not have the bypass switch, the voltage operation unit 153c' samples and adds the second voltage VH, 2 voltage (VH) is output.

Since the third switch SW3 is included in the voltage operation unit 153c " according to the second embodiment shown in Fig. 9 as the bypass switch, during the addition of the second voltage VH from the voltage operation unit 153c " The second DC voltage is precharged to the first voltage VL when the second voltage VH is output by precharging the second DC voltage 152 with the first voltage VL by the path, The voltage can be changed only by a certain amount (DELTA V = VADD1-VADD2), which is advantageous in terms of time.

More specifically, the voltage calculator 153c 'according to the first embodiment shown in FIG. 7 calculates the second voltage VH in a state in which the second DC voltage is not precharged with the first voltage VL during the addition of the second voltage VH. The time for completing the output of the second voltage VH (A in FIG. 11 (b)) is relatively long because the second voltage VH is finally output after the addition of the voltage VH is completed. On the other hand, the voltage calculator 153c " according to the second embodiment shown in Fig. 9 precharges the second DAC 152 with the first voltage (VL) by bypass while adding the second voltage (VH) Since the voltage should be changed only by the amount (? V = VADD1-VADD2) that is previously charged to the first voltage (VL) and finally partially changed to the first voltage (VL) The time (B in Fig. 11 (b)) for completing the output of the second voltage VH is relatively long.

12 shows areas of a general data driver and a data driver according to an embodiment.

As shown in FIG. 12, when the data driver 150 according to an exemplary embodiment is compared with a general data driver, the data driver 150 and the second DAC 153b of the DA converter in the exemplary embodiment of FIG. The area is the same. The area of the first DAC 153a of the data driver 150 according to the embodiment is smaller than that of the first DAC 153a of the general data driver and the area of the added voltage calculator 153c is relatively small. The data driver 150 according to the example can reduce the area of the DA converter 150 by 57.3% based on the number of transistors of the first DAC 153a as compared with a general data driver.

According to the embodiments described above, the number of transistors of the digital-to-analog converter included in the data driver can be reduced to reduce the area of the digital-analog converter.

According to the above-described embodiment, the area of the digital-analog converting unit is reduced, thereby reducing the area of the data driver.

According to the above-described embodiment, the number of transistors of the digital-analog converter can be reduced, and the power consumption of the data driver can be reduced.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

130: system board section 140: timing control section
150: Data driver 160:
170: Display panel DDATA: Color data signal
152: latch unit 153: DA conversion unit
154: gamma voltage generator 155: output circuit

Claims (12)

A first digital-to-analog converter converting the first digital signal to a first voltage in a digital signal including a first digital signal and a second digital signal based on a reference gamma voltage;
A voltage operation unit receiving the first voltage, first and second reference voltages, and outputting a second voltage; And
And a second digital-to-analog converter for receiving the first and second voltages and outputting an analog signal to the second digital signal. The method according to claim 1,
Wherein the voltage operation unit is a capacitor coupled adder that adds the first voltage and the difference between the first reference voltage and the second reference voltage and outputs the result as the second voltage. part. 3. The method of claim 2,
The capacitor coupled adder may comprise:
amplifier;
Each of the two capacitors being connected to a first input of the amplifier and sampling a first difference between the first voltage and the second reference voltage and a second difference between the first reference voltage and the second reference voltage, And outputs the second voltage to the output terminal of the amplifier by adding the first voltage and a difference between the first reference voltage and the second reference voltage;
A first reference voltage generating circuit for generating a first reference voltage and a second reference voltage by adding the first voltage and the difference between the first reference voltage and the second reference voltage to the amplifier stage of the amplifier, And a switch for outputting the first voltage before outputting the second voltage. 3. The method of claim 2,
The capacitor coupled adder comprises:
amplifier;
A first capacitor to which the first voltage is input, the first capacitor being located between the first input of the amplifier and the first digital to analog converter;
A second capacitor receiving the first reference voltage and being connected to a first input of the amplifier;
A first switch for inputting the first voltage to the first capacitor;
A second switch for inputting the first reference voltage to the second capacitor;
A fourth switch positioned between a node between the first switch and the first capacitor and an output terminal of the amplifier;
A fifth switch positioned between a first input and an output of the amplifier;
A sixth switch connected to an output terminal of the amplifier;
And a seventh switch located between the terminal to which the first reference voltage is input and the second input terminal of the amplifier in the second capacitor. The method of claim 3,
The capacitor coupled adder comprises:
And a third switch located between the input terminal of the first voltage and the output terminal of the second voltage. A digital-analog converter for converting a digital signal including a first digital signal and a second digital signal into an analog signal; And
And an output buffer for outputting the analog signal as an output signal,
The digital-to-
A first digital-to-analog converter for converting the first digital signal to a first voltage based on a reference gamma voltage,
A voltage operation unit receiving the first voltage, first and second reference voltages, and outputting a second voltage;
And a second digital-to-analog converter that receives the first and second voltages and outputs an analog signal to the second digital signal. The method according to claim 6,
Wherein the voltage operation unit is a capacitor coupled adder that adds the first voltage and a difference between the first reference voltage and the second reference voltage and outputs the result as the second voltage. 8. The method of claim 7,
The capacitor coupled adder may comprise:
amplifier;
Each of the capacitors being connected to a first input of the amplifier and sampling a first difference between the first voltage and the first reference voltage and a second difference between the first reference voltage and the second reference voltage, And outputs the second voltage to the output terminal of the amplifier by adding the first voltage and a difference between the first reference voltage and the second reference voltage;
A first reference voltage generating circuit for generating a first reference voltage and a second reference voltage by adding the first voltage and the difference between the first reference voltage and the second reference voltage to the amplifier stage of the amplifier, And a switch for outputting the first voltage before outputting the second voltage. The method according to claim 6,
The capacitor coupled adder comprises:
amplifier;
A first capacitor to which the first voltage is input, the first capacitor being located between the first input of the amplifier and the first digital to analog converter;
A second capacitor receiving the first reference voltage and being connected to a first input of the amplifier;
A first switch for inputting the first voltage to the first capacitor;
A second switch for inputting the first reference voltage to the second capacitor;
A fourth switch positioned between a node between the first switch and the first capacitor and an output terminal of the amplifier;
A fifth switch positioned between a first input and an output of the amplifier;
A sixth switch connected to an output terminal of the amplifier;
And a seventh switch located between the terminal to which the first reference voltage is input and the second input terminal of the amplifier in the second capacitor. 8. The method of claim 7,
The capacitor coupled adder comprises:
And a third switch located between an input terminal of the first voltage and an output terminal of the second voltage. Display panel;
And a second voltage is applied to the first and second reference voltages to convert the first digital signal into a first voltage based on a reference gamma voltage, A data driver for receiving a voltage and outputting a second digital signal as an analog signal; And
And a timing controller for controlling the data driver. 12. The method of claim 11,
Wherein the data driver includes a capacitor coupled adder that adds the first voltage and a difference between the first reference voltage and the second reference voltage and outputs the result as the second voltage.

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