KR101603307B1 - Ditigal to analog converting device and data driver - Google Patents

Abstract

The present invention provides a digital analog converting unit and a data driving unit using the same. The digital analog converting unit comprises: a first decoder controlled by an upper (N-1) bit from a first digital signal to output one of 2^(N-1) reference gamma voltages as a first selection voltage; and a second decoder controlled by an N bit first digital signal to output another one of the 2^(N-1)+1 reference gamma voltages as a second selection voltage. According to the second decoder, in N-2 XOR groups in which reference gamma voltages having Dx (x is a natural number which is greater than 0 and lower than N-2) and D(x+1) which are XOR are grouped from a first digital signal, each of the XOR groups comprises tree-structure switches controlled by upper bits which are greater than D(x+1) and XOR-structure switches controlled by Dx and D(x+1).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital-

The present invention relates to a data driver and a display using the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display (EPD), and a plasma display panel (PDP) ) Have been increasingly used.

In recent years, in order to realize a high resolution of a display device, the size of the data driver has been increased, and it has been required to improve the manufacturing cost and the power consumption.

According to an aspect of the present invention, there is provided a digital-to-analog (D / A) converter for reducing a size of a data driver and reducing a production cost by reducing the number of components constituting a size and a digital- And a display device using the same.

The present invention also provides a digital-to-analog converter capable of reducing power consumption, a data driver using the same, and a display device using the same.

The present invention also provides a digital-to-analog converter capable of reducing the time for converting digital data into an analog signal and reducing the driving time of the data driver, a data driver using the same, and a display using the same.

The present invention in the above-described problem solving means is (2 ^N-1 +1) Based on the gamma voltages (N is a natural number greater than 2) based on the first digital signal (D (N-1) of the N-bit, D ( A first digital-to-analog converter converting the first and second voltages to a first voltage and a second voltage, and a second digital-to-analog converter converting the first and second voltages into a first voltage and a second voltage, Wherein the first digital to analog converter is controlled by an upper (N-1) bit of the first digital signal to output one of the ( ^2N-1 ) reference gamma voltages as a first selected voltage ( ^2N-1 + 1) -th reference gamma voltages; and a second decoder for outputting a second selection voltage of the ( ^2N-1 + 1) 2) XOR groups in which 2 ^NX-2 reference gamma voltages having a magnitude larger than x = 0 and smaller than N-2 are grouped and two reference gamma voltages having Dx + 1 equal to XOR are grouped, each XOR group is higher than D (x + 1) Bits A second decoder including switches of a tree structure controlled by Dx and D (x + 1), switches of an XOR structure controlled by Dx and D (x + 1), a second decoder including switches of a first selection voltage and a second selection voltage, And a switch unit for selectively outputting the voltage of the data signal to the data line.

In another aspect, the present invention provides ^N- bit first digital signals D (N-1) and D (N-2) based on ( ^2N-1 +1) reference gamma voltages (N is a natural number greater than 2) ), ..., D2, D1, D0) into a first voltage and a second voltage, and a second digital-to-analog converter (ADC) receiving the first and second voltages and outputting the second digital signal as an analog signal Wherein the first digital to analog converter is controlled by an upper (N-1) bit of the first digital signal to output one of (2 ^N-1 ) reference gamma voltages as a first ( ^N-1 ) -th reference digital gamma voltages, and outputs the second selected voltage to the other of the ( ^2N-1 + 1) reference gamma voltages controlled by the first digital signal of ^N bits, One XNOR group in which the three reference gamma voltages in which D (N-2) to D0 are XNOR except for N (N-1) is a tree group controlled by higher bits than D (N-2) A second decoder including switches of the XNOR structure controlled by D (N-2) to D0, a first decoder for selectively outputting the first selection voltage and the second selection voltage to the first voltage and the second voltage, And a data driver using the digital-analog converter.

The present invention has the effect of reducing the size of the data driver by reducing the size of the digital-analog converter.

The present invention has the effect of reducing the size of the data driver by reducing the number of components constituting the digital-to-analog converter.

In addition, the present invention has the effect of reducing the number of components constituting the digital-to-analog converter and reducing the power consumption of the data driver.

In addition, the present invention has the effect of reducing the number of components constituting the digital-to-analog converter and reducing the production cost of the data driver.

1 is a schematic block diagram of an organic light emitting display according to an embodiment of the present invention.
2 is a schematic circuit configuration diagram of a subpixel.
3 is a schematic configuration diagram of the data driver of FIG.
4 shows a part of the configuration of the data driver.
5 is a configuration diagram of a part of the configuration of the gamma voltage generator and the data driver and the output circuit.
6 is a configuration diagram of a first DAC of a DA conversion unit according to an embodiment.
7A is a block diagram of a second decoder (4 bits) of the first DAC of the DA conversion unit.
7B is a block diagram of a second decoder (5 bits) of the first DAC of the DA conversion unit according to another embodiment.
7C is a block diagram of a second decoder (N bits) of the first DAC of the DA conversion unit.
8 is a circuit diagram of a 4-bit first DAC of a DA conversion unit according to an embodiment.
9 is a circuit diagram of a modified 4-bit first DAC of a DA conversion unit according to an embodiment.
10 is a circuit diagram of a 5-bit first DAC of a DA conversion unit according to another embodiment.
11 is a configuration diagram of a first DAC of a general DA conversion unit.
12 is a graph comparing the number of transistors according to the resolution (number of bits) of the second decoders of the general first DAC shown in FIG. 11 and the second decoders of the first DAC according to the embodiments of the present invention
13 shows areas of a data driver according to a general data driver and embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic configuration diagram of an organic light emitting display according to an embodiment of the present invention, and FIG. 2 is a schematic circuit configuration diagram of a subpixel.

1, a display device according to an exemplary embodiment of the present invention includes a timing controller 140 (T-CON), a data driver 150 (SD-IC), a scan driver 160 (GD-IC) A panel 170 (PANEL) is included.

The system board 130 receives a video data signal from the outside and converts it into a digital data signal, and outputs a drive signal such as a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The system board unit 130 converts the video data signal into a digital data signal. The timing control unit 140 may convert the video data signal into a digital data signal.

The timing controller 140 receives a color data signal DDATA from the system board 130 in addition to a driving signal such as a data enable signal, a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 140 generates a gate timing control signal GDC for controlling the operation timing of the scan driver 160 and a data timing control signal DDC for controlling the operation timing of the data driver 150 based on the driving signal. . The timing controller 140 outputs the color data signal DDATA in response to the gate timing control signal GDC and the data timing control signal DDC generated based on the driving signal.

The data driver 150 samples and latches the color data signal DDATA in response to the data timing control signal DDC supplied from the timing controller 140 and converts it into an analog data signal corresponding to the gamma reference voltage. The data driver 150 is formed in the form of an IC (Integrated Circuit).

The scan driver 160 outputs a scan signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 140. The scan driver 160 outputs a scan signal through the scan lines SL1 to SLm. The scan driver 160 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 170.

The display panel 170 is implemented with a subpixel structure including a red subpixel SPr, a green subpixel SPg, and a blue subpixel SPb (hereinafter abbreviated as RGB subpixels). The display panel 170 includes a red subpixel SPr, a green subpixel SPg, a blue subpixel SPb, and a white subpixel SPw to prevent luminance decline and color degradation of pure- And RGBW subpixel). That is, one pixel P is composed of RGB subpixels (SPr, SPg, SPb) or RGBW subpixels (SPr, SPg, SPb, SPw). These pixels P are formed in a number corresponding to the resolution of the display panel 170.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR. The switching transistor SW performs a switching operation so that the color data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor Cst in response to the scan signal supplied through the first scan line SL1 . The driving transistor DR operates so that the driving current flows between the first power supply line VDD and the ground line GND in accordance with the data voltage stored in the capacitor Cst.

The compensation circuit CC is a circuit added to compensate the threshold voltage of the driving transistor DR and the like. Thus, the compensation circuit CC may be omitted depending on the configuration of the subpixel, but is usually composed of one or more transistors and capacitors. The configuration of the compensation circuit (CC) is very various, and a detailed illustration and description thereof are omitted.

One subpixel is composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor SW, a driving transistor DR, a capacitor Cst, and an organic light emitting diode (OLED). However, when the compensation circuit (CC) is added, it is composed of 3T1C, 4T2C, 5T2C, and the like. The subpixels having the above-described structure may be formed by a top emission method, a bottom emission method, or a dual emission method according to the structure.

3 is a schematic configuration diagram of the data driver of FIG. 4 shows a part of the configuration of the data driver. 5 is a configuration diagram of a part of the configuration of the gamma voltage generator and the data driver and the output circuit.

As shown in FIG. 3, the timing controller 140 and the data driver 150 are connected by data communication interfaces IF1 and IF2. The timing control unit 140 transmits the color data signal DDATA together with the data timing control signal DDC via its first interface IF1. The data driver 150 receives the color data signal DDATA in addition to the data timing control signal DDC transmitted from the timing controller 140 through the second interface IF2.

The data driver 150 includes a shift register unit 151, a latch unit 152, a gamma voltage generator 154, a digital-to-analog converter (hereinafter referred to as DA converter) 153 and an output circuit unit 155 do.

A source sampling clock (SSC), a source output enable signal (SOE), and the like are input to the data timing control signal (DDC) ) And the like. The source start pulse SSP controls the data sampling start timing of the data driver 150. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver 150 based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver 150.

The shift register unit 151 outputs a sampling signal SAM in response to the source start pulse SSP and the source sampling clock SSC output from the timing controller 140.

The latch unit 152 sequentially samples the digital data signal DDATA in response to the sampling signal SAM output from the shift register unit 151 and outputs the sampled data signal DDATA in response to the source output enable signal SOE And simultaneously outputs sampled color data signals DDATA for one line. The latch portion 152 may be composed of at least two latches, but only one of them has been shown and described for convenience of explanation.

The gamma voltage generator 154 generates first to n-th reference gamma voltages GMA1 to GMAn corresponding to voltages or signals supplied from the outside or the inside. In the case of the liquid crystal display device, the first to n-th reference gamma voltages GMA1 to GMAn include a positive reference gamma voltage and a negative reference gamma voltage. That is, the gamma voltage generating unit 154 may include a positive gamma voltage generating unit for generating the positive reference gamma voltage and a negative gamma voltage generating unit for generating the negative reference gamma voltage according to the characteristics of the display device.

The DA converter 153 converts the color data signal DDATA for one line in accordance with the first to the nth reference gamma voltages GMA1 to GMAn output from the gamma voltage generator 154 into analog color data signals (ADATA).

5, the DA converter 153 converts digital data in a digital form for one line corresponding to the first to n-th reference gamma voltages (GMA1 to GMAn) output from the gamma voltage generator 154, Converts the signal DDATA into an analog type color data signal ADATA. The digital data signal DDATA may be composed of a first digital signal (upper data or MSB) and a second digital signal (lower data or LSB). When the digital data signal DDATA is an M-bit digital signal, the upper N bits correspond to the first digital signal LSB and the lower M-N bits correspond to the second digital signal MSB. For example, if the digital data signal DDATA is a 10-bit digital signal, the upper 7 bits may correspond to the first digital signal LSB and the lower 3 bits may correspond to the second digital signal MSB .

The DA converter 153 converts the first digital signal MSB to the first voltage V _L and the second voltage V _H (V _H ) based on the reference gamma voltages GMA1 to GMAn supplied from the gamma voltage generator 154. [ And a second digital analog converter (a second DAC) 153b that receives the first and second voltages and outputs an analog signal to the second digital signal LSB, . An amplifier may be positioned between the first DAC 153a and the second DAC 153b to amplify the first voltage V _L and the second voltage V _H , as shown in FIG. 5 (b).

The DA converter 153 of the data driver 153 outputs the first voltage VL and the second voltage VH using, for example, the first DACs 153a, for example, 7-bit first DACs And outputs the final analog signal ADATA using the first voltage and the second voltage in the second DAC 153b, for example, a 3-bit interpolator 2DAC.

For example, when the first DAC 153a selects the two first voltages VL and VH adjacent to each other in accordance with the 7-bit first digital signal MSB, It is possible to generate a linear voltage between the first and second voltages VL and VH and generate an output signal using the second digital signal LSB of 3 bits. 2046 (2N + 1-2) transistors are required using one 10-bit DA converter 153, but two first voltages (VL) are required in the DAC system of this type 522 transistors are used because two 7-bit first DAC 153a and one 3-bit second DAC 153b are used to select the second voltage VH.

A product having a high resolution of the DA converter 153 is being marketed and a resolution of the DA converter 153 is increased. The price of the data driver increases. In order to suppress the increase of the price, products formed by separating the DA converter 153 into the first DAC 153a and the second DAC 153b are applied. However, even in such products, the DA converter 153 can not acquire the data occupied by the data driver 150 The area occupies a large part.

In order to solve such a problem, in order to reduce the number of switches or transistors used in the second decoder 153ab, the DA converter 150a according to embodiments for reducing the size of the DA converter by grouping the reference gamma voltages selected by the same rule, A data driver, and a display device using the same will be described.

6 is a configuration diagram of a first DAC of a DA conversion unit according to an embodiment. 7A is a block diagram of a second decoder (4 bits) of the first DAC of the DA conversion unit. 7B is a block diagram of a second decoder (5 bits) of the first DAC of the DA conversion unit according to another embodiment. 7C is a block diagram of a second decoder (N bits) of the first DAC of the DA conversion unit.

The 1DAC (153a) of the DA conversion unit 153 is a first decoder which one is controlled by the digital signal output to one of a portion of the 2 ^N-1 of the reference gamma voltage to the first selection voltage (V _x) (153aa A second decoder 153ab which is controlled by the first digital signal and outputs the other of the ( ^2N-1 + 1) reference gamma voltages as a second selection voltage V _Y , and a (V _x) and a second selection voltage (V _Y) of the first voltage switch portion (153ac) which selectively outputs the (V _H) and a second voltage (V _L).

In the case of the N-bit first DAC 153, the first decoder 153aa is controlled by the upper (N-1) bits and the second decoder 153ab is controlled by the N bits.

The first decoder 153aa is composed of switches of a tree structure controlled by the upper (N-1) bits of the first digital signal of N bits. A first decoder (153aa) of the first of the digital signals is controlled by the upper (N-1) bits (2 ^N-1) of the even-numbered (or odd-numbered) based on the gamma voltages, a first selection voltage (Vx of .

The second decoder 153ab is controlled by an N-bit first digital signal to output the second selection voltage to the other of the ( ^2N-1 + 1) odd-numbered (even-numbered) reference gamma voltages.

As shown in FIG. 7A, when the first digital signal is, for example, 4 bits, the second decoder 153ab is controlled by the 4-bit first digital signals D3, D2, D1 and D0, And outputs the other one of the voltages V0, V2, V4, V6, V8, V10, V12, V14, and V16 as the second selection voltage V _Y. When the first digital signals D0 and D1 are XOR ("01" or "10"), the nine odd-numbered reference gamma voltages V0, V2, V4, V6, V8, V10, V12, V14, The four reference voltage groups V2, V4, V10 and V14 selected are grouped into a first group of XORs 711, two reference voltages V4 and V2 selected when X1 and X2 are XOR and D1 and D2 are XOR, V8 and V16 selected when the grouped second XOR groups 712, D2, D1 and D0 are XNOR ("00" or "11") are grouped into a grouped XNOR group 720).

As shown in FIG. 7B, when the first digital signal is, for example, 5 bits, the second decoder 153ab is controlled by the 5-bit first digital signals D4, D3, D2, D1, The other one of the reference gamma voltages V0, V2, V4, ..., V30, and V32 is output as the second selection voltage VY. The eightteen reference gamma voltages V0, V2, V4, ..., V30 and V32 of the seventeenth odd-numbered reference gamma voltages are selected when the D0 and D1 of the first digital signal are XOR ("01" V4, V12, V20, and V28, which are selected when D0 and D1 are XNOR and D1 and D2 are XOR, respectively, in the first XOR group 711 in which the voltages V2, V6, Grouped second XOR group 712, two reference gamma voltages V8 and V24 selected when D0 and D1 and D2 are XNOR and D2 and D3 are XOR, and a third group of XOR groups 713 and D3 , And three reference voltages (V0, V16, V32) with D2, D1, and D0 being XNOR ("00" or "11") grouped into XNOR groups 720.

As shown in FIG. 7C, when the first digital signal is N bits, the 2 decoder 153ab outputs N-bit first digital signals D (N-1), D (N-2) ( ^2N-1 + 1) odd-numbered reference gamma voltages V0, V2, V4, ..., V ( ^2N- 2), V ( ^2N ) controlled by D2, D1, And outputs one of them as the second selection voltage (V _Y ). (2 ^N-1 +1) of the odd-numbered reference gamma voltages (V0, V2, V4, ... , V (2 N -2), V (2 N)) is in the D0 and D1 of the first digital signal XOR ^{2 N-2} of the reference gamma voltages (V2, V6, ..., V (2 N -4), V (2 N -2)) is a group of grouping claim 1XOR (711), D1 and D2 of the ^N XOR 2 ^- the ^three gamma reference voltages (V4, V12, ..., V (2 -12 ^N), V (2 ^N -4)) are grouped claim 2XOR group 712, a 2 ^N- is D2 and D3 XOR the ^fourth reference gamma voltages (V8, V24, ..., V (2 N -24), V (2 N -8)) than N-2 is greater than Dx (x = 0, etc. the 3XOR group 713. the grouping (N-2), D (N-3), and N-2 XOR groups in which 2 ^NX-2 reference gamma voltages with D (x + 1) , ..., 2, D1, D0 is a can include the three reference voltages ^{(V0, V (2 N -1} ), V (2 N)) the grouping XNOR group (720) XNOR.

Table 1 shows a reference gamma voltage to be selected by the first decoder 153aa and the second decoder 153bb using a general DAC structure as a digital signal and is represented by a 5-bit DAC.

[Table 1]

The reference gamma voltage inputted to the first decoder 153aa is 16, the reference gamma voltage inputted to the second decoder 153ab is 17, and the two decoders 153aa and 153ab are connected to two adjacent reference [V0, V1], [V2, V1], [V2, V3] ... Since the gamma voltage must be selected, [V28, V29], [V30, V29], [V30, V31] and other reference gamma voltages except V0 and V31 are selected from two digital signals.

Table 2-1 shows only the portion of the first decoder 153aa in Table 1 for easy understanding, and two digital signals for selecting the reference gamma voltage in all the gradations are upper (MSB) 4 bits excluding the lower (LSB) And the 4-bit decoder using the upper (MSB) 4 bits.

[Table 2-1]

Table 2-2 shows only the portion of the second decoder 153ab in Table 1. Since there is no regularity of the two digital signals for selecting the reference gamma voltage in all the gradations, the reference gamma voltage should be selected according to each digital signal A 5-bit decoder is used. As a result, since the number of reference gamma voltages selected from the first decoder 153aa is one more but the regularity is not in the second decoder 153ab, the number of switches or transistors to be used is doubled .

[Table 2-2]

Table 3-1 shows that the lower bits (LSB) are D1 and D0 in order to sort the regularity of the second decoder 153ab. When the respective reference gamma voltages are selected, D1 and D0 are "01" Or "10", and when it is "00" or "11" such as XNOR.

So first, the lower 2 bits are selected when D1 and D0 are XOR and when XNOR? And when it is selected when XOR is selected, it can be confirmed that the remaining upper bits of the two digital signals selecting the reference gamma voltage are the same.

[Table 3-1]

Table 3-2 shows the cases where D2 and D1, which are one bit high, are selected as XOR and XNOR when D1 and D0 are selected as XNOR in Table 3-1. If it is also selected in the case of XOR, it can be confirmed that the remaining upper bits of the two digital signals selecting the reference gamma voltage are the same.

[Table 3-2]

Table 3-3 shows the cases where D3 and D2, which are one bit high, are selected as XOR and XNOR when D2 and D1 are selected as XNOR as shown in Table 3-2. The reference gamma voltage becomes three. In other words, the first, middle, and final reference gamma voltages are left until the voltage is left.

[Table 3-3]

In the case of the N-bit second decoder 153ab, the number of reference gamma voltages to be selected as shown in FIG. 7C is ( ^2N-1 + 1) and the number of reference gamma voltages in which D1 and D0 are XOR is 2 ^N-2 , and the number of reference gamma voltages in which D1 and D0 are XOR is reduced by ½ as the number of bits to be grouped into ^2N-3 increases, and the number of reference gamma voltages to be grouped is 2N-2 / 2N-3 / 2N-4 / ... / 3.

Table 4 shows that the result of grouping the reference gamma voltages having the same XOR and XNOR results in Table 3-3 shows that the remaining upper bits are the same in each grouping, and in the case of 5 bits, As shown in FIG.

[Table 4]

As shown in FIG. 7A, the 4-bit second decoder 153ab outputs the reference gamma voltages V2, V4, V10 and V14 to D1 ^ D0 (XOR) corresponding to the first XOR group 711, ) Grouping decoder 731 and a D2 D1 (XOR) grouping decoder 732 corresponding to the second XOR group 712 in which the two reference voltages V4 and V12 are grouped, three reference voltages V0 and V8 V16, and V16 XNOR decoders 740 corresponding to the grouped XNOR group 720, and a function of selecting one of the XOR and the reference gamma voltages selected from the XNOR decoder according to the digital signal, And an XOR decoder 750. The XOR decoder 750 is an XOR decoder.

Similarly, as shown in FIG. 7B, the 5-bit second decoder 153ab is configured to divide the 8 reference gamma voltages V2, V6, ..., V26, V30 into D1 ^ D0 XOR) grouping decoder 731 and a D2 D1 (XOR) grouping decoder 732 corresponding to the second XOR group 712 in which the four reference gamma voltages V4, V12, V20 and V28 are grouped, A D2 D1 (XOR) grouping decoder 733 corresponding to the third XOR group 713 in which the gamma voltages V8 and V24 are grouped and an XNOR group 733 in which the three reference voltages V0, V16 and V322 are grouped XNOR decoder 740 for selecting one of the XORs and the reference gamma voltages selected from the XNOR decoders in accordance with the digital signal and outputting the selected one of the reference gamma voltages to the XOR decoder 750 .

)이 그룹핑된 XNOR그룹(720)에 대응하는

XNOR 디코더(740), 디지털신호에 따라서 각각의 XOR와 XNOR 디코더에서 선택된 기준감마전압 중에서 1개를 선택하여 출력하는 기능을 하는 XOR, XNOR 디코더(750)로 구성된다.
Similarly, as shown in FIG. 7C, the N-bit second decoder 153ab includes a D1 ^ D0 (XOR) grouping decoder 731 corresponding to the first XOR group 711 and a D2 ^ A D1 (XOR) grouping decoder 732, a D2 D1 (XOR) grouping decoder 733 corresponding to the third XOR group 713, ... , XOR group (73x) grouped by 2 ^NX-2 reference gamma voltages with Dx and Dx + 1 being XOR, ... , Three reference voltages (

) Corresponding to the grouped XNOR group 720

An XNOR decoder 740, and an XOR and XNOR decoder 750 for selecting and outputting one of the XOR and the reference gamma voltages selected from the XNOR decoder according to the digital signal.

In other words, the N-bit second decoder 153ab includes N-2 XOR decoders 731 and 732 corresponding to N-2 XOR groups, an XNOR decoder 740, And an XOR and XNOR decoder 750 for selecting and outputting one of the reference gamma voltages selected by the XNOR decoder.

8 is a circuit diagram of a 4-bit first DAC of a DA conversion unit according to an embodiment. 9 is a circuit diagram of a modified 4-bit first DAC of a DA conversion unit according to an embodiment.

As shown in FIGS. 8 and 9, the first decoder 153aa includes switches of a tree structure controlled by a first digital signal of N-1 bits. The tree structure refers to a structure in which upper nodes and lower nodes are hierarchically connected. In this case, the tree structure may be a binary tree type in which the number of children of all nodes is two.

The switches included in the first decoder 153aa may be implemented by various types of transistors such as a PMOS transistor, an NMOS transistor, and a CMOS transistor

As described above, when the first digital signal is N-bit and the even-numbered reference gamma voltages connected to the first decoder 153aa are ^2N-1 , the first decoder 153aa includes ^2N- 2 switches. That is, 2 ^N -2 switches can be connected in a tree structure with 2 ^N-1 , 2 ^N-2 , 2 ^N-3 , 4, and 2 switches.

As described above, the N-bit second decoder 153ab includes N-2 XOR decoders 731 and 732 corresponding to N-2 XOR groups, an XNOR decoder 740, And an XOR and XNOR decoder 750 for selecting and outputting one of the reference gamma voltages selected from the XOR and XNOR decoders.

In this case, in the N-2 XOR groups, each XOR group may include switches of a tree structure controlled by higher bits than Dx and switches of an XOR structure controlled by Dx and Dx + 1. Also, each XOR group may include switches of the XNOR structure controlled by lower bits than Dx and Dx.

The second decoder 153ab includes switches of a tree structure in which D2 of the first digital signal and one XNOR group in which three reference gamma voltages of D1 and D0 are XNOR are controlled by higher bits than D2, And switches of the XNOR structure controlled by D1, D0.

In the second decoder 153ab, all or some of the XOR groups may be configured as switches of the XOR structure and the XNOR group and other configurations may be composed of the switches of the tree structure. Alternatively, all or a part of the XNOR groups may be configured as the XNOR structure Even if only some of the above-described switches are selectively used, the number of transistors used as switches can be reduced, thereby reducing the area of the general second decoder have.

As shown in FIG. 8, the D1 ^ D0 (XOR) grouping decoder 731 corresponding to the first XOR group 711 includes six tree structure switches. On the other hand, the XOR corresponding to the first XOR group 711 and the XOR (01 " or " 10 ") of D1 ^ D0 are included in the XNOR decoder 750.

Similarly, the D2 D1 (XOR) grouping decoder 732 corresponding to the second XOR group 712 includes two switches of a tree structure. The XOR corresponding to the second XOR group 712 and the XNOR decoder 750 controlled by the four switches D1 and D0 of the D2 D1 (01 " or " 10 & Four switches of the structure.

The second decoder 153ab includes four switches of a tree structure in which D2 of the first digital signal and one XNOR group in which three reference gamma voltages of D1 and D0 are XNOR are controlled by higher bits than D2, , D2 and six switches of the XNOR structure controlled by D1, D0.

The second decoder 153ab shown in FIG. 9 has an advantage in that the connection is easy by changing the order selected by the second decoder 153ab shown in FIG. 8, and the number of transistors connected to each digital signal becomes more uniform have.

10 is a circuit diagram of a 5-bit first DAC of a DA conversion unit according to another embodiment.

As shown in FIG. 10, the D1 ^ D0 (XOR) grouping decoder 731 corresponding to the first XOR group 711 includes switches of fourteen tree structures. Meanwhile, the XOR corresponding to the first XOR group 711 and the XOR (D1 " 0 " or " 10 ") of D1 D0 are included in the XNOR decoder 750.

Similarly, the D2 D1 (XOR) grouping decoder 732 corresponding to the second XOR group 712 includes six switches of a tree structure. The XOR corresponding to the second XOR group 712 and the XNOR decoder 750 controlled by the four switches D1 and D0 of the D2 D1 (01 " or " 10 & Four switches of the structure.

The D3 D2 (XOR) grouping decoder 733 corresponding to the third XOR group 713 includes two switches of a tree structure. XOR corresponding to the second XOR group 712 and XNOR (01 " or " 10 ") of D3 D2 by the XNOR decoder 750 and XNOR Six switches of the structure.

The second decoder 153ab includes six switches of a tree structure in which D3, D2 of the first digital signal and one XNOR group in which three reference gamma voltages of D1 and D0 are XNOR are controlled by higher bits than D2, And six switches of the XNOR structure controlled by D2 and D1, D0.

11 is a configuration diagram of a first DAC of a general DA conversion unit.

As shown in FIG. 11A, when the first digital signal is 3 bits, for example, the first DAC 153a 'of the general DA converter is separately provided for selecting two from the nine reference gamma voltages Only two 3-bit decoders 153aa 'and 153ab' can be used without including the switch part of the 3-bit decoder. The two 3-bit decoders 153aa 'and 153ab' may be composed of switches in a tree structure. (2 ³⁺ 1) gamma reference voltages are required to implement only the 3-bit decoders 153aa ', 153ab' including the switches in the tree structure, two 3-bit decoders are used, (2 ^{3 + 1 -} 2) transistors are required.

In general, in order to implement the N-bit first 1DAC (2 ^N +1) of the gamma reference voltage is required, and two N-bit decoders are used, and one N-bit decoder (2 ^{N + 1} -2) of transistors need.

As shown in FIG. 11 (b), the first DAC 153a '' of another general DA converter, for example, when the first digital signal is 3 bits, selects two from the nine reference gamma voltages The first decoder 153aa '' for selecting the first selection voltage Vx by the upper two bits of the first digital signal and the second decoder 153aa '' for selecting the second selection voltage VY by the three bits of the first digital signal A third decoder 153ab '' for selecting three bits of the first selection voltage Vx and a third selection voltage Vx for switching the first voltage VH and the second voltage VL among the first selection voltage Vx and the second selection voltage VY, '') Can be used. At this time, the two decoders 153aa 'and 153ab' may be configured as switches of a tree structure.

In other words, the first decoder 153aa '' and the second decoder 153ab '' of the first DAC 153a '' of other general DA converters are connected to the switches of the tree structure as shown in FIG. 11 (b) The odd-numbered reference gamma voltage and the even-numbered reference gamma voltage are selected and the two reference gamma voltages selected using the most significant bit are used as the first voltage VH and the second voltage VH of the second DAC 153b, (VL).

N to the bit implement the 1DAC one N-1 bit decoder (153aa '') and one N-bit decoder (153ab '') uses one N-1 bit decoder (153aa '') is (2 ^N -2) transistors are required and one N-bit decoder 153ab '' requires ( ^{2N + 1} -2) transistors. Therefore, the first DAC 153a '' of the general DA conversion unit shown in FIG. 11 (b) has 2 ^N (all of the approximately DA converters 153a '') than the first DAC 153a ' 25%) of transistors can be used while achieving the same performance.

12 is a graph comparing the number of transistors according to the resolution (number of bits) of the second decoders of the general first DAC shown in FIG. 11 and the second decoders of the first DAC according to the embodiments of the present invention.

As described above, the number of transistors according to the resolution (number of bits) of the second decoder (Proposed in FIG. 12) of the first DAC according to the embodiments of the present invention decreases as the DAC resolution increases, Therefore, it is possible to use only about 60% of the transistors of the second decoder (ref1 and ref2 in FIG. 12) of the general first DAC shown in FIG. 11A at a low resolution of about 5 to 6 bits, It is possible to use only about 50% of the transistors of the second decoder (ref1 and ref2 in FIG. 12) of the general first DAC shown in FIG. 11 (a).

13 shows areas of a data driver according to a general data driver and embodiments.

13 (b) and 13 (c) when a 7-bit first DAC is implemented by the method of FIG. 8 and FIG. 9) and the general data driver 13A), it is possible to reduce the number of transistors of the digital-analog converter included in the data driver according to the above-described embodiments, thereby reducing the area of the digital-analog converter. As shown in FIG. 13, when the first digital signal is 7 bits and the first DAC is composed of the 6-bit first decoder and the 7-bit second decoder, the data driver (FIG. 13 (b) and c) can be reduced by about 44% from the area of a general data driver (Fig. 13 (a)).

According to the above-described embodiments, the area of the data driver can be reduced because the area of the digital-analog converter is reduced.

According to the embodiments described above, it is possible to reduce the number of transistors of the digital-analog converter and reduce the power consumption of the data driver.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

130: system board section 140: timing control section
150: Data driver 160:
170: Display panel DDATA: Color data signal
152: latch unit 153: DA conversion unit
154: gamma voltage generator 155: output circuit

Claims (12)

(2 ^N-1 +1) Based on the gamma voltages to the first digital signal D of the N-bit (N-1) based on the (N is a natural number greater than 2), D (N-2 ), ... A first digital-to-analog converter for converting D2, D1, D0 into a first voltage and a second voltage; And
And a second digital-to-analog converter for receiving the first and second voltages and outputting an analog signal to the second digital signal,
Wherein the first digital-to-
A first decoder controlled by an upper (N-1) bit of the first digital signal to output a first selection voltage of one of (2 ^N-1 ) reference gamma voltages;
N bits of the first digital signal and outputs the second selected voltage to the other one of the (2 ^N-1 + 1) reference gamma voltages, wherein Dx (x = 0 2) XOR groups in which 2 ^NX-2 reference gamma voltages are grouped, each XOR group having a larger number of bits than the D (x + 1) A second decoder including switches in a controlled tree structure, switches in an XOR structure controlled by Dx and D (x + 1)
And a switch unit for selectively outputting the first selection voltage and the second selection voltage to the first voltage and the second voltage. The method according to claim 1,
Wherein each XOR group includes switches of an XNOR structure controlled by lower bits than Dx and Dx. The method according to claim 1,
The second decoder includes one XNOR group in which three reference gamma voltages grouped by D (N-2) to D0 other than D (N-1), which is the most significant bit of the digital signal of the first digital signal, are XNOR A switch of a tree structure controlled by higher bits than D (N-2), and switches of an XNOR structure controlled by D (N-2) to D0. . (2 ^N-1 +1) Based on the gamma voltages to the first digital signal of N bits (D (N-1, based on the (N is a natural number larger than 2)), D (N- 2), ..., D2, D1, D0) into a first voltage and a second voltage; And
And a second digital-to-analog converter for receiving the first and second voltages and outputting an analog signal to the second digital signal,
Wherein the first digital-to-
A first decoder controlled by an upper (N-1) bit of the first digital signal to output a first selection voltage of one of (2 ^N-1 ) reference gamma voltages;
( ^N-1 ) -th reference digital gamma voltages, a second selection voltage is controlled by the first digital signal of N bits and the other of the ( ^2N-1 + 1) One of the XNOR groups in which the three reference gamma voltages D (N-2) to D0 except XNOR are grouped except D (N-1) is controlled by higher bits than D (N-2) , A second decoder including switches of the XNOR structure controlled by D (N-2) to D0,
And a switch unit for selectively outputting the first selection voltage and the second selection voltage to the first voltage and the second voltage. 5. The method of claim 4,
The second decoder outputs N-2 reference gamma voltages grouped by 2 ^NX-2 reference gamma voltages in which Dx (a natural number larger than x = 0 and smaller than N-2) of the first digital signal and X (X + Each XOR group in the XOR groups includes a switch of a tree structure controlled by upper bits than D (x + 1) and a switch of the XOR structure controlled by Dx and D (x + 1) Conversion section. 6. The method of claim 5,
Wherein each XOR group includes switches of an XNOR structure controlled by lower bits than Dx and Dx. A digital-analog converter for converting an M-bit digital signal including an N-bit first digital signal and a (MN) -bit second digital signal into an analog signal; And
And an output circuit for outputting the analog signal as an output signal,
(2 ^N-1 +1) Based on the gamma voltages to the first digital signal of N bits (D (N-1, based on the (N is a natural number larger than 2)), D (N- 2), ..., D2, D1, D0) into a first voltage and a second voltage; And
And a second digital-to-analog converter for receiving the first and second voltages and outputting an analog signal to the second digital signal,
Wherein the first digital-to-
A first decoder controlled by an upper (N-1) bit of the first digital signal to output a first selection voltage of one of (2 ^N-1 ) reference gamma voltages;
N bits of the first digital signal and outputs the second selected voltage to the other one of the (2 ^N-1 + 1) reference gamma voltages, wherein Dx (x = 0 2 XOR groups in which 2 ^NX-2 reference gamma voltages are grouped, where XOR is a natural number smaller than N-2 and XOR is DOR (x + 1) A second decoder including switches of a tree structure controlled by Dx and D (x + 1), switches of an XOR structure controlled by Dx and D (x + 1)
And a switch unit for selectively outputting the first selection voltage and the second selection voltage to the first voltage and the second voltage. 8. The method of claim 7,
Wherein each XOR group includes switches of an XNOR structure controlled by lower bits than Dx and Dx. 8. The method of claim 7,
Wherein the second decoder is one of the XNOR groups in which the three reference gamma voltages grouped by DN (N-2) to D0 except for the most significant bit D (N-1) of the first digital signal are XNOR, N-2), and switches of the XNOR structure controlled by D (N-2) to D0. A digital-analog converter for converting an M-bit digital signal including an N-bit first digital signal and a (MN) -bit second digital signal into an analog signal; And
And an output circuit for outputting the analog signal as an output signal,
(2 ^N-1 +1) Based on the gamma voltages to the first digital signal of N bits (D (N-1, based on the (N is a natural number larger than 2)), D (N- 2), ..., D2, D1, D0) into a first voltage and a second voltage; And
And a second digital-to-analog converter for receiving the first and second voltages and outputting an analog signal to the second digital signal,
Wherein the first digital-to-
A first decoder controlled by an upper (N-1) bit of the first digital signal to output a first selection voltage of one of (2 ^N-1 ) reference gamma voltages;
( ^N-1 ) -th reference digital gamma voltages, a second selection voltage is controlled by the first digital signal of N bits and the other of the ( ^2N-1 + 1) One of the XNOR groups in which the three reference gamma voltages D (N-2) to D0 except XNOR are grouped except D (N-1) is controlled by higher bits than D (N-2) , A second decoder including switches of the XNOR structure controlled by D (N-2) to D0,
And a switch unit for selectively outputting the first selection voltage and the second selection voltage to the first voltage and the second voltage. 11. The method of claim 10,
The second decoder outputs N-2 reference gamma voltages grouped by 2 ^NX-2 reference gamma voltages in which Dx (a natural number larger than x = 0 and smaller than N-2) of the first digital signal and X (X + Each XOR group in the XOR groups includes switches in a tree structure controlled by upper bits than D (x + 1) and switches in an XOR structure controlled by Dx and D (x + 1) . 12. The method of claim 11,
Wherein each XOR group includes switches of an XNOR structure controlled by lower bits than Dx and Dx.

Images