KR20060038112A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device for processing a data signal at high speed is disclosed.

The liquid crystal display of the present invention includes a digital-analog converter for converting a data signal into an analog data voltage, a data driver including a buffer unit for amplifying and outputting a current of the analog data voltage, and the first and second buffer units. And a controller configured to generate first and second clock signals for controlling the interval, wherein the buffer unit corrects the offset voltage in the first interval defined by the first and second clock signals, and the first and second clock signals. An output voltage equal to the analog data voltage is output in a second section defined by two clock signals.

Current amplifier, data driver, first clock signal, second clock signal

Description

Liquid crystal display device

1 is a block diagram showing a conventional liquid crystal display device.

FIG. 2 is a block diagram showing a detailed configuration of a data driver of the liquid crystal display of FIG.

FIG. 3 is a diagram illustrating a buffer unit of the data driver of FIG. 2. FIG.

4 is a diagram showing waveforms of first and second clock signals for correcting offset voltage Voffset.

5 is a circuit diagram illustrating a buffer unit for correcting an offset voltage Voffset.

FIG. 6A is a circuit diagram of a case where the buffer portion of FIG. 5 is one section. FIG.

FIG. 6B is a circuit diagram of a case where the buffer unit of FIG. 5 is in two sections. FIG.

7 is a circuit diagram illustrating a buffer unit provided at an output terminal of a data driver of a liquid crystal display according to the present invention.

FIG. 8A is a circuit diagram of a case where the buffer unit of FIG. 7 is one section. FIG.

FIG. 8B is a circuit diagram of a case where the buffer unit of FIG. 7 is divided into two sections. FIG.

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of implementing a high speed digital-to-analog converter (DAC).

Recently, flat panel display devices are in the spotlight. The flat panel display device includes a liquid crystal display (LCD), an electroluminescent display (ELD), a field emission display (FED), and a plasma display (PDP). The flat panel display device requires light weight, high brightness, high efficiency, high resolution, high speed response characteristics, low driving voltage, low power consumption, low cost, and full color display characteristics.

1 is a block diagram showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a plurality of gate lines GL0 to GLn and data lines DL1 to DLm, and a thin film transistor TFT formed on a pixel region defined by an intersection thereof. ) And a pixel electrode to display an image, a data driver 6 to supply a data voltage to data lines of the liquid crystal panel 2, and gate lines of the liquid crystal panel 2. A gate driver 4 for supplying scan signals for driving GL0 to GLn, a gamma voltage generator (not shown) for supplying a predetermined gamma voltage to the data driver 6, and the gate driver 4 And a timing controller 8 for generating control signals for controlling the data driver 6.

FIG. 2 is a block diagram illustrating a detailed configuration of a data driver of the liquid crystal display of FIG. 1.

As shown in FIG. 2, the data driver 6 includes a shift register array 18 for supplying sequential sampling signals, and a latch array 20 for sequentially latching and simultaneously outputting digital data signals in response to the sampling signals. ), A digital-to-analog conversion (hereinafter referred to as DAC) array 22 for converting a digital data signal from the latch array 20 into an analog data voltage, and an analog data voltage from the DAC array 22. And an output buffer array 30 that buffers and outputs the buffer. The data driver 6 subdivides the reference gamma voltage from the signal control unit 14 relaying the data control signals supplied from the timing controller 8 and the digital data signal, and a reference gamma voltage unit (not shown). A gamma voltage unit 16 is further provided to supply the DAC array 22.

3 is a diagram illustrating a buffer unit of the output buffer array of FIG. 2.

As shown in FIG. 3, the output buffer array 30 amplifies the current of the analog data voltage output from the DAC array 22. That is, each buffer unit of the output buffer array 30 is provided with a current amplifier 5 for amplifying the current of the analog data voltage Vin. To this end, a high current value is set in advance in the current amplifier 5. Accordingly, the analog data voltage Vin input to each of the buffer units is amplified by the high current of the current amplifier 5 and output.

The analog data voltage Vin is supplied to the inverting (−) input terminal of the current amplifier 5. At this time, the non-inverting (+) input terminal of the current amplifier 5 is grounded to ground. Therefore, the analog data voltage Vin is amplified to a high current value and output as it is to the output voltage Vout. However, in practice, a large number of transistors exist in the current amplifier 5, and the offset voltage Voffset is generated by the transistor. Therefore, the output voltage Vout is output as a value obtained by adding the offset voltage Voffset to the analog data voltage Vin. Therefore, as the output voltage Vout becomes larger than the analog data voltage Vout, the gray scale is changed so that the desired gray scale expression is impossible. For this purpose, a current amplifier for generating the first and second clock signals inverted from each other in the timing controller 8 and correcting the offset voltage Voffset included in the output voltage Vout has been recently proposed.

4 is a diagram illustrating waveforms of first and second clock signals for correcting an offset voltage Voffset.

As shown in FIG. 4, first and second clock signals are generated in the timing controller 8 so that the first and second clock signals CK1 and CK2 have opposite values. When the first clock signal CK1 has a high value, the second clock signal CK2 has a low value and the first clock signal CK1 has a low value. In this case, the second clock signal CK2 has a high value. In addition, each of the first and second clock signals CK1 and CK2 is alternately inverted every predetermined period. When the first clock signal CK1 has a high value and the second clock signal CK2 has a low value is referred to as Phase1 (hereinafter referred to as "first period"). When the first clock signal CK1 has a low value and the second clock signal CK2 has a high value, it is referred to as Phase2 (second section; hereinafter referred to as second section).

5 is a circuit diagram illustrating a buffer unit for correcting an offset voltage Voffset.                         

As illustrated in FIG. 5, a first switch SW1 is connected between an input terminal to which the analog data voltage Vin of the buffer unit is input and the first node nd1. A capacitor C is connected between the first node nd1 and a second node nd2, and the second node nd2 is connected to an inverting (−) input terminal of the current amplifier 15. A third clock signal switch SW3 is connected between the first node nd1 and an output terminal of the current amplifier 15, and a second clock signal switch SW2 is connected between the second node nd2 and the output terminal. Connected. The reference voltage Vref is supplied to the non-inverting (+) input terminal of the current amplifier 15. The first and second clock signal switches SW1 and SW2 are opened and closed by the first clock signal CK1, and the third clock signal switch SW3 is opened and closed by the second clock signal CK2. .

FIG. 6A is a circuit diagram illustrating a case where the buffer unit of FIG. 5 is in a first section.

As shown in FIG. 6A, in the first period, the first and second clock signal switches are turned on by the first clock signal CK1 having a high value, and the third clock signal switch has a low value. It is turned off by the second clock signal CK2.

The analog data voltage Vin converted by the digital-to-analog converter DAC (not shown) of the data driver 6 is supplied to the second node nd2 through the capacitor C. The reference voltage Vref is supplied to the non-inverting (+) input terminal of the current amplifier 15. In this case, the voltage V (−) applied to the non-inverting (−) input terminal of the current amplifier 15 is set to be equal to the reference voltage Vref. The V (−) voltage is designated as a virtual ground voltage V.G having a constant voltage value. The reference voltage Vref and the offset voltage Voffset are fixed voltages. The offset voltage Voffset is generated by transistors present in the current amplifier 15. At this time, it is set to be applied to the inverting (-) input terminal of the current amplifier 15 as a voltage value obtained by adding the offset voltage Voffset and the reference voltage Vref. As a result, the output voltage Vout of the current amplifier 15 is turned on by the first and second clock signal switches SW1 and SW2 so that a value obtained by adding the reference voltage Vref and the offset voltage Voffset is output. .

The data analog voltage Vin and the output voltage Vout of the current amplifier 15 should be equal. Therefore, the output voltage Vout should not be different from the data analog voltage Vin of the current amplifier 15. The current amplifier 15 serves to equalize the values of the data analog voltage Vin and the output voltage Vout and to amplify only the current. However, since the reference voltage Vref and the offset voltage Voffset voltage are output as the output voltage Vout of the current amplifier 15, the offset voltage Voffset should be corrected. When the above description is expressed as a formula, it is as follows.

FIG. 6B is a circuit diagram illustrating the case where the buffer unit of FIG. 5 is divided into two sections. FIG.

As illustrated in FIG. 6B, in the second period, the first and second clock signal switches SW1 and SW2 are turned off by the first clock signal CK1, and the third clock signal switch SW3 is turned off. ) Is turned on by the second clock signal CK2 to have a high value.                         

The output terminal of the current amplifier 15 provided in the buffer unit is fed back to the input terminal of the current amplifier 15. In the case of Phase1, the current amplifier 15 is driven in Phase2 to correct the offset voltage Voffset included in the output voltage Vout of the current amplifier 15.

The output voltage Vout of the current amplifier 15 driven in Phase 2 is expressed as follows.

In the case of the phase 1, the voltage Vc charged in the capacitor C of the current amplifier 15 is inverted (−) of the current amplifier 15 at the analog data voltage Vin of the current amplifier 15. It is equal to minus the voltage (V (-)) applied to the input terminal. Herein, the voltage V (-) applied to the inverting (-) input terminal means a virtual ground voltage V.G. Accordingly, when the output voltage Vout of the current amplifier 15 is driven in Phase 1, the analog voltage from which the offset voltage Voffset has been removed by driving the current amplifier 15 with the generated offset voltage Voffset in Phase 2 is generated. It becomes equal to the data voltage Vin.

According to the first and second clock signals having different signal values, the current amplifiers may include first to third clock signal switches SW1 to SW3 corresponding to the first and second clock signals CK1 and CK2. By turning on / off, the output voltage Vout equal to the analog data voltage of the current amplifier 15 may be output.

However, the analog data voltage Vin input to the current amplifier 15 varies depending on the gray scale. The analog data voltage Vin and the output voltage Vout of the current amplifier must be the same through the first and second steps of correcting the offset voltage Voffset generated by the transistors in the current amplifier. After the process of eliminating the offset voltage Voffset, the analog data voltage Vin and the output voltage Vout of the current amplifier become the same. The analog data voltage converted into a voltage value due to the digital-analog converter present inside the data driver is input to the current amplifier with other values. Each time, the first and second intervals for correcting the offset voltage (Voffset) generated by the numerous transistors present in the current amplifier must be passed. In other words, conventionally, each time an analog data voltage Vin is input, a continuous process of the first section and the second section is required. Accordingly, in the process of processing data at high speed, the process of correcting the offset voltage Voffset of the current amplifier slows down processing of the data. Therefore, it is difficult to process data at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display which generates an output voltage corresponding to an input voltage which changes at high speed by quickly correcting an offset voltage generated by a current amplifier located at an output terminal of a data driver.

According to a preferred embodiment of the present invention, there is provided a digital-analog converter for converting a data signal into an analog data voltage, a data driver including a buffer unit for amplifying and outputting a current of the analog data voltage, and the buffer unit. A control unit for generating first and second clock signals for controlling the first and second periods, the buffer unit correcting an offset voltage in a first period defined by the first and second clock signals, The present invention relates to a liquid crystal display device which outputs an output voltage equal to the analog data voltage in a second section defined by the first and second clock signals.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

7 is a circuit diagram illustrating a buffer unit provided at an output terminal of a data driver of a liquid crystal display according to the present invention.

The liquid crystal display and the data driver have been described in detail above, and further description thereof will be omitted for convenience of description.

As illustrated in FIG. 7, an analog data voltage Vin output from a digital-to-analog converter (DAC) (not shown) for converting a digital data signal existing in the data driver into an analog data voltage is stored in the buffer unit 100. It is supplied to the input terminal of the current amplifier 105 provided in. In the current amplifier 105 of the present invention, a second resistor R2 is connected to the first node nd1, and a first resistor R1 is connected between the first node nd1 and the second node nd2. It is. An output terminal of the second node nd2 and the current amplifier 105 is connected, and a third clock signal switch SW3 is connected between the first node nd1 and the third node nd3, The first clock signal switch SW1 is connected between the second node nd2 and the fourth node nd4, and the capacitor C is connected between the third node nd3 and the fourth node nd4. ) Is connected, and a second clock signal switch SW2 is connected between the third node nd3 and the fifth node nd5. A non-inverting (+) input terminal of the current amplifier 105 and a reference voltage Vref are connected to the fifth node nd5. The reference voltage Vref is supplied to the non-inverting (+) input terminal of the current amplifier 105 through the fifth node nd5. The inverting (-) input terminal of the current amplifier 105 has a voltage VG obtained by adding the reference voltage Vref and the offset voltage Voffset to correct the offset voltage Voffset generated by the current amplifier 15. Is set to be.

First and second clock signals are generated in a timing controller (not shown) of the liquid crystal display according to the present invention. Therefore, when the first clock signal is high, the second clock signal is low, the first clock signal is low, and the second clock signal is high. The first interval is when the first clock signal is high and the second clock signal is low. The second interval is when the first clock signal is low and the second clock signal is high. It is called a section. The second section means a section that is multiplied by a plurality of times of the first section. The first clock signal controls opening and closing of the first and second clock signal switches SW1 and SW2, and the second clock signal controls opening and closing of the third clock signal switch SW3.

FIG. 8A is a circuit diagram illustrating a case where the buffer unit of FIG. 7 is a first section.

As shown in FIG. 8A, when the first clock signal is High and the second clock signal is Phase1, the current amplifier 105 includes the first and second clock signal switches SW1, SW2 is turned on and the third clock signal switch SW3 is turned off. The reference voltage Vref is supplied to the non-inverting (+) input terminal of the current amplifier 105. At this time, the reference voltage Vref is also applied to the third node nd3. The voltage V (−) applied to the inverting (−) input terminal of the current amplifier 105 is equal to the output voltage Vout of the current amplifier 105. The V (−) voltage means a virtual ground V.G having a constant voltage value. In this case, the virtual ground voltage V.G is always applied with a value obtained by adding the reference voltage and the offset voltage Voffset generated in the current amplifier. If this is expressed as an expression, it appears as follows.

At this time, the voltage Vc applied to the capacitor C connected to the inverting (−) input terminal of the current amplifier 105 is obtained as follows.

That is, the voltage Vc charged in the capacitor C is the voltage V applied to the inverting (-) input terminal to the reference voltage Vref supplied to the non-inverting (+) input terminal of the current amplifier 105. It means minus (-)). In this case, the output voltage Vout of the current amplifier 105 includes an offset voltage Voffset generated by a number of transistors existing in the current amplifier 105 as shown in the above equation. Therefore, the current amplifier 105 is driven to Phase 2 to correct the offset voltage Voffset.                     

8B is a circuit diagram illustrating a case where the current amplifier of FIG. 7 is Phase2.

값이 충전된다. 그리고 상기 전류증폭기(105)에서 A로 도시된 블록부분을 이용해서 상기 전류증폭기(105)의 출력전압(Vout)을 구하면 다음과 같다. 이때, 상기 제 1 저항(R1)과 제 2 저항(R2)은 직렬로 연결되어 있어서, 똑같은 전류가 흐른다. As shown in FIG. 8B, when the first clock signal is low and the second clock signal is Phase2, the current amplifier 105 switches the first and second clock signal switches. (SW1, SW2) are turned off, and the third clock signal switch SW3 is turned on. In this case, a reference voltage Vref is applied to the non-inverting (+) input terminal of the current amplifier 105, and the output voltage Vout of the current amplifier 105 is the current through the first resistor R1. It is fed back to the first node nd1 of the amplifier 105. In the capacitor C of the current amplifier 105, as obtained in the case of Phase 1,

The value is filled. The output voltage Vout of the current amplifier 105 is obtained by using the block portion shown by A in the current amplifier 105 as follows. At this time, since the first resistor R1 and the second resistor R2 are connected in series, the same current flows.

Accordingly, the output voltage Vout of the current amplifier 105 is analog data voltage Vin converted to a voltage value by a digital-to-analog converter (not shown) existing in the data driver, and a reference voltage Vref. And the first and second resistors R1 and R2. The analog data voltage Vin and the output voltage Vout should be the same. This is because the current amplifier 105 serves to equalize the input voltage Vin and the output voltage Vout and to amplify the current. Therefore, in order to output the output voltage Vout equal to the analog data voltage Vin of the current amplifier 105 in the above-mentioned equation, the reference voltage Vref and the first and second resistors satisfying the above formula are set. Accordingly, the analog data voltage Vin, which is always variable, may be supplied to the input terminal of the current amplifier 105, and the output voltage Vout of the current amplifier 105 that is equal to the analog data voltage Vin may be output. . Accordingly, as the analog data voltage Vin is input to the input terminal of the current amplifier 105 included in the buffer unit, the current amplifier 105 is continuously driven in the second section.

As described above, in the case where the first clock signal is low and the second clock signal is a second period in which the second clock signal is high, the current amplifier provided with the analog data voltage Vin, which changes to various values, is provided in the buffer unit. When supplied to the input terminal of the output voltage (Vout) of the current amplifier corresponding to the output.

As described above, according to the liquid crystal display device according to the present invention, by first driving to the first section to correct the offset voltage (Voffset) and then driving to the second section, by performing the offset correction only once, high-speed driving is possible. As a result, the offset voltage Voffset is removed for a certain period to process the data signal at high speed.

Claims (6)

A data driver including a digital-analog converter for converting a data signal into an analog data voltage, and a buffer unit for amplifying and outputting a current of the analog data voltage; A control unit for generating first and second clock signals for controlling the buffer unit in first and second periods; The buffer unit compensates for an offset voltage in a first section defined by the first and second clock signals, and outputs an output voltage equal to the analog data voltage in a second section defined by the first and second clock signals. And a liquid crystal display device for outputting. The method of claim 1, The length of the second section has a multiple of the first section. The method of claim 1, And the first and second clock signals have inverted signals. The method of claim 1, The buffer unit, A current amplifier for amplifying the current, a first resistor connected between the first node and the second node, a second resistor connected between the analog data voltage and the first node, and between the third node and the fourth node. A connected capacitor, a third clock signal switch connected between the first node and the third node, a first clock signal switch connected between the second node and the fourth node, the third node and a fifth node. And a second clock signal switch connected therebetween. The method of claim 4, wherein And the first and second clock signal switches are turned on in the first section, and the third clock signal switch is turned off, so that an offset voltage is corrected at an output terminal of the current amplifier. The method of claim 4, wherein Wherein the first and second clock signal switches are turned off and the third clock signal switch is turned on in the second section, so that the analog data voltage with amplified current is output from an output terminal of the current amplifier. Display.

Images