JP2009168842A - Reference voltage generating circuit, driver, electrooptical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit which can generate a gradation voltage, adaptive to display characteristics of a variety of electrooptical panels, having high versatility, a driver, an electrooptical device, and electronic equipment. <P>SOLUTION: The reference voltage generating circuit includes a ladder resistance circuit 10, a selecting circuit 100, and a sample holding unit 200. The ladder resistance circuit 10 has a plurality of resistances RA0 to RAn connected in series between a first power supply voltage VGMH and a second power supply voltage VGML, and outputs first to n-th divided voltages divided by the RA0 to RAn. The selecting circuit 100 selects an output voltage VQA corresponding to one of the first to n-th divided voltages that the ladder resistance circuit 10 outputs based upon a selection signal DA and outputs the output voltage. The sample holding unit 200 has a plurality of sample holding circuits, which sample and hold the output voltage VQA of the selecting circuit 100. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a reference voltage generation circuit, a driver, an electro-optical device, an electronic apparatus, and the like.

  Conventionally, as a liquid crystal panel (electro-optical panel in a broad sense) used for electronic devices such as mobile phones and projectors, an active matrix method using a simple matrix type liquid crystal panel and a switch element such as a thin film transistor (Thin Film Transistor) LCD panels are known.

  In recent years, liquid crystal panel image displays used in mobile phones, projectors, and the like are required to accurately reproduce the tone expression inherent in the video.

  In general, video signals for image display are subjected to gradation correction in accordance with the display characteristics of the liquid crystal panel, and in order to achieve accurate color expression, the gradation that is optimal for the display characteristics of the liquid crystal panel is used. It is required to perform correction (γ correction).

  This gradation correction is performed by a gradation voltage generation circuit (reference voltage generation circuit in a broad sense). The gradation voltage generation circuit generates a gradation voltage corresponding to the display characteristics of the liquid crystal panel. Such a gradation voltage generation circuit can be constituted by a ladder resistor, and voltages at both ends of each resistance circuit constituting the ladder resistor are output as a multi-value gradation voltage corresponding to the gradation data.

  By the way, there are various products for liquid crystal panels, and each product has different display characteristics. In addition, liquid crystal panels of the same product have a plurality of display characteristics. For example, although polarity inversion driving is performed to prevent deterioration of the liquid crystal, the display characteristics (γ curve) in the positive electrode period and the display characteristics (γ curve) in the negative electrode period are not the same. For example, when the display of the liquid crystal panel is composed of three primary colors of red, blue and green, the display characteristics of red, blue and green are different, and the display characteristics in the positive electrode period and the display characteristics in the negative electrode period of each color are not the same. Absent.

  In order to realize gradation correction corresponding to such various display characteristics, for example, Japanese Patent Application Laid-Open No. 2004-228867 discloses a gradation resistance using a ladder resistance circuit including a variable resistance circuit whose resistance value is variably controlled based on a control signal. A gradation voltage generation circuit having a configuration capable of adjusting the voltage is disclosed.

However, in the technique disclosed in Patent Document 1, since the resistance value of the variable resistance circuit can be changed only within a range set in advance at the time of design, there is a problem that the range in which the gradation voltage can be adjusted is limited. was there.
JP 2003-233354 A

  According to some embodiments of the present invention, it is possible to provide a reference voltage generation circuit, a driver, an electro-optical device, and an electronic apparatus that can generate a highly versatile grayscale voltage corresponding to display characteristics of various electro-optical panels.

  The present invention is a reference voltage generation circuit that generates at least one reference voltage, and includes a first power supply line to which a first power supply voltage is supplied and a second power supply line to which a second power supply voltage is supplied. A ladder resistor circuit that outputs first to n-th (n is a natural number) divided voltage divided by the resistors of the plurality of resistors in series. A selection circuit configured to select and output an output voltage corresponding to any one of the first to n-th divided voltages output from the ladder resistor circuit based on a selection signal; Each sample and hold circuit of the sample and hold circuit includes a sample and hold unit that samples and holds the output voltage of the selection circuit.

  In the present invention, the ladder resistor circuit outputs first to nth divided voltages divided by a plurality of resistors connected in series between the first power supply voltage and the second power supply voltage. The selection circuit selects and outputs an output voltage corresponding to any one of the first to n-th divided voltages output from the ladder resistor circuit based on the selection signal. In the sample hold unit, each sample hold circuit of the plurality of sample hold circuits samples and holds the output voltage of the selection circuit. In this way, each of the plurality of sample-and-hold circuits samples and holds any one of the first to n-th divided voltages output from the ladder resistor circuit. A free combination and order can be selected from the n-th divided voltage, and a highly versatile reference voltage can be generated.

  According to the present invention, the selection circuit includes first to nth switch elements provided between an output node and first to nth input nodes, respectively, and the first to nth input nodes. Are supplied with the first to n-th divided voltages output from the ladder resistor circuit, and any one of the first to n-th switch elements is turned on based on the selection signal. Then, the output voltage may be output to the output node of the selection circuit by turning off another switch element.

  According to such a selection circuit, a selected one of the first to nth switch elements is turned on, and the other switch elements are turned off, so that the first to nth outputs from the ladder resistor circuit. The output voltage corresponding to any one of the divided voltages can be selected and output based on the selection signal.

  In the present invention, the selection circuit outputs the first to first outputs from the ladder resistor circuit in each output period of first to m-th output periods (m is a natural number) based on the selection signal. An output voltage corresponding to one of the n divided voltages is selected and output, and the sample and hold unit includes first to m-th sample and hold circuits as the plurality of sample and hold circuits, and the at least one reference M reference voltages including the first to mth reference voltages are output as voltages, and the i th sample (i is an integer of 1 ≦ i ≦ m) of the first to mth sample hold circuits. The hold circuit samples the output voltage of the selection circuit in the i-th output period of the first to m-th output periods based on the sampling instruction signal, and outputs the first to m-th reference voltage. I's You may hold and output as a reference voltage.

  As described above, the selection circuit selects and outputs one of the first to n-th divided voltages output from the ladder resistor circuit in each of the first to m-th output periods based on the selection signal. The i-th sample hold circuit of the sample hold unit samples the output voltage of the selection circuit in the i-th output period based on the sampling instruction signal, and holds and outputs the output voltage as the i-th reference voltage. Thus, the first to mth reference voltages can be selected in any combination and order from the first to nth divided voltages output from the ladder resistor circuit. In particular, for example, when the relationship of n> m is established, the degree of freedom of adjustment of the reference voltage is further increased.

  In the present invention, the sample hold unit includes a first sample hold unit and a second sample hold unit, and the first sample hold unit includes a first period and a second period which are periodically repeated. In the first period, the output voltage of the selection circuit is sampled, and in the subsequent second period, the voltage sampled in the first period is held, and the second sample hold unit May sample the output voltage of the selection circuit in the second period, and hold the voltage sampled in the second period in the subsequent first period.

  According to such a sample and hold unit, the first sample and hold unit samples the output voltage of the selection circuit in the first period, and holds the voltage sampled in the first period in the second period. A first set of reference voltages is generated. The second sample and hold unit samples the output voltage of the selection circuit in the second period, and holds the voltage sampled in the second period in the first period, so that it is independent of the first set of reference voltages. A second set of reference voltages of the combination is generated. In this way, two independent sets of reference voltages can be generated alternately.

  In the present invention, the sample hold unit selects and outputs a voltage held by the second sample hold unit based on an output instruction signal in the first period, and in the second period, Based on the output instruction signal, a voltage held by the first sample hold unit may be selected and output.

  As described above, in the first period, the voltage held by the second sample-and-hold unit is selected and output based on the output instruction signal, and in the second period, the first sample-hold is based on the output instruction signal. By selecting and outputting the voltage held by the unit, two sets of reference voltages can be alternately output.

  In the present invention, each sample and hold circuit of the plurality of sample and hold circuits may be a flip-around type sample and hold circuit.

  By using such a flip-around type sample-and-hold circuit, the sample-and-hold circuit can be provided with a voltage sample-and-hold function, and so-called offset free can be realized, so that a highly accurate reference voltage with little variation can be generated.

  According to the present invention, each sample and hold circuit is provided between an operational amplifier, a first input terminal of the operational amplifier and an input node of each sample and hold circuit, and an input voltage of the input node in a sampling period. And an output voltage corresponding to the charge accumulated in the sampling capacitor during the sampling period may be output during the hold period.

  In this way, by sampling the input voltage to the input node in the sampling period in the sampling capacitor and performing the flip-around operation of the sampling capacitor, the output voltage corresponding to the charge accumulated in the sampling capacitor is obtained. Output is possible in the hold period.

  According to the present invention, each sample and hold circuit has an operational amplifier whose analog reference power supply voltage is set to the second input terminal thereof, the input node of each sample and hold circuit, and the first input terminal of the operational amplifier. A sampling switch element and a sampling capacitor provided between the operational amplifier, a feedback switch element provided between an output terminal of the operational amplifier and the first input terminal, the sampling switch element, and the And a flip-around switch element provided between a connection node between the sampling capacitor and the output terminal of the operational amplifier.

  In this way, sampling of the input voltage to the sampling capacitor can be realized using the sampling switch element and the feedback switch element, and the flip-around operation of the sampling capacitor can be realized using the flip-around switch element. .

  In the present invention, in the sampling period, the sampling switch element and the feedback switch element are turned on, the flip-around switch element is turned off, and the sampling capacitor is input to the input node. The charge corresponding to the voltage is accumulated, and in the hold period, the sampling switch element and the feedback switch element are turned off, and the flip-around switch element is turned on. An output voltage corresponding to the charge accumulated in the sampling capacitor may be output during the sampling period.

  In this manner, when the sampling switch element and the feedback switch element are turned on during the sampling period, charges corresponding to the input voltage can be stored in the sampling capacitor using the imaginary short function of the operational amplifier. Further, by turning on the flip-around switch element in the hold period, an output voltage corresponding to the charge accumulated in the sampling capacitor can be output to the output node of each sample hold circuit.

  According to the present invention, the at least one reference voltage is a gradation voltage used for gradation expression of an electro-optical device, and the first sample-and-hold unit performs the selection in the first period. The output voltage of the circuit is sampled, and in the subsequent second period, the output voltage of the selection circuit sampled in the first period is held and output as a negative gradation voltage, and the second sample is output. The holding unit samples the output voltage of the selection circuit in the second period, and outputs the output voltage of the selection circuit sampled in the second period in the subsequent first period. You may hold and output as a voltage.

  In this way, the positive gradation voltage and the negative gradation voltage used for gradation expression of the electro-optical device can be generated and output alternately. Further, since the positive gradation voltage and the negative gradation voltage can be selected in any combination and order from the first to nth divided voltages output by the ladder resistor, a highly versatile gradation voltage can be selected. Can be generated.

  According to the present invention, the at least one reference voltage is a gradation voltage used for gradation expression of the electro-optical device, and the first period and the second period are the first time, respectively. The second divided period and the second divided period, the second first period and the second period are the third divided period and the fourth divided period, respectively, and the third first period And the second period is a fifth divided period and a sixth divided period, respectively, and the first sample and hold unit samples the output voltage of the selection circuit in the first divided period, In the subsequent second divided period, the output voltage of the selection circuit sampled in the first divided period is held and output as the positive polarity gradation voltage of the second color component, and the third divided period is output. In the output circuit of the selection circuit In the subsequent fourth divided period, the output voltage of the selection circuit sampled in the third divided period is held and output as a negative gradation voltage of the first color component, and the second divided period is output. In the fifth divided period, the output voltage of the selection circuit is sampled, and in the subsequent sixth divided period, the output voltage of the selection circuit sampled in the fifth divided period is used as the negative electrode of the third color component. The second sample-and-hold unit samples the output voltage of the selection circuit in the second divided period, and then outputs the second voltage in the third divided period. The output voltage of the selection circuit sampled in the two divided periods is held and output as the positive polarity gradation voltage of the third color component, and is output in the fourth divided period. The output voltage of the selection circuit is sampled, and in the subsequent fifth division period, the output voltage of the selection circuit sampled in the fourth division period is used as the negative gradation voltage of the second color component. The output of the selection circuit sampled in the sixth division period, sampled in the sixth division period, and sampled in the sixth division period in the subsequent first division period The voltage may be held and output as the positive gradation voltage of the first color component.

  According to this configuration, the first to third color component positive polarity gradation voltages and the first to third color component negative polarity gradation voltages used for gradation expression in the electro-optical device are generated. It can be output periodically. Further, since each gradation voltage can be selected in any combination and order from the first to n-th divided voltages output from the ladder resistor, a highly versatile gradation voltage can be generated.

  In the present invention, the first half period of the first divided period and the first half period of the fourth divided period are in a polarity inversion period of the counter voltage supplied to the counter electrode of the electro-optical panel included in the electro-optical device. It may be set.

  In this way, the first half period of the first and fourth divided periods after polarity inversion can be used as a stabilization period of the counter voltage supplied to the counter electrode of the electro-optical panel.

  The present invention also relates to a driver including any of the above reference voltage generation circuits.

  The present invention also relates to an electro-optical device including the driver described above.

  The present invention also relates to an electronic apparatus including the electro-optical device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. FIG. 1 shows a configuration example of a driver 480 (integrated circuit device) including a reference voltage generation circuit (grayscale voltage generation circuit, γ correction circuit) according to the present embodiment and an electro-optical device 600 including the driver 480. Show. Note that the driver 480 and the electro-optical device 600 of the present embodiment are not limited to the configuration in FIG. 1, and some of the components (for example, a scanning driver, a memory, etc.) are omitted or other components are added. Various modifications are possible.

  Hereinafter, an example in which the reference voltage generation circuit of the present invention is applied to the gradation voltage generation circuit 430 of the driver 480 will be described. However, the reference voltage generation circuit of the present invention can be applied to a circuit that switches a plurality of combinations of reference voltages and a circuit that outputs the reference voltages in a time-sharing manner in addition to the gradation voltage generation circuit 430. For example, the present invention can be applied to the power supply circuit 490 of the driver 480.

  The electro-optical panel 400 (electro-optical device) includes a plurality of data lines (for example, source lines), a plurality of scanning lines (for example, gate lines), and a plurality of pixels specified by the data lines and the scanning lines. Then, the display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element or an EL element) in each pixel region. The electro-optical panel 400 (display panel in a narrow sense) can be configured by an active matrix type panel using switch elements such as TFTs and TFDs. The electro-optical panel may be a panel other than the active matrix system, or may be a panel using a light emitting element such as an organic EL (Electro Luminescence) or an inorganic EL other than the liquid crystal panel.

  The driver 480 (integrated circuit device) generates a data signal (voltage signal, current signal) supplied to the data line of the electro-optical panel and a scanning signal supplied to the scanning line.

  The memory 420 (display data RAM) stores image data. The memory cell array 422 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). A row address decoder 424 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 422. A column address decoder 426 (MPU column address decoder) performs a decoding process on the column address, and performs a selection process of a bit line of the memory cell array 422. The write / read circuit 428 (MPU write / read circuit) performs image data write processing to the memory cell array 422 and image data read processing from the memory cell array 422.

  The logic circuit 440 (driver logic circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 440 can be formed by automatic placement and routing such as a gate array (G / A).

  The control circuit 442 generates various control signals and controls the entire apparatus. Specifically, gradation adjustment data (γ correction data) for adjusting gradation characteristics (γ characteristics) is output to the gradation voltage generation circuit 430, or power supply voltage is supplied to the power supply circuit 490. Outputs power adjustment data for adjustment. Further, it controls write / read processing to the memory using the row address decoder 424, the column address decoder 426, and the write / read circuit 428.

  The display timing control circuit 444 generates various control signals for controlling the display timing, and controls reading of image data from the memory 420 to the electro-optical panel side. The host (MPU) interface circuit 446 realizes a host interface that generates an internal pulse for each access from the host and accesses the memory 420. The RGB interface circuit 448 implements an RGB interface that writes moving image RGB data to the memory 420 using a dot clock. Note that only one of the host interface circuit 446 and the RGB interface circuit 448 may be provided.

  The data driver 450 is a circuit that generates a data signal (voltage, current) for driving a data line of the electro-optical panel 400 (electro-optical device). Specifically, the data driver 450 receives image data (grayscale data, display data) from the memory 420 and receives a plurality of (for example, 256 levels) grayscale voltages (reference voltages) from the grayscale voltage generation circuit 430. Then, a voltage (data voltage) corresponding to the image data (gradation data) is selected from the plurality of gradation voltages, and is output to the data line of the electro-optical panel 400.

  The scanning driver 470 is a circuit that generates a scanning signal for driving the scanning lines of the electro-optical panel 400. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by level-converting the shifted signal is output as a scanning signal (scanning voltage) to each scanning line of the electro-optical panel. To do. The scan driver 470 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 490 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. The voltage obtained by the boosting is supplied to the data driver 450, the scan driver 470, the gradation voltage generation circuit 430, and the like.

  The gradation voltage generation circuit 430 is a circuit that generates gradation voltages and supplies them to the data driver 450. Specifically, the gradation voltage generation circuit 430 can include a ladder resistor circuit that divides a resistance between a high potential side voltage and a low potential side voltage and outputs a gradation voltage to a resistance division node. In addition, a gradation register unit in which gradation adjustment data is written, a gradation voltage setting circuit that variably sets (controls) the gradation voltage output to the resistance division node based on the written gradation adjustment data, and the like. Can be included.

2. Next, a specific example of the gradation voltage generation circuit 430 to which the reference voltage generation circuit of the present invention is applied will be described. The gradation voltage generation circuit 430 is a circuit for generating a gradation voltage to be used for gradation expression of the electro-optical device 600. In this case, the reference voltage generation circuit of the present invention generates a plurality of gradation voltages as at least one reference voltage. However, the reference voltage generation circuit of the present invention may be any circuit that generates at least one reference voltage, and may generate, for example, one reference voltage.

  First, a gradation voltage generation circuit according to a comparative example of this embodiment will be described with reference to FIG. The gradation voltage generation circuit of this comparative example is configured by a ladder resistor circuit 50 including a plurality of variable resistor circuits R0 to Rs + 1 (s is an integer of 0 or more). The variable resistance circuits R0 to Rs + 1 are connected in series between the power supply voltage VGMH and the power supply voltage VGML, and the gradation voltages V0 to Vs are output by dividing the resistance between these power supply voltages. Thereby, the gradation voltages V0 to Vs that match the display characteristics can be generated.

  However, the gradation voltage generation circuit of this comparative example has a problem that the range in which the gradation voltage can be adjusted is narrow because the resistance values of the variable resistance circuits R0 to Rs + 1 can be set only within a predetermined range. It was.

  FIG. 3 shows a configuration example of the gradation voltage generation circuit (reference voltage generation circuit, γ correction circuit) of the present embodiment that can solve the above problems. The gradation voltage generation circuit includes a ladder resistor circuit 10, a selection circuit 100, and a sample hold unit 200. It should be noted that modifications such as omitting some of these components (for example, a selection circuit) and adding other components are possible.

  The ladder resistor circuit 10 includes a plurality of resistors RA0 to RAn (n is an integer of 2 or more). The resistors RA0 to RAn are connected in series between a power supply line VHL that is a first power supply line and a power supply line VLL that is a second power supply line. The power supply line VHL is supplied with the power supply voltage VGMH on the high voltage side, which is the first power supply voltage, and the power supply line VLL is supplied with the power supply voltage VGML on the low voltage side, which is the second power supply voltage. Note that a power supply voltage on the low voltage side may be supplied to the power supply line VHL, and a power supply voltage on the high voltage side may be supplied to the power supply line VLL. Further, the resistors RA0 to RAn can be constituted by poly resistors, for example.

  Resistors RA0 to RAn divide the voltage between power supply voltage VGMH and power supply voltage VGML by resistance. The resistance-divided voltage is output as first to nth divided voltages VA1 to VAn.

  For example, a node between the resistors RA0 and RA1 is a node NA1, a node between the resistors RA1 and RA2 is a node NA2, and a node between the resistors RAj-1 and RAj is a node NAj (j is 1 ≦ 1). j ≦ n). Then, the divided voltage VA1 is output to the node NA1, the divided voltage VA2 is output to the node NA2, and the divided voltage VAj is output to the node NAj.

  The selection circuit 100 receives the divided voltages VA1 to VAn output from the ladder resistor circuit 10 and outputs an output voltage VQA. Based on the selection signal DA, any one of the divided voltages VA1 to VAn is selected and output as the output voltage VQA.

  Specifically, the divided voltages VA1 to VAn are input from the nodes NA1 to NAn, the selection signal DA is received from a control circuit (not shown), and one of the divided voltages VA1 to VAn is selected, and the corresponding output voltage VQA is set to the node NQA. Output to.

  The sample hold unit 200 includes a plurality of sample hold circuits 240-1 to 240-N. In the sample hold circuits 240-1 to 240 -N, each sample hold circuit samples and holds the output voltage VQA of the selection circuit 100, and generates a gradation voltage (reference voltage in a broad sense).

  Specifically, in the sample hold circuits 240-1 to 240-N, each sample hold circuit independently samples and holds the output voltage VQA. For example, the output voltage VQA is one of the divided voltages VA1 to VAn of the ladder resistor circuit 10, and each sample and hold circuit outputs a voltage corresponding to the held output voltage VQA as a gradation voltage.

  For example, any one of the sample and hold circuits 240-1 to 240-N samples one of the divided voltages VA1 to VAn, and the other one of the sample and hold circuits 240-1 to 240-N includes the divided voltages VA1 to VA1. The other one of VAn can be sampled. Each sample and hold circuit outputs gradation voltages having different voltages.

  Here, the sample-and-hold circuits 240-1 to 240-N can also sample-hold in response to the sampling instruction signal DB shown in FIG. For example, when the sampling instruction signal DB is a signal for instructing the sampling of the sample hold circuit 240-1, the sample hold circuit 240-1 samples the output voltage VQA of the selection circuit 100.

  In the sample and hold circuits 240-1 to 240-N, a plurality of sample and hold circuits may sample and hold the same divided voltage selected as the output voltage VQA and output the gradation voltage of the same voltage. . Further, the sample hold circuits 240-1 to 240-N may sample and hold the output voltage VQA in a time division manner and output a gradation voltage.

  For example, since the gradation voltage generation circuit of the comparative example of the present embodiment shown in FIG. 2 outputs a gradation voltage using a ladder resistor composed of a variable resistor, the adjustment range of the gradation voltage is a variable resistance. There is a problem that it is limited by the adjustment range.

  In this regard, according to the grayscale voltage generation circuit of the present embodiment shown in FIG. 3, grayscale voltages can be generated from the divided voltages VA1 to VAn of the ladder resistor circuit 10 in any combination and order. The voltage can be adjusted in a wide range. That is, even if various products are used for the electro-optical panel 400, an optimum gradation voltage can be generated for each product. For example, the ladder resistor circuit is configured to divide and output the power supply voltage to n = 256, and select N = 64 gradation voltages that match the gradation characteristics of the electro-optic panel from among them. Thus, a highly versatile gradation voltage generation circuit can be realized.

3. Selection Circuit FIG. 4 shows a specific example of the selection circuit 100. The selection circuit 100 includes first to nth switch elements SA1 to SAn. The first to nth switch elements SA1 to SAn are provided between the output node NQA and the first to nth input nodes NA1 to NAn, respectively.

  Specifically, one end of the switch element SA1 is connected to the input node NA1, and the other end is connected to the output node NQA. In addition, one end of the switch element SA2 is connected to the input node NA2, and the other end is connected to the output node NQA. Similarly, one end of the switch element SAj (j is an integer satisfying 1 ≦ j ≦ n) is connected to the input node NAj, and the other end is connected to the output node NQA.

  Further, the divided voltages VA1 to VAn from the ladder resistor circuit 10 of FIG. 3 are input to the input nodes NA1 to NAn, respectively.

  The selection circuit 100 receives, for example, a multi-bit selection signal DA [0: q] (q is an integer of 1 or more) from a control circuit (switch signal generation circuit) (not shown), and the selection circuit 100 One of the switch elements is turned on, and the other switch element is turned off. As a result, the output voltage VQA is output to the output node NQA of the selection circuit 100.

  Specifically, when the switch element SA1 is selected by the selection signal DA [0: q], the switch element SA1 is turned on and the switch elements SA2 to SAn are turned off, so that the divided voltage VA1 becomes the output voltage VQA. Is output as When the switch element SA2 is selected by the selection signal DA [0: q], the switch element SA2 is turned on and the switch element SA1 and the switch elements SA3 to SAn are turned off, so that the divided voltage VA2 is output as the output voltage. Output as VQA. Similarly, when the switch element SAj is selected by the selection signal DA [0: q], the switch element SAj is turned on, and the switch elements SA1 to SAj−1 and the switch elements SAj + 1 to SAn are turned off, so that the division is performed. Voltage VAj is output as output voltage VQA.

  Here, the selection circuit 100 may output the output voltage VQA selected from the divided voltages VA1 to VAn in a time division manner. For example, in each output period of the first to m-th (m is a natural number) output periods, the output voltage VQA corresponding to any one of the divided voltages VA1 to VAn may be selected and output. Further, the switch elements SA1 to SAn can be configured by CMOS transistors such as transfer gates, for example.

  According to the configuration of FIG. 4, it is possible to realize a selection circuit that arbitrarily selects any one of the divided voltages VA <b> 1 to VAn output from the ladder resistor circuit 10.

4). Sample Hold Unit FIGS. 5 and 7 show first and second configuration examples of the sample hold unit 200. The sample hold unit of FIG. 5 can sample and hold an arbitrary m number of gradation voltages from the n divided voltages output from the ladder resistor circuit 10 and output them. However, the first configuration example of FIG. That is, the gradation voltage cannot be output during the sampling period. Therefore, in the second configuration example of FIG. 7, this problem is solved by causing the two sample hold units to alternately perform sample hold and output.

  Here, the sample and hold unit 200 in FIGS. 5 and 7 can sample and hold m (p in FIG. 7) grayscale voltages that are smaller than n from n divided voltages, for example. it can. Specifically, for example, 64 gradation voltages from 256 divided voltages can be sampled and held. In this case, since the interval between the 256 divided voltages is sufficiently smaller than the interval necessary for the 64 gradation voltages, a gradation voltage close to the display characteristics of the liquid crystal panel can be selected with high accuracy and easily.

  However, the number of n divided voltages may be smaller than the number of m (p) gradation voltages, and the number of n divided voltages may be the same as the number of m (p) gradation voltages. .

4.1. First Configuration Example First, the first configuration example in FIG. 5 will be described. Although only the configuration example of the sample hold unit 200 is shown in FIG. 5, the sample hold unit 200 samples the output voltage VQA from the selection circuit 100 of FIG. First, the operation of the selection circuit 100 in the first configuration example will be described.

  The selection circuit 100 in FIG. 3 receives the selection signal DA [0: q] and outputs the output voltage VQA in each of the output periods of the first to m-th (m is a natural number) output periods. The output voltage VQA corresponds to one of the first to nth divided voltages VA1 to VAn output by the ladder resistor circuit 10 in each output period. The output voltage VQA to be output can output a different voltage in each output period among the first to m-th output periods.

  Note that the selection circuit 100 may select and output the same divided voltage as the output voltage VQA in some or all of the first to m-th output periods.

  As shown in FIG. 5, the sample hold unit 200 includes first to mth sample hold circuits SHA1 to SHAm. These sample and hold circuits SHA1 to SHAm output m grayscale voltages as at least one grayscale voltage. The m gradation voltages are composed of first to mth gradation voltages VGA1 to VGAm. Here, the i-th sample-and-hold circuit SHAi (i is an integer of 1 ≦ i ≦ m) samples the output voltage VQA of the selection circuit 100 in the i-th output period. Sampling is performed based on, for example, a multi-bit sampling instruction signal DB [0: r] (r is an integer of 1 or more) from a control circuit (not shown). The sampled output voltage VQA is held and output as the i-th gradation voltage VGAi.

  Specifically, the output voltage VQA of the selection circuit 100 is output to the output node NQA and input to the sample hold circuits SHA1 to SAHm. The sample hold circuits SHA1 to SAHm output the gradation voltages VGA1 to VGAm to the nodes NGA1 to NGAm. Also, the sampling instruction signal DB [0: r] is input to the sample hold circuits SHA1 to SHAm.

  Next, an operation example when the first to m-th output periods are periodically repeated will be described with reference to FIG.

  As shown in A1 of FIG. 6, in the first output period TQ1, the selection signal DA [0: q] instructs the selection circuit 100 to select the divided voltage VA1. Thereby, the selection circuit 100 selects the divided voltage VA1 from among the divided voltages VA1 to VAn output from the ladder resistor 10, and outputs the divided voltage VA1 as the output voltage VQA as indicated by A2.

  Then, as indicated by A3 in FIG. 6, in the first output period TQ1, the sampling instruction signal DB [0: r] instructs the sample hold circuit SHA1 to perform sampling. Thereby, as shown by A4 in FIG. 6, the sample hold circuit SHA1 samples the divided voltage VA1 output from the selection circuit 100. Sampling is performed in the sampling period TSA1 corresponding to the output period TQ1. As shown in A5 of FIG. 6, in the hold period THA1 corresponding to the output periods TQ2 to TQm, the sample hold circuit SHA1 holds the divided voltage VA1 sampled in the output period TQ1, and outputs it as the gradation voltage VGA1. To do.

  Further, in the second output period TQ2, the selection circuit 100 selects the divided voltage VA3 according to the selection signal DA [0: q] shown in A6 of FIG. 6, and sets the output voltage VQA as shown in A7 of FIG. The divided voltage VA3 is output. Then, the sample hold circuit SHA2 samples the divided voltage VA3 in the sampling period TSA2 corresponding to the output period TQ2 as indicated by A9 in FIG. 6 in accordance with the sampling instruction signal DB [0: r] indicated in A8 in FIG. Then, as shown at A10 in FIG. 6, in the hold period THA2 corresponding to the output periods TQ3 to TQm and the next output period TQ1, the sample hold circuit SHA1 holds the divided voltage VA1 sampled in the output period TQ1, Output as the gradation voltage VGA2.

  Thereafter, in general, in the i-th output period TQi, the selection circuit 100 selects the divided voltage VAh according to the selection signal DA [0: q] shown in A11, and outputs the divided voltage VAh as the output voltage VQA as shown in A12. To do. Then, the sample hold circuit SHAi samples the divided voltage VAh in the sampling period TSAi corresponding to the output period TQi as shown in A14, in accordance with the sampling instruction signal DB [0: r] shown in A13. As shown in A15, in the hold period THAi corresponding to the output periods TQi + 1 to TQm and the next output periods TQ1 to TQi-1, the sample hold circuit SHAi holds the divided voltage VAh sampled in the output period TQi, and Output as regulated voltage VGAi.

  The sample hold unit 200 in FIG. 5 repeats the same operation until the output period TQm indicated by A16 in FIG. 6 to complete one operation in the output periods TQ1 to TQm. As a result, the sample hold unit 200 generates and outputs m grayscale voltages VGA1 to VGAm. In FIG. 6, the output periods TQ1 to TQm are periodically repeated, and the sample hold unit 200 of FIG. 5 periodically generates and outputs the gradation voltages VGA1 to VGAm.

  Note that the grayscale voltages VGA1 to VGAm periodically generated by the sample hold unit 200 may be different for each period or the same for each period. Further, for example, a set of a plurality of gradation voltages can be periodically generated. Further, the gradation voltages VGA1 to VGAm may be different from each other, or part or all of them may be the same voltage.

  Further, the sample hold circuits SHA1 to SHAm may output the held voltage as the gradation voltage in the entire hold period THA1 to THAm, or may output only in a part of the period. Good. Further, all the outputs of the sample hold circuits SHA1 to SHAm may be used as gradation voltages, or a part of them may be used as gradation voltages. For example, one part may be output as the gradation voltage of the data driver 450, and the other part may be used instead of the output of the power supply circuit 490.

  As described above, according to the first configuration example of FIG. 5, it is possible to realize the sample hold unit 200 that samples and holds an arbitrary m number of gradation voltages from the n divided voltages output from the ladder resistor circuit 10. In addition, according to the first configuration example, since the gradation voltage can be adjusted in a wide range, it is possible to provide a highly versatile gradation voltage generation circuit that can correspond to the display characteristics of various liquid crystal panels. .

  However, in the first configuration example, since the sample voltage hold and output of the gradation voltage is performed by one set of sample hold units 200, the gradation voltage is not changed while the sample hold circuits SHA1 to SHAm are sampling. There is a problem that it cannot be output.

  For example, it is assumed that the gradation voltage generation circuit of this embodiment supplies 64 gradation gradation voltages to the data driver 450 in FIG. 1 every horizontal period (for example, positive gradation voltage and negative gradation voltage). . Then, the gradation voltage generation circuit performs 64 sampling operations in one horizontal period, and the period during which the data driver 450 can use the gradation voltage is shortened by the period required for the 64 sampling operations. There is a problem of becoming.

  Therefore, in the second configuration example shown in FIG. 7, two sample hold units are provided, and during the period during which one sample hold unit is sampling, the gradation voltage is output to the other to solve this problem. ing.

4.2. Second Configuration Example Hereinafter, a second configuration example of the sample and hold unit illustrated in FIG. 7 will be described. The sample hold unit 200 includes a first sample hold unit 220-1 and a second sample hold unit 220-2. There are a first period and a second period, which are repeated periodically. The first sample hold unit 220-1 samples the output voltage VGA of the selection circuit 100 in the first period. Then, in the subsequent second period, the voltage sampled in the first period is held. The second sample hold unit 220-2 samples the output voltage VGA of the selection circuit 100 in the second period. In the subsequent first period, the voltage sampled in the first period is held.

  7 receives an output instruction signal POL from a control circuit (not shown) or the like, and outputs gradation voltages VGB1 to VGBp. At this time, in the first period, the voltage held by the second sample hold unit is selected and output, and in the second period, the voltage held by the first sample hold unit is selected and output. .

  Specifically, the first sample hold unit 220-1 includes sample hold circuits SHB11 to SHB1p, and the second sample hold unit 220-2 includes sample hold circuits SHB21 to SHB2p. The output voltage VQA of the selection circuit 100 is input to the sample hold circuits SHB11 to SHB1p and SHB21 to SHB2p. The sample hold circuits SHB11 to SHB1p and SHB21 to SHB2p output the gradation voltages VGB1 to VGBp to the nodes NGB1 to NGBp.

  In the first period, the sample hold circuits SHB11 to SHB1p receive the sampling instruction signal DB [0: r] and sample the output VQA of the selection circuit 100, and the sample hold circuits SHB21 to SHB2p in the second period. Hold the sampled voltage. In the second period, the sample hold circuits SHB21 to SHB2p receive the sampling instruction signal DB [0: r] and sample the output VQA of the selection circuit 100, and the sample hold circuits SHB11 to SHB1p are in the first period. Hold the sampled voltage. Then, the output instruction signal POL selects the sample hold unit that is holding and outputs the held voltage as the gradation voltages VGB1 to VGBp.

  As described above, by providing two sample-and-hold units, one sample-and-hold unit generates p grayscale voltages, and in the meantime, another sample-and-hold unit receives the other p grayscale voltages. It can be output. For example, two sets of p gray scale voltages can be alternately generated and output, or a plurality of sets of three or more sets of p gray scale voltages can be periodically generated and output.

  Next, the operation of this embodiment will be specifically described with reference to FIG. As shown in B1 of FIG. 8, the first sample hold unit 220-1 samples the output voltage VGA of the selection circuit 100 in the sampling period TSB1 corresponding to the first period TB1. This sampling is performed based on the sampling instruction signal DB [0: r]. As shown in B2 of FIG. 8, the voltage sampled in the sampling period TSB1 shown in B1 of FIG. 8 is held in the hold period THB1 corresponding to the second period TB2. Here, as indicated by B3 in FIG. 8, the output instruction signal POL is at the second signal level PB2. As a result, as indicated by B4 in FIG. 8, the voltage held by the first sample hold unit 220-1 is output as the gradation voltages VGB1 to VGBp.

  Subsequently, as illustrated in B5 of FIG. 8, the second sample hold unit 220-2 samples the output voltage VGA of the selection circuit 100 in the sampling period TSB2 corresponding to the second period TB2. This sampling is performed based on the sampling instruction signal DB [0: r]. As shown in B6 of FIG. 8, the voltage sampled in the sampling period TSB2 shown in B5 of FIG. 8 is held in the hold period THB2 corresponding to the second period TB1. Here, as indicated by B7 in FIG. 8, the output instruction signal POL is at the first signal level PB1. As a result, as indicated by B8 in FIG. 8, the voltage held by the second sample hold unit 220-2 is output as the gradation voltages VGB1 to VGBp.

  At this time, the first sample hold unit 220-1 and the second sample hold unit 220-2 perform the same sample hold operation as the sample hold unit 200 in FIG. 5 in the respective sampling periods TSB1 and TSB2. Here, a sample hold operation in the sampling period TSB1 of the first sample hold unit 220-1 will be described as an example.

  As shown in B9 of FIG. 8, in the first output period TQB1, the selection circuit 100 selects, for example, the divided voltage VA1 according to the selection signal DA [0: q], and outputs the divided voltage VA1 as the output voltage VQA. Then, the sample hold circuit SHB11 samples the divided voltage VA1 according to the sampling instruction signal DB [0: r] indicated by B10 in FIG. In the output periods TQB2 to TQBm, the sample hold circuit SHB11 holds the divided voltage VA1 sampled in the output period TQB1. Similarly, in the output periods TQB2 to TQBp, the sample hold circuits SHB12 to SHB1p can perform the sample hold operation to generate p grayscale voltages.

  Thus, according to the second configuration example of FIG. 7, a plurality of sets of gradation voltages can be repeatedly output. Further, while one of the two sample hold units outputs the gray scale voltage, the other sample hold unit can sample the gray scale voltage. Thus, since the two sample hold units alternately output the gradation voltage, the first configuration example of FIG. 5 solves the problem that the gradation voltage could not be output during the sampling period.

5. Positive and negative independent and RGB positive and negative independent gradation voltages By the way, in the liquid crystal panel which is a typical electro-optical panel 400, the display characteristics are different depending on the positive polarity and the negative polarity in polarity inversion. In order to correct, a gradation voltage suitable for the display characteristics of each polarity is necessary. If the gradation voltage generation circuit of this embodiment is applied in such a case, gradation voltages suitable for the display characteristics of each polarity can be output as a plurality of sets of gradation voltages. Accordingly, in the following, with reference to FIGS. 9 and 10, as a specific application example of the gradation voltage generation circuit of the present embodiment, an operation when applied to the electro-optical device 600 that performs polarity inversion every one horizontal period. explain.

5.1. Positive / Negative Independent Grayscale Voltage First, an operation example shown in FIG. 9 will be described. FIG. 9 shows a case where a positive gradation voltage and a negative gradation voltage are alternately output as a plurality of sets of gradation voltages every horizontal period. In this operation example, the positive gradation voltage is output corresponding to the output of the second sample hold unit indicated by B4 in FIG. 8, and the output of the first sample hold unit indicated by B8 of FIG. A negative gradation voltage is output.

  Specifically, the first period TE1 and the second period TE2 in FIG. 9 correspond to TB1 and TB2 in FIG. 8, and each corresponds to one horizontal period of the electro-optical device 600. Further, TQE1 to TQE64 in FIG. 9 correspond to TQB1 to TQBp in FIG. 8, and VGE1 to VGE64 in FIG. 9 correspond to VGB1 to VGBp in FIG. Also, PE1 and PE2 in FIG. 9 correspond to PB1 and PB2 in FIG. 8, and TSE1, TSE2, THE1, and THE2 in FIG. 9 correspond to TSB1, TSB2, THB1, and THB2 in FIG.

  Then, as indicated by E1 in FIG. 9, in the first period TE1, the first sample hold unit 220-1 samples the output voltage VQA of the selection circuit 100. Next, as shown in E2 of FIG. 9, in the subsequent second period TE2, the output voltage VQA of the selection circuit 100 sampled in the first period TE1 is held, and as shown in E3 of FIG. Output as gradation voltage. Then, as indicated by E4 in FIG. 9, in the second period TE2, the second sample hold unit 220-2 samples the output voltage VQA of the selection circuit 100. Next, as shown in E5 of FIG. 9, in the subsequent first period TE1, the output voltage VQA of the selection circuit 100 sampled in the second period TE2 is held, and as shown in E6 of FIG. Output as gradation voltage.

  As described above, according to the gradation voltage generation circuit of the present embodiment, the positive gradation voltage and the negative gradation voltage can be alternately output every horizontal period.

5.2. However, in recent years, for example, an image display of a projector or a mobile phone has been required to express excellent color tone, and independent gradation correction only for positive and negative may not be sufficient. Therefore, in order to realize more accurate gradation correction, it is necessary to perform independent gradation correction for each color component of the image display. Therefore, as an example in which the gradation voltage generation circuit of the present embodiment is applied to such gradation correction using FIG. 10, the case where it is applied to the electro-optical device 600 that performs RGB independent and positive / negative independent gradation correction is described. An operation example will be described.

  In this example of operation, the positive electrode R (positive color gradation voltage of the first color component), the positive electrode G (positive color gradation voltage of the second color component), the positive electrode B (third color component of the third color component) in one horizontal period. Output the gradation voltage for the positive electrode). Then, in the next one horizontal period, negative electrode R (negative color gradation voltage of the first color component), negative electrode G (negative color gradation voltage of the second color component), negative electrode B (negative electrode of the third color component) Output gradation voltage). These horizontal periods are repeated alternately.

  Specifically, the first divided period TF1 and the second divided period TF2 in FIG. 10 are the first first period and the second period, and the third divided period TF3 and the fourth divided period. TF4 is the second first period and the second period, and the fifth divided period TF5 and the sixth divided period TF6 are the third first period and the second period. These first period and second period correspond to the period TB1 and the period TB2 in FIG. Further, PF1 and PF2 in FIG. 10 correspond to PB1 and PB2 in FIG. Further, the positive electrode R, the positive electrode B, and the negative electrode G in FIG. 10 correspond to the output of the second sample hold unit in FIG. 8, and the positive electrode G, the negative electrode R, and the negative electrode B in FIG. 10 are the first sample in FIG. Corresponds to the output of the hold unit.

  Then, as indicated by F1 in FIG. 10, the first sample hold unit 220-1 samples the output voltage VQA of the selection circuit 100 in the divided period TF1. Next, as shown in F2 of FIG. 10, in the subsequent divided period TF2, the output voltage VQA of the selection circuit 100 sampled in the divided period TF1 is held and output as the positive electrode G as shown in F3 of FIG. Then, as indicated by F4 in FIG. 10, the second sample hold unit 220-2 samples the output voltage VQA of the selection circuit 100 in the divided period TF2. Next, as shown in F5 of FIG. 10, in the subsequent divided period TF3, the output voltage VQA of the selection circuit 100 sampled in the divided period TF2 is held and output as the positive electrode B as shown in F6 of FIG.

  Similarly, the first sample hold unit 220-1 samples in the divided period TF3, holds in the subsequent divided period TF4, and outputs it as the negative electrode R. Next, the second sample hold unit 220-2 samples in the divided period TF4, holds in the subsequent divided period TF5, and outputs it as the negative electrode G. Next, the first sample hold unit 220-1 samples in the divided period TF5, holds in the subsequent divided period TF6, and outputs it as the negative electrode B. Next, the second sample hold unit 220-2 samples in the divided period TF6, holds in the subsequent divided period TF1, and outputs it as the positive electrode R.

  As described above, according to the grayscale voltage generation circuit of the present embodiment, RGB independent positive polarity grayscale voltage and negative polarity grayscale voltage can be repeatedly output.

5.3. Setting of Polarity Reversal Period In the foregoing, the case where the gradation voltage generation circuit of this embodiment is applied to the electro-optical device 600 that performs the polarity reversal operation has been described. Here, in the electro-optical device 600, the polarity of the counter voltage VCOM supplied to the counter electrode of the electro-optical panel 400 is inverted when the polarity is inverted. For example, when the polarity is inverted every horizontal period, the counter voltage VCOM is also inverted every horizontal period. At this time, since the liquid crystal capacitance or the like parasitic to the counter electrode is charged according to the inversion of the counter voltage VCOM, the counter voltage VCOM is not set to a predetermined voltage until the charging is completed.

  Therefore, as shown in FIG. 10, in the gradation voltage generation circuit of this embodiment, polarity inversion periods TF11 and TF41 are set. This polarity inversion period is a polarity inversion period of the counter voltage VCOM supplied to the counter electrode of the electro-optical panel 400 included in the electro-optical device 600. Thus, it is possible to secure a period for setting the counter voltage VCOM to a predetermined voltage after polarity inversion. Here, the polarity inversion period TF11 is set to the first half period of the first division period TF1, and the polarity inversion period TE41 is set to the first half period of the fourth division period TF4.

  Specifically, the counter voltage VCOM is stabilized in the polarity inversion period TF11 that is the first half period of the divided period TF1, and the counter voltage VCOM is stabilized in the polarity inversion period TF41 that is the first half period of the divided period TF4. Other operations are the same as described above with reference to FIG.

  For example, the polarity inversion periods TF11 and TF41 can be used as the stable periods of the divided voltages VA1 to VAn. Taking the polarity inversion period TF11 as an example, when the power supply voltage supplied to the power supply line VHL of the ladder resistor circuit 10 and the power supply voltage supplied to the power supply line VLL are switched in accordance with the polarity inversion, the polarity inversion period TF11 is divided into voltages. It can be used as a stable period of VA1 to VAn. Then, when the first sample hold unit starts sampling after the polarity inversion period TF11 ends, stable divided voltages VA1 to VAn can be sampled. When the power supply voltage supplied to the power supply line VHL is the same as the power supply voltage supplied to the power supply line VLL regardless of polarity inversion, the first sample hold unit samples from the beginning of the divided period TF1 as shown in FIG. You can also.

  According to the gradation voltage generation circuit of the present embodiment, the polarity inversion period can be used as a period for stabilizing the counter voltage after the counter voltage supplied to the counter electrode of the electro-optical panel is inverted. Further, when the power supply voltage of the ladder resistor circuit 10 is switched in accordance with the polarity inversion, the polarity inversion periods TF11 and TF41 can be used as the stable periods of the divided voltages VA1 to VAn. Therefore, since the sample hold units 220-1 and 220-2 can sample the accurate divided voltages VA1 to VAn, it is possible to generate a highly accurate reference voltage.

6). Flip Around Sample Hold Circuit Each of the sample hold circuits 240-1 to 240-N shown in FIG. 3 and the like can be constituted by a so-called flip around sample hold circuit. Since each of these sample and hold circuits can be constituted by the same flip-around type sample and hold circuit, the sample and hold circuit 240-1 will be described below as a representative. Here, the flip-around sample-and-hold circuit, for example, samples the charge according to the input voltage in the sampling capacitor in the sampling period, performs the flip-around operation of the sampling capacitor in the hold period, and stores the accumulated charge Is a circuit that outputs a voltage corresponding to 1 to its output node.

  The flip-around sample-and-hold circuit will be described in more detail with reference to FIGS. 11A and 11B.

  For example, in FIGS. 11A and 11B, the sample and hold circuit 240-1 configured by a flip-around sample and hold circuit includes an operational amplifier OPC and a sampling capacitor CC.

  The sampling capacitor CC is provided between the inverting input terminal (first input terminal in a broad sense) of the operational amplifier OPC and the input node VIC of the sample hold circuit 240-1. As shown in FIG. 11A, the capacitor CC accumulates charges according to the input voltage VIC of the input node NIC during the sampling period.

  As shown in FIG. 11A, the output of the operational amplifier OPC is fed back to the node NEG at the inverting input terminal of the OPC during the sampling period. The non-inverting input terminal (second input terminal in a broad sense) of the operational amplifier OPC is set to the analog reference power supply voltage AGND. Therefore, the node NEG to which one end of the capacitor CC is connected is set to AGND by the imaginary short function of the operational amplifier OPC. As a result, charges corresponding to the input voltage VIC are accumulated in the capacitor CC.

  Here, the analog reference power supply voltage AGND is an arbitrary voltage from VDD to VSS when the high-potential-side power supply voltage of the operational amplifier is VDD and the low-potential-side power supply voltage is VSS. For example, the voltage is between VDD and VSS (intermediate), and in this case, it can be expressed as AGND = VSS + (VDD−VSS) / ML (ML> 1). For example, when ML = 2, it can be expressed as AGND = VSS + (VDD−VSS) / 2, and when VSS = 0, it can be expressed as AGND = VDD / 2.

  Next, as shown in FIG. 11B, in the hold period, the sample hold circuit 240-1 applies the output voltage VOC corresponding to the charge stored in the sampling capacitor CC in the sampling period to the output node NOC. Output. Specifically, an output voltage corresponding to the electric charge accumulated in the capacitor CC is obtained by performing a flip-around operation in which the other end of the capacitor CC connected to the node NEG is connected to the output terminal of the operational amplifier OPC. Outputs VOC.

  If the sample-and-hold circuit 240-1 is configured by the flip-around sample-and-hold circuit as described above, so-called offset free can be realized.

  For example, the offset voltage generated between the inverting input terminal and the non-inverting input terminal of the operational amplifier OPC is set to VOF, the analog reference power supply voltage AGND is temporarily set to 0 V to simplify the description, and the input voltage in the sampling period is set to VIC = Let VI be the capacitance value of the capacitor CC. Then, the charge Q accumulated in the sampling period is expressed by the following equation.

Q = (VI−VOF) × CS (1)
On the other hand, when the voltage of the node NEG in the hold period is VX and the output voltage is VOC, the charge Q ′ accumulated in the hold period is expressed by the following equation.

Q ′ = (VOC−VX) × CS (2)
When the amplification factor of the operational amplifier OPC is A, VOC is expressed by the following equation.

VOC = −A × (VX−VOF) (3)
Then, since Q = Q ′ by the law of charge conservation, the following equation is established.

(VI−VOF) × CS = (VOC−VX) × CS (4)
Therefore, according to the above equations (3) and (4),
VOC = VI-VOF + VX = VI-VOF + VOF-VOC / A
Is established. Therefore, the output voltage VOC of the sample and hold circuit 240-1 is expressed by the following equation.

VOC = {1 / (1 + 1 / A)} × VI (5)
As apparent from the above equation (5), the output voltage VOC of the sample and hold circuit 240-1 does not depend on the offset voltage VOF, and the offset can be canceled, so that offset free can be realized.

  For example, when the gradation voltage is output by the sample hold circuits 240-1 to 240 -N of the gradation voltage generation circuit 430, if the offset voltage VOF appears in the output voltage VOC, the gradation voltage is changed due to the variation in the output voltage VOC. An error occurs, and the display quality deteriorates.

  In this regard, if a flip-around type sample-and-hold circuit is used, offset can be canceled, so that variations in the output voltage VOC can be minimized. Therefore, a highly accurate gradation voltage with few errors can be supplied to the data driver 450, and display quality can be improved.

  Next, FIGS. 12A and 12B show a detailed configuration example of the sample-and-hold circuit 240-1 using a flip-around sample-and-hold circuit.

  12A and 12B includes an operational amplifier OPD, a sampling switch element SSD, a sampling capacitor CD, a feedback switch element SFD, and a flip-around switch element. Includes SAD. Further, it includes an output switch element SOD. It should be noted that modifications such as omitting some of these components or adding other components are possible. In addition, the switch elements SSD, SAD, SFD, and SOD can be configured by CMOS transistors such as transfer gates, for example.

  The analog reference power supply voltage AGND is set to the non-inverting input terminal (second input terminal) of the operational amplifier OPD. The sampling switch element SSD and the sampling capacitor CD are provided between the input node NID of the sample hold circuit 240-1 and the inverting input terminal (first input terminal) of the operational amplifier OPD. The feedback switch element SFD is provided between the output terminal of the operational amplifier OPD and the inverting input terminal of the OPD. The flip-around switch element SAD is provided between a connection node NS between the switch element SSD and the capacitor CD and an output terminal of the operational amplifier OPD.

  As shown in FIG. 12A, in the sampling period, the sampling switch element SSD and the feedback switch element SFD are turned on, and the flip-around switch element SAD is turned off. Thereby, the sampling operation of the flip-around sample-hold circuit described with reference to FIG.

  On the other hand, as shown in FIG. 12B, in the hold period, the sampling switch element SSD and the feedback switch element SFD are turned off, and the flip-around switch element SAD is turned on. Accordingly, the hold operation of the flip-around sample hold circuit described with reference to FIG. 12B can be realized.

  The output switch element SOD is provided between the output terminal of the operational amplifier OPD and the output node NOD of the sample hold circuit 240-1. Then, as shown in FIG. 12A, the output switch element SOD is turned off during the sampling period. As a result, the output of the sample hold circuit 240-1 becomes a high impedance state, and it is possible to prevent an uncertain voltage during the sampling period from being transmitted to the subsequent stage.

  On the other hand, as shown in FIG. 12B, the output switch element SOD is turned on in the hold period. Thereby, the voltage VOD which is the gradation voltage generated in the sampling period can be output.

  Here, the output switch element SOD can be turned on and off independently of the sample and hold operation of the flip-around sample and hold circuit. For example, the sample and hold circuits SHB11 to SHB1p and SHB21 to SHB2p of the sample and hold unit 200 described with reference to FIGS. 7 and 8 are formed of flip-around sample and hold circuits. Specifically, for example, the sample hold circuit SHB11 of FIG. 7 samples in the output period TQ1 of the period TB1 of FIG. 8 according to the sampling instruction signal DB [0: r], and holds the other output periods. However, the output switch element SOD is turned off in the period TB1 and turned on in the period TB2 in accordance with the output instruction signal POL which is a signal different from the sampling instruction signal DB [0: r].

  Next, the circuit operation of FIGS. 12A and 12B will be described with reference to FIG. 6, taking as an example the case where the sample and hold circuit SHA1 of FIG. 5 is formed of a flip-around type sample and hold circuit. The output voltage VGA of the selection circuit 100 is input to the node NID in FIGS. 12A and 12B.

  In the sampling sampling period TSA1 in FIG. 6, the switch control signal input to the sampling switch element SSD and the feedback switch element SFD becomes active (H level) in response to the sampling instruction signal DB [0: r]. The switch elements SSD and SFD are turned on. On the other hand, since the switch control signal input to the flip-around switch element SAD and the output switch element SOD becomes inactive (L level), the switch elements SAD and SOD are turned off.

  Further, in the hold period THA1 in FIG. 6, the switch control signal input to the switch elements SSD and SFD becomes inactive in response to the sampling instruction signal DB [0: r], so that the SSD and SFD are turned off. . On the other hand, since the switch control signal input to the switch elements SAD and SOD becomes active, SAD and SOD are turned on.

  Then, as shown by A4 in FIG. 6, the voltage VA1 of A2 is sampled in the sampling period TSA1, and charges corresponding to the voltage VA1 are accumulated in the sampling capacitor CD. At this time, since the switch element SOD is off, the voltage VOD is not output as a gradation voltage. Next, as indicated by A5, the voltage VA1, which is a voltage corresponding to the charge accumulated in the sampling capacitor CD in the hold period THA1, is held and output as the voltage VOD. Since the switch element SOD is on, the voltage VOD is output as a gradation voltage. Therefore, the voltage VA1 is output as the gradation voltage VGA1 in FIG.

7). Detailed Configuration Example Next, FIG. 13 shows a detailed configuration example of the present embodiment. The gradation voltage generation circuit of FIG. 13 can generate and output 64 gradation gradation voltages VGE1 to VGE64 from the output voltage of the 256 gradation ladder resistor circuit. The gradation voltage generation circuit includes a ladder resistor circuit 10, a selection circuit 100, and a sample hold unit 200 corresponding to FIG. In FIG. 13, the ladder resistance circuit 10 and the selection circuit 100 are combined into a ladder resistance circuit & selection circuit.

  The ladder resistor circuit 10 includes resistors RE0 to RE256 connected in series. The resistors RE0 to RE256 correspond to the resistors RA0 to RAn in FIG. 3 and divide the voltage between the power supply voltage VGMH and the power supply voltage VGML by resistance, and output 256 divided voltages.

  The selection circuit 100 includes switch elements SE1 to SE256 corresponding to the switch elements SA1 to SAn in FIG. The switch elements SE1 to SE256 are provided between a node between the resistors RE0 to RE256 and the output node NQE. For example, the switch element SE1 is provided between the node between the resistors RE0 and RE1 and the output node NQE, and the switch element SE2 is provided between the node between the resistors RE1 and RE2 and the output node NQE.

  The sample hold unit 200 includes a first sample hold unit 220-1 and a second sample hold unit 220-2. The first sample hold unit 220-1 includes sample hold circuits SHE101 to SHE164 corresponding to the sample hold circuits SHB11 to SHB1p of FIG. 7, and the second sample hold unit 220-2 includes the sample hold circuit SHB21 of FIG. Sample hold circuits SHE201 to SHE264 corresponding to .about.SHB2p are included.

  Each of these sample and hold circuits is constituted by the flip-around sample and hold circuit described with reference to FIG. For example, the sample hold circuit SHE101 corresponds to FIG. 12, and includes an operational amplifier OPE101, a sampling switch element SSE101, a sampling capacitor CE101, a feedback switch element SFE101, a flip-around switch element SAE101, and an output A switch element SOE101 is included.

  In response to the selection signal DA [0: q], the selection circuit 100 selects any one of the 256 voltages output from the ladder resistor circuit 10 and outputs the selected voltage as the voltage VQE. Next, the first sample hold unit 220-1 and the second sample hold unit 220-2 receive the sampling instruction signal DB [0: r], and sample and hold the voltage VQE. Then, in response to the output instruction signal POL, the gradation voltages VGE1 to VGE64 are output.

  Here, the specific operation of the grayscale voltage generation circuit of this embodiment will be described with reference to FIG. Note that the operation of the present embodiment is not limited to that shown in FIG. 9, and can be applied to the operation examples shown in FIGS. 8 and 10, for example.

  In the first period TE1 of FIG. 9, the first sample hold unit 220-1 samples the voltage VQE, the second sample hold unit 220-2 holds the voltage sampled in the second period TE2, Output as a positive polarity gradation voltage. On the other hand, in the second period TE2 of FIG. 9, the second sample hold unit 220-2 samples the voltage VQE, and the first sample hold unit 220-1 holds the voltage sampled in the first period TE1. And output as a negative gradation voltage.

  Specifically, for example, the sample hold circuit SHE101 operates as follows. Here, a voltage between the resistors RE1 and RE2 of the ladder resistor circuit 10 is a voltage VE2. In the period TQE1 of the period TE1, the selection circuit 100 receives the selection signal DA [0: q] and selects the voltage VE2. Then, in the selection circuit 100, the switch element SE2 is turned on, the other switch elements are turned off, and the voltage VE2 is output as the voltage VQE.

  Then, the sample hold circuit SHE101 samples the voltage VE2 in the period TQE1 of the period TE1, and holds the voltage VE2 in the remaining period of the period TE1 and the period TE2. Here, the switch element SOE101 receives the output instruction signal POL and is turned off in the period TE1 and turned on in the period TE2. Thereby, the sample hold circuit SHE101 outputs the voltage VE2 to be held as the gradation voltage VGE1 in the period TE2.

  Here, in the sample hold circuit SHE101, in the sampling period, the switch elements SSE101 and SFE101 are turned on, and the SAE101 is turned off. In the holding period, the switch elements SSE101 and SFE101 are turned off and the SAE 101 is turned on.

  Thus, according to the detailed configuration example shown in FIG. 13, the grayscale voltage generation circuit of the present embodiment can be realized.

8). Driver The gradation voltage output from the gradation voltage generation circuit of this embodiment is supplied to, for example, the data driver 450 shown in FIG. The data driver 450 supplies a data signal to the data line of the electro-optical panel 400 such as a liquid crystal panel. Hereinafter, a configuration example of the data driver 450 (source driver) will be described with reference to FIGS. 14 and 15.

  First, the configuration example of FIG. 14 will be described. 14 includes a D / A conversion circuit 452 and data line driving circuits 460-1 to 460-M. In FIG. 14, one D / A conversion circuit 452 is shared by a plurality of data line driving circuits 460-1 to 460-M (first to Mth data line driving circuits). A data line driving circuit or the like may be provided for each data line of the display panel, or the data line driving circuit may supply data signals to a plurality of data lines in a time division manner. A part or all of the data driver (integrated circuit device) may be integrally formed on the display panel.

  The D / A conversion circuit 452 (voltage generation circuit) receives gradation data DG (image data, display data) from the memory 420 of FIG. 1, for example. Then, the first and second gradation voltages VG1 and VG2 corresponding to the gradation data DG are output.

  Specifically, the D / A conversion circuit 452 receives the gradation data and applies the first and second gradation voltages VG1 and VG2 corresponding to the gradation data to each sampling in the first to Mth sampling periods. Output in time division during the period.

  The data line driving circuits 460-1 to 460-M include gradation generation amplifiers 462-1 to 462-M (GA1 to GAM). Each of these gradation generation amplifiers 462-1 to 462-M has first and second gradation voltages VG1 output from the D / A conversion circuit 452 in each sampling period of the first to Mth sampling periods. , VG2 is sampled to generate a gradation voltage between VG1 and VG2.

  Specifically, the gradation voltages VG1 and VG2 are adjacent gradation voltages (for example, VM1 and VM2, VM2 and VM3) in a plurality of gradation voltages (for example, VM1 to VM64) input to the D / A conversion circuit 452. become. Then, the gradation voltages VG1 and VG2 are sampled, and VG1, VG2, or (VG1 + VG2) / 2 is generated according to the gradation data DG.

  Note that the gradation voltage between VG1 and VG2 is not limited to (VG1 + VG2) / 2, and may be any voltage between VG1 and VG2, and may be more than one.

  Next, FIG. 15 shows a second configuration example of the data driver 450. In FIG. 15, the data line drive circuits 460-1 to 460 -M further include drive amplifiers 464-1 to 464 -M provided at the subsequent stage of the gradation generation amplifiers 462-1 to 462 -M. A modification in which the drive amplifiers 464-1 to 464-M are not provided is also possible.

  The drive amplifiers 464-1 to 464-M (DA1 to DAM) included in the data line drive circuits 460-1 to 460-M generate gradations in the drive amplifier sampling period after the first to Mth sampling periods. The output voltage of the amplifiers 462-1 to 462-M is sampled. In the drive amplifier hold period after the drive amplifier sampling period, the sampled output voltage is output.

  14 and 15, even if the D / A conversion circuit 452 outputs the first and second gradation voltages VG1 and VG2 in a time division manner, the gradation generation amplifiers 462-1 to 462-M. With this sampling function, it is possible to appropriately sample the voltage in each of the first to Mth sampling periods.

  For example, when the data line driving circuit is configured by an amplifier having no sample hold function, for example, a voltage follower type amplifier, it is necessary to provide a D / A conversion circuit having the same configuration for each data line driving circuit. Due to the layout area of the conversion circuit, the scale of the integrated circuit device is increased.

  In this regard, in the present embodiment, the D / A conversion circuit 452 is provided for the plurality of data line driving circuits 460-1 to 460 -M by providing the tone generation amplifier and the driving amplifier with the sample hold function. Can be shared. Therefore, the area occupied by the D / A conversion circuit 452 in the integrated circuit device can be reduced, and the integrated circuit device can be downsized.

  In addition, according to the data driver of this embodiment, the gradation voltage can be generated by the gradation generation amplifier 462, so that the number of gradation voltages generated by the gradation voltage generation circuit 430 in FIG. 1 can be reduced. As a result, the number of gradation voltage lines can be reduced, and the circuit scale of the D / A conversion circuit 452 can be reduced.

For example, when the gradation data DG is 8 bits and the number of gradations is 2 ⁸ = 256 gradations, the gradation voltage generation circuit 430 needs to generate 256 gradation voltages in the conventional method. The D / A conversion circuit 452 requires a selector group for selecting a gray scale voltage corresponding to the gray scale data DG from these 256 gray scale voltages. Therefore, the gradation voltage generation circuit 430 and the D / A conversion circuit 452 are increased in scale. In addition, since the number of gradation voltage lines is 256, the area occupied by the wiring region also increases.

  In this regard, according to the data driver of the present embodiment, the gradation voltage is generated by the gradation generation amplifier 462, so the gradation voltage generation circuit 430 only needs to generate, for example, 128 gradation voltages. The A conversion circuit 452 may be provided with a selector group for selecting a voltage from among these 128 gradation voltages. Therefore, the circuit scale can be greatly reduced as compared with the conventional method. Further, the number of gradation voltage lines can be reduced to 128, and the area of the wiring region can be greatly reduced. Actually, since the gradation generation amplifier 462 generates a voltage obtained by dividing the first and second gradation voltages VG1 and VG2, 128 + 1 = 129 gradation voltage lines are necessary in the above case.

  Further, according to the data driver of the present embodiment, the gradation voltage line is used for R (red), for example, when the gradation voltage generation circuit described with reference to FIG. 10 outputs the positive RGB and the negative RGB in time division. , G (green) and B (blue) can be shared in a time-sharing manner.

  Here, when 64 grayscale voltage lines are required for each of R, G, and B, the method of providing separate grayscale voltage lines for R, G, and B is 64. X3 = 192 grayscale voltage lines are required.

  In this respect, in the present embodiment, since one gradation voltage line is used for R, G, and B in a time-sharing manner, 64 gradation voltage lines can be used, and the gradation voltage is reduced. The wiring area of the line can be greatly reduced, and the area of the integrated circuit device can be reduced.

  Note that the data driver of the present invention may use a data line driving circuit configured with an amplifier that has a sample-hold function but does not generate a gradation voltage, or uses a data line driving circuit configured with a voltage follower type amplifier, A D / A conversion circuit may be provided for each data line driving circuit.

9. Electronic Device FIGS. 16A and 16B illustrate a configuration example of an electronic device or the electro-optical device 600 including the driver 480 of this embodiment. Note that various modifications may be made such as omitting some of the components shown in FIGS. 16A and 16B and adding other components (such as a camera, an operation unit, or a power supply). . The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  In FIGS. 16A and 16B, the host device 410 is, for example, an MPU or a baseband engine. The host device 410 controls the driver 480. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. In addition, the image processing controller 500 in FIG. 16B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 16A, a driver 480 having a built-in memory can be used. That is, in this case, the driver 480 once writes the image data from the host device 410 to the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 16B, a driver without a memory can be used as the driver 480. That is, in this case, the image data from the host device 410 is written in the built-in memory of the image processing controller 500. The driver 480 drives the electro-optical panel 400 under the control of the image processing controller 500.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, it is described at least once together with different terms having a broader meaning or the same meaning (first input terminal, second input terminal, reference voltage, first power supply voltage, second power supply voltage, etc.). The terms (inverted input terminal, non-inverted input terminal, gradation voltage, VGMH, VGML, etc.) can be replaced with the different terms in any part of the specification or the drawings. Further, the configuration and operation of a reference voltage generation circuit (grayscale voltage generation circuit), a selection circuit, a sample hold unit, a data line driving circuit, a grayscale generation amplifier, a driving amplifier, an electro-optical device, an electronic device, and the like are also described in this embodiment. However, the present invention is not limited to the above, and various modifications can be made.

2 is a configuration example of a driver and an electro-optical device according to the present embodiment. The comparative example of a gradation voltage generation circuit. 2 is a configuration example of a gradation voltage generation circuit according to the present embodiment. 2 shows a configuration example of a selection circuit. 1 is a first configuration example of a sample hold unit. The 1st signal waveform example for demonstrating the operation | movement of this embodiment. The 2nd structural example of a sample hold part. The 2nd example of a signal waveform for demonstrating operation | movement of this embodiment. The 3rd example of a signal waveform for demonstrating the operation | movement of this embodiment. The 4th example of a signal waveform for demonstrating operation | movement of this embodiment. 11A and 11B are explanatory diagrams of a flip-around type sample-and-hold circuit. 12A and 12B show detailed configuration examples of the flip-around sample-and-hold circuit. 3 shows a detailed configuration example of a gradation voltage generation circuit. The 1st modification of a data driver. The 2nd modification of a data driver. FIG. 16A and FIG. 16B are configuration examples of electronic devices.

Explanation of symbols

RA0 to RAn resistors, VA1 to VAn, first to nth divided voltages,
VGMH, VGML first and second power supply voltages, VHL, VLL first and second power supply lines,
Output voltage of VQA selection circuit, DA selection signal, SA1 to SAn switch element,
DB sampling instruction signal, VGA1 to VGAm reference voltage, POL output instruction signal,
CC sampling capacitor, OPC operational amplifier,
SSD sampling switch element, SFD feedback switch element,
SAD flip-around switch element, SOD output switch element,
TB1, TB2 first and second periods, TF1 to TF6, first to sixth divided periods,
TF11, TF41 polarity inversion period, TQ1 to TQm, the first to mth output periods,
10 ladder resistance circuit, 100 selection circuit, 200 sample hold section,
220-1 to 220-N sample hold circuit,
400 electro-optic panel, 410 host device, 420 memory,
422 memory cell array, 424 row address decoder,
426 column address decoder, 428 write / read circuit,
430 gradation voltage generation circuit, 440 logic circuit, 442 control circuit,
444 Display timing control circuit, 446 Host interface circuit,
448 RGB interface circuit, 450 data driver,
452 D / A conversion circuit, 460-1 to 460-M data line driving circuit,
462-1 to 462-M gradation generation amplifier, 464-1 to 464-M drive amplifier,
470 scan driver, 480 driver, 490 power supply circuit,
500 image processing controller, 600 electro-optical device

Claims (15)

A reference voltage generating circuit for generating at least one reference voltage,
A plurality of resistors connected in series between a first power supply line to which a first power supply voltage is supplied and a second power supply line to which a second power supply voltage is supplied; A ladder resistor circuit that outputs first to n-th (n is a natural number) divided voltages divided by each of the resistors;
A selection circuit that selects and outputs an output voltage corresponding to any of the first to n-th divided voltages output by the ladder resistor circuit based on a selection signal;
A plurality of sample and hold circuits, and each sample and hold circuit of the plurality of sample and hold circuits samples and holds the output voltage of the selection circuit; and
A reference voltage generation circuit comprising: In claim 1,
The selection circuit includes:
Having first to n-th switching elements respectively provided between the output node and the first to n-th input nodes;
The first to nth divided nodes output from the ladder resistor circuit are input to the first to nth input nodes, respectively.
Based on the selection signal, any one of the first to n-th switching elements is turned on and the other switching elements are turned off, so that the output voltage is applied to the output node of the selection circuit. A reference voltage generation circuit characterized by being output. In claim 1 or 2,
The selection circuit includes:
Based on the selection signal, in each of the output periods of the first to m-th (m is a natural number) output periods, it corresponds to one of the first to n-th divided voltages output by the ladder resistor circuit. Select and output the output voltage,
The sample hold unit
The first to mth sample and hold circuits as the plurality of sample and hold circuits, and output m reference voltages including the first to mth reference voltages as the at least one reference voltage,
Of the first to m-th sample-and-hold circuits, the i-th sample-and-hold circuit (where i is an integer of 1 ≦ i ≦ m) The output voltage of the selection circuit is sampled during the i-th output period, and is held and output as the i-th reference voltage among the first to m-th reference voltages. circuit. In any one of Claims 1 thru | or 3,
The sample hold unit
A first sample hold unit and a second sample hold unit;
The first sample hold unit includes:
The output voltage of the selection circuit is sampled in the first period of the first period and the second period that are periodically repeated, and in the second period, the sampling is performed in the first period. Hold the voltage
The second sample hold unit includes:
The reference voltage generation circuit characterized in that the output voltage of the selection circuit is sampled in the second period, and the voltage sampled in the second period is held in the subsequent first period. In claim 4,
The sample hold unit
In the first period, based on the output instruction signal, select and output the voltage held by the second sample and hold unit,
In the second period, a reference voltage generation circuit that selects and outputs a voltage held by the first sample-and-hold unit based on the output instruction signal. In any one of Claims 1 thru | or 5,
Each sample hold circuit of the plurality of sample hold circuits,
A reference voltage generating circuit, which is a flip-around sample-and-hold circuit. In claim 6,
Each of the sample and hold circuits is
An operational amplifier;
A sampling capacitor that is provided between a first input terminal of the operational amplifier and an input node of each of the sample and hold circuits, and stores a charge according to an input voltage of the input node in a sampling period;
A reference voltage generation circuit, wherein an output voltage corresponding to the charge accumulated in the sampling capacitor in the sampling period is output in the hold period. In claim 6,
Each of the sample and hold circuits is
An operational amplifier having an analog reference power supply voltage set at its second input terminal;
A sampling switch element and a sampling capacitor provided between the input node of each sample and hold circuit and the first input terminal of the operational amplifier;
A feedback switch element provided between an output terminal of the operational amplifier and the first input terminal;
A flip-around switch element provided between a connection node between the sampling switch element and the sampling capacitor and an output terminal of the operational amplifier;
A reference voltage generation circuit comprising: In claim 8,
In the sampling period, the sampling switch element and the feedback switch element are turned on, the flip-around switch element is turned off, and the sampling capacitor has a charge corresponding to the input voltage of the input node. Is accumulated,
In the hold period, the sampling switch element and the feedback switch element are turned off, and the flip-around switch element is turned on,
Each of the sample and hold circuits is
A reference voltage generation circuit that outputs an output voltage corresponding to the charge accumulated in the sampling capacitor during the sampling period. In any one of Claims 4 thru | or 9.
The at least one reference voltage is a gradation voltage for use in gradation expression of an electro-optical device,
The first sample hold unit includes:
In the first period, the output voltage of the selection circuit is sampled, and in the subsequent second period, the output voltage of the selection circuit sampled in the first period is held as a negative gradation voltage. Output,
The second sample hold unit includes:
The output voltage of the selection circuit is sampled in the second period, and in the subsequent first period, the output voltage of the selection circuit sampled in the second period is held as a positive gradation voltage. A reference voltage generation circuit characterized in that the output is output. In any one of Claims 4 thru | or 9.
The at least one reference voltage is a gradation voltage for use in gradation expression of an electro-optical device,
The first period and the second period are the first divided period and the second divided period, respectively, and the second period of the first period and the second period are the third divided period, respectively. A third divided period, and the third period and the second period are a fifth divided period and a sixth divided period, respectively.
The first sample hold unit includes:
In the first division period, the output voltage of the selection circuit is sampled, and in the subsequent second division period, the output voltage of the selection circuit sampled in the first division period is used as a second color component. Hold and output as the positive polarity gradation voltage of
In the third division period, the output voltage of the selection circuit is sampled, and in the subsequent fourth division period, the output voltage of the selection circuit sampled in the third division period is used as a first color component. Is held and output as the negative gradation voltage of
In the fifth division period, the output voltage of the selection circuit is sampled, and in the subsequent sixth division period, the output voltage of the selection circuit sampled in the fifth division period is used as a third color component. Is held and output as the negative gradation voltage of
The second sample hold unit includes:
In the second division period, the output voltage of the selection circuit is sampled, and in the subsequent third division period, the output voltage of the selection circuit sampled in the second division period is used as a third color component. Hold and output as the positive polarity gradation voltage of
In the fourth division period, the output voltage of the selection circuit is sampled, and in the subsequent fifth division period, the output voltage of the selection circuit sampled in the fourth division period is used as a second color component. Is held and output as the negative gradation voltage of
In the sixth division period, the output voltage of the selection circuit is sampled, and in the subsequent first division period, the output voltage of the selection circuit sampled in the sixth division period is a first color component. A reference voltage generation circuit which holds and outputs as a positive polarity gradation voltage. In claim 11,
The first half period of the first division period and the first half period of the fourth division period are set to polarity inversion periods of the counter voltage supplied to the counter electrode of the electro-optical panel included in the electro-optical device. A characteristic reference voltage generation circuit.   A driver comprising the reference voltage generation circuit according to claim 1.   An electro-optical device comprising the driver according to claim 13.   An electronic apparatus comprising the electro-optical device according to claim 14.

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