CN117134770A - Sectional type digital-to-analog conversion circuit, electronic circuit and electronic equipment - Google Patents
Sectional type digital-to-analog conversion circuit, electronic circuit and electronic equipment Download PDFInfo
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- CN117134770A CN117134770A CN202310843816.XA CN202310843816A CN117134770A CN 117134770 A CN117134770 A CN 117134770A CN 202310843816 A CN202310843816 A CN 202310843816A CN 117134770 A CN117134770 A CN 117134770A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/76—Simultaneous conversion using switching tree
Abstract
The invention provides a sectional digital-to-analog conversion circuit, an electronic circuit and an electronic device, which are used for converting a digital signal into a first analog voltage, wherein the digital signal consists of a low L bit and a high M bit, and the circuit comprises: the low-order conversion module comprises a current source array, a first switch array and a first resistor; the first switch array is used for controlling the on and off of the switch of the first switch array according to the low L-bit value of the digital signal; the current source array is used for providing a first switching current for the first resistor according to the closing and opening of the switches in the first switch array; the first resistor is used for outputting a second analog voltage according to the first conversion current; the high-order conversion module is used for outputting a first analog voltage according to the high M-order numerical value of the digital signal; the first analog voltage is a voltage obtained by superposing two ends of the high-order conversion module on the basis of the second analog voltage; the current source array replaces a resistor network in the prior art, so that the linearity of the segmented digital-to-analog conversion circuit is improved.
Description
Technical Field
The present invention relates to the field of digital-to-analog converters, and in particular, to a segmented digital-to-analog conversion circuit, an electronic circuit, and an electronic device
Background
Digital-to-analog conversion circuits are widely used in the field of integrated circuits and are an important bridge linking the digital world and the analog world. In order to improve the output accuracy of the digital-to-analog converter, there are several approaches; 1) The device size of the digital-to-analog conversion circuit is increased, but the area of the chip and the bit number of the digital-to-analog conversion circuit are in an exponential relation; when the number of bits is greater than 10, the cost of the chip is greatly increased by increasing the device size only to improve the precision; 2) Calibrating the matching device; the scheme firstly has complex technology, increases the design period, and secondly, the performance of the calibrated device can change according to the process, voltage and temperature (process, voltage, temperature-PVT) changes and is unstable. In order to have a good tradeoff between chip area and output accuracy, one skilled in the art will typically choose a segmented digital-to-analog converter.
Referring to fig. 1, a segmented digital-to-analog conversion circuit of the prior art generally adopts a series connection of high-bit small resistors and low-bit large resistors, and connects the series connection of the large resistors and the series connection of the small resistors in parallel; however, after parallel connection, the equivalent resistance of the whole circuit is smaller than the original small resistance of the high-bit series connection, and the voltage obtained by dividing the small resistance of the high-bit series connection is changed, so that the voltage output by the sectional digital-to-analog conversion circuit is deviated, and the Integral Nonlinearity (INL) and the Differential Nonlinearity (DNL) of the circuit are influenced.
Disclosure of Invention
The invention provides a sectional digital-to-analog conversion circuit, an electronic circuit and electronic equipment, which are used for realizing the sectional digital-to-analog conversion circuit with high linearity on the basis of small chip area.
According to a first aspect of the present invention, there is provided a segmented digital-to-analog conversion circuit for converting a first digital signal into a first analog voltage, wherein the first digital signal is composed of low bits and high bits, wherein the low bits are L bits, and the high bits are M bits, the circuit comprising:
the low-order current source array comprises a current source array, a first switch array and a first resistor; wherein a first end and a second end of a first switch array are coupled to a first end of the first resistor and a first end of the current source array, respectively; the first switch array is used for controlling the on and off of a switch of the first switch array according to the value of the low L bit of the first digital signal; the second end of the current source array is coupled to the power end; the current source array is used for providing a first conversion current for the first resistor according to the on and off of a switch in the first switch array; the second end of the first resistor is grounded; the first resistor is used for outputting a second analog voltage according to the first conversion current;
the first end of the high-order resistor array is coupled to the power end, and the second end of the high-order resistor array is coupled to the first end of the first resistor; the high-order conversion module is used for outputting the first analog voltage according to the high-order M-bit value of the first digital signal; the first analog voltage is a voltage obtained by superposing two ends of the high-order conversion module on the basis of the second analog voltage; wherein M and L are integers, M is more than or equal to 1, and L is more than or equal to 1.
Optionally, the current source array comprises (2 L -1) first current sources;
a second end of each first current source is used as a second end of the current source array; a first end of each first current source is used as a first end of the current source array; the currents output by each first current source are equal.
Optionally, the first switch array comprises (2 L -1) low-level switches;
a first end of each low-level switch is used as a first end of the first switch array; the second end of each low-level switch is used as the second end of the first switch array; wherein each low-level switch corresponds to one first current source. Alternatively to this, the method may comprise,
optionally, the high-order conversion module comprises a second current source and a second resistor array;
the first end of the second current source is used as the first end of the high-order conversion module, and the second end of the second current source is coupled to the first end of the second resistor array; the second current source is used for providing a second switching current for the second resistor array;
the second end of the second resistor array is used as the second end of the high-order conversion module; the second resistor array is used for outputting the first analog voltage according to the high M bit value of the first digital signal, the second conversion current and the second analog voltage.
Optionally, the second resistor array comprises (2 M -1) a second resistor and 2 connected in series M A high-level switch;
the second end of each high-level switch is used as the output end of the second resistor array, and all the high-level switches are used for controlling the on/off of the high-level switches according to the high-M-bit value of the first digital signal;
the first end and the second end of each second resistor are respectively coupled with the first end of the high-level switch; all the second resistors are used for outputting the first analog voltage according to the second conversion current, the closed high-order switch and the second analog voltage.
Optionally, parameters in the segmented digital-to-analog conversion circuit satisfy:
R·I msb ＝2 L ·R 2 ·I lsb ；
wherein R is used to characterize the second resistance; r2 is used to characterize the first resistance; i lsb A current magnitude for characterizing the first current source; i msb For characterizing the current magnitude of the second current source.
Optionally, the segmented digital-to-analog conversion circuit further includes a third resistor;
the first and second ends of the third resistor are coupled to the second end of the second resistor array and the first end of the first resistor, respectively.
Optionally, the segmented digital-to-analog conversion circuit further includes a first control unit;
the first control unit is coupled to all the low-level switches and all the high-level switches respectively, and is used for converting the first digital signal into a first control signal and a second control signal and controlling the on and off of all the low-level switches and the on and off of all the high-level switches respectively by using the first control signal and the second control signal; wherein the first control signal is used to characterize a set of level signals converted from the low L bits of the first digital signal; the second control signal is used to characterize a set of level signals converted from the high M-bit values of the first digital signal.
Optionally, the first control unit includes a decoder.
According to a second aspect of the present invention there is provided an electronic circuit comprising the segmented digital to analogue conversion circuit of the first aspect of the present invention and optionally provided.
According to a third aspect of the present invention there is provided an electronic device comprising the electronic circuit provided by the second aspect of the present invention.
Compared with the prior art that a large resistance network is used as a small resistance network of the low-order conversion module and the high-order conversion module to be connected in parallel, the segmented digital-to-analog conversion circuit provided by the invention has the advantages that the equivalent resistance change of the digital-to-analog conversion circuit caused by the parallel connection of the resistors and the on-resistance of the switch in the low-order conversion module is avoided, so that the linearity of the digital-to-analog conversion circuit is deteriorated.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a circuit diagram of a prior art segmented digital to analog conversion circuit;
fig. 2 is a block diagram of a sectional digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 3 is a circuit configuration diagram of a segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 4 is a circuit configuration diagram of a segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 5 is a circuit configuration diagram III of a segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 6 is a circuit configuration diagram of a segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 7 is a circuit configuration diagram of a first current source according to an embodiment of the present invention.
Description of the drawings:
a 10-low level conversion module;
11-a current source array;
12-a first switch array;
a 20-high conversion module;
21-a second resistor array;
vdd-power supply terminal;
vout-the first analog voltage;
r1-a first resistor;
r2-a third resistor;
r-a second resistor;
ilsb-a first current source;
imsb-a second current source;
ilsb 1-a first low-level current source;
ilsbi-i low current source;
IlsbL-L low current source;
an amp-amplifier;
rx-fourth resistor;
m1-a first MOS tube;
m2-a second MOS tube;
m3-third MOS tube.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Before explaining the embodiment of the invention, the design idea of the invention is briefly introduced:
in the prior art of the segmented digital-to-analog conversion circuit, the parallel connection of the small resistance network of the high-order conversion module 20 and the large resistance network of the low-order conversion module 10 affects the equivalent resistance of the whole circuit, so that the actual voltage obtained by the parallel connection of the high-order conversion module 20 and the low-order conversion module 10 is different from an ideal value, and further the voltage output by the segmented digital-to-analog conversion circuit is deviated, and the linearity of the segmented digital-to-analog conversion circuit is deteriorated. Meanwhile, in the low-level conversion module 10, the on-resistance of each switch further affects the equivalent resistance of the whole circuit, and the linearity of the segmented digital-to-analog conversion circuit is deteriorated. Therefore, the key to improving the linearity of the segmented digital-to-analog conversion circuit is to reduce the influence of the parallel connection of the resistor network and the on-resistance of the switch on the equivalent resistance of the whole circuit. The invention replaces the large resistance network of the original low-level conversion module 10 and the switch array for controlling the output voltage of the large resistance network with the current source array 11 and the switch array for controlling the whole output current of the current source array 11, and the current output by the whole current source array 11 flows through a resistor to realize the voltage output of the low-level conversion module 10. Because the current output by the current source array 11 cannot be changed due to the change of the whole equivalent resistance of the circuit, the influence of the parallel connection of the resistor network and the on-resistance of the switch on the whole equivalent resistance of the circuit can be effectively avoided, and the linearity of the sectional digital-to-analog conversion circuit is improved.
Referring to fig. 2, an embodiment of the present invention provides a segmented digital-to-analog conversion circuit for converting a first digital signal into a first analog voltage Vout, wherein the first digital signal is composed of a low bit and a high bit, wherein the low bit is L bits, and the high bit is M bits, the circuit includes:
a low-order conversion module 10, wherein the low-order conversion module 10 comprises a current source array 11, a first switch array 12 and a first resistor R1; wherein a first end and a second end of the first switch array 12 are coupled to a first end of the first resistor R1 and a first end of the current source array 11, respectively; the first switch array 12 is configured to control on and off of its own switch according to the low L bit value of the first digital signal; a second terminal of the current source array 11 is coupled to a power supply terminal Vdd; the current source array 11 is configured to provide a first switching current to the first resistor R1 according to the on and off states of the switches in the first switch array 12; the second end of the first resistor R1 is grounded; the first resistor R1 is used for outputting a second analog voltage according to the first conversion current;
a high-level conversion module 20, wherein a first end of the high-level resistor array is coupled to the power supply terminal Vdd, and a second end thereof is coupled to a first end of the first resistor R1; the high-order conversion module 20 is configured to output the first analog voltage Vout according to a high-order M-bit value of the first digital signal; wherein the first analog voltage Vout is a voltage obtained by superimposing two ends of the high-order conversion module 20 on the second analog voltage; wherein M and L are integers, M is more than or equal to 1, and L is more than or equal to 1.
Referring to fig. 3, as an embodiment, the current source array 11 includes (2 L -1) a first current source Ilsb;
a second end of each of the first current sources Ilsb serves as a second end of the current source array 11; a first end of each of the first current sources Ilsb serves as a first end of the current source array 11; wherein, the current outputted by each first current source Ilsb is equal.
The first switch array 12 corresponding to the current source array 11 includes (2 L -1) low-level switches;
a first end of each low-side switch serves as a first end of the first switch array 12; the second end of each low-side switch serves as the second end of the first switch array 12; wherein each low-level switch corresponds to one of the first current sources Ilsb.
Referring to fig. 4, as an alternative embodiment, the current source array 11 further includes first to L-th low-level current sources Ilsb1 to IlsbL;
the second end of the first low-level current source Ilsb1 to the second end of the L-th low-level current source IlsbL are all used as the second ends of the current source array 11; the first end of the first low-level current source Ilsb1 to the first end of the L-th low-level current source IlsbL are all used as the first end of the current source array 11; the current magnitude of the first low-level current source Ilsb1 is equal to the current magnitude of the first current source Ilsb; from the first low-level current source Ilsb1 to the L-th low-level current source IlsbL, the current magnitude of each current source is sequentially increased by 2 times; specific: the current level of the i-th low-level current source Ilsbi is 2 i-1 The current magnitude of the first low-order current source Ilsb1 is multiplied. The specific embodiment has the beneficial effects of reducing the number of the current sources, reducing the chip area and reducing the production cost.
The first switch array 12 corresponding to the current source array 11 includes L low-level switches;
a first end of each low-side switch serves as a first end of the first switch array 12; the second end of each low-level switch serves as the second end of the first switch array 12; wherein each low-level switch corresponds to a low-level current source.
Referring to fig. 3, as a specific embodiment, the high-order conversion module 20 includes a second current source Imsb and a second resistor R array 21;
a first end of the second current source Imsb is used as a first end of the high-order conversion module 20, and a second end thereof is coupled to a first end of the second resistor R array 21; the second current source Imsb is configured to provide a second switching current to the second resistor R array 21;
a second end of the second resistor R array 21 is used as a second end of the high-order conversion module 20; the second resistor R array 21 is configured to output the first analog voltage Vout according to the high M bit value of the first digital signal, the second conversion current, and the second analog voltage.
Referring to fig. 3, as an embodiment, the second resistor R array 21 includes (2 M -1) a series connection of second resistors R and 2 M A high-level switch;
the second end of each high-level switch is used as the output end of the second resistor R array 21, and all the high-level switches are used for controlling the on/off of the high-level switches according to the high-M-bit value of the first digital signal;
the first end and the second end of each second resistor R are respectively coupled with the first end of the high-level switch; all the second resistors R are configured to output the first analog voltage Vout according to the second switching current and the closed high-side switch and the second analog voltage; the voltage across the high-order conversion module 20 is superimposed on the first analog voltage Vout, which is the second analog voltage.
As a specific embodiment, original 2 M High-order switches connected in parallel, i.e. 2 M The parallel single-stage decoding switches may also be changed into multi-stage decoding switches, which are not limited herein.
As a specific implementation manner, in order to reduce differential nonlinearity of the segmented digital-to-analog conversion circuit provided by the embodiment of the present invention, parameters in the segmented digital-to-analog conversion circuit satisfy:
R·I msb ＝2 L ·R 2 ·I lsb ；
wherein R is used to characterize the second resistance R; r2 is used to characterize the first resistance R1; i lsb A current magnitude for characterizing the first current source Ilsb; i msb A current scale for characterizing the second current source ImsbIs small. That is, in the high-order conversion module 20, the voltage generated by the second conversion current flowing through one of the second resistors R is equal to the voltage generated by the first resistor R1 when all the switches in the first switch array 12 are closed in the low-order conversion module 10.
Referring to fig. 5, as a specific embodiment, the segmented digital-to-analog conversion circuit further includes a third resistor R2;
the first and second ends of the third resistor R2 are coupled to the second end of the second resistor R array 21 and the first end of the first resistor R1, respectively. The third resistor R2 is configured to generate a fixed dc bias voltage of the segmented digital-to-analog conversion circuit according to the second conversion current, where the fixed dc bias voltage is also superimposed in the first analog voltage Vout output by the high-order conversion module 20 to be used as a starting voltage of the first analog voltage Vout. For example, when the high-order value and the low-order value of the first digital signal are both zero, the voltages across the second analog voltage and the high-order conversion module 20 are also equal to zero, and then the first analog voltage Vout is equal to the fixed dc bias voltage.
As a preferred embodiment, to ensure that the first analog voltage Vout output by the high-order conversion module 20 conforms to a binary voltage output, the resistance of the second resistor R is set to be equal to the resistance of the first resistor R1 plus the resistance of the third resistor R2.
Referring to fig. 7, as a specific embodiment, the specific structure of the first current source Ilsb is: the amplifier amp, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth resistor Rx.
A reference voltage is input to the non-inverting input terminal of the comparator amp; the first end of the fourth resistor Rx is connected with the inverting input end of the comparator amp; the output end of the comparator amp is connected with the grid electrode of the first MOS tube M1;
the first end of the first MOS tube M1 is connected with the first end of the fourth resistor Rx, and the second end of the first MOS tube M2 is connected with the second end of the second MOS tube;
the second MOS tube M2 and the third MOS tube M3 form a current mirror; the grid electrode of the second MOS tube M2 is respectively connected with the second end of the second MOS tube M2 and the grid electrode of the third MOS tube M3; the first end of the second MOS tube M2 and the first end of the third MOS tube M3 are both connected with the power supply end Vdd; the second end of the third MOS transistor M3 is used as an output end of the first current source Ilsb, and outputs the current of the first current source Ilsb; the formula of the current of the first current source Ilsb is as follows:
wherein M is used for representing the ratio of the width-to-length ratio of the third MOS tube M3 to the width-to-length ratio of the second MOS tube M2; r is R x For characterizing the resistance of the fourth resistor Rx.
Referring to fig. 6, the above-mentioned segmented digital-to-analog conversion circuit according to the embodiment of the present invention uses the ground terminal as a reference point, and as a specific implementation manner, the segmented digital-to-analog conversion circuit may also use the power terminal Vdd as a reference point; the second terminal of the current source array 11 is changed from the coupled power terminal Vdd to the coupled ground terminal; the second end of the first resistor R1 is required to be coupled to the power supply terminal Vdd instead of the coupling ground terminal; the first terminal of the high-order resistor array is required to be changed from the coupled power terminal Vdd to the coupled ground terminal. Of course, the specific reference point of the power supply terminal Vdd or the ground terminal Vdd may be selected according to actual requirements, which is not limited herein.
As a specific embodiment, the segmented digital-to-analog conversion circuit further includes a first control unit;
the first control unit is coupled to all the low-level switches and all the high-level switches respectively, and is used for converting the first digital signal into a first control signal and a second control signal and controlling the on and off of all the low-level switches and the on and off of all the high-level switches respectively by using the first control signal and the second control signal; wherein the first control signal is used to characterize a set of level signals converted from the low L bits of the first digital signal; the second control signal is used to characterize a set of level signals converted from the high M-bit values of the first digital signal. Specific: the first control unit includes a decoder. Of course, the first control unit may be other devices capable of converting the digital signal into a corresponding level signal, which is not limited herein.
Taking the first digital signal as 6 bits, the first 3 bits of the first digital signal as low bits, and the last 3 bits as high bits as examples, the workflow of the segmented digital-to-analog conversion circuit provided by the embodiment of the invention is introduced:
the first digital signal is 111011, but may be any other 6-bit binary number, which is not limited herein. The first control unit converts 111011 into the first control signal and the second control signal; wherein the first control signal is used to characterize the set of level signals converted by 011 and the second control signal is used to characterize the set of level signals converted by 111.
The first control signal is used for controlling the on and off of all low-level switches in the first switch array 12; specifically, the first control signal controls the first switch array 12 to be turned on, and the first to third low switches and the fourth to seventh low switches are turned off; the first switching current output by the current source array 11 via the first switch array 12 is equal to 3 times the first current source Ilsb current; however, this is limited to the current source array 11 including 7 first current sources Ilsb with equal current, if the current source array 11 includes first to third low-level current sources Ilsb1 to Ilsb 2 times the current level of each current source, only the low-level switches corresponding to the first and second low-level current sources Ilsb1 and Ilsb1 are closed, and the low-level switch corresponding to the third low-level current source is opened.
The second control signal is used for controlling the on and off of all high-order switches in the second resistor R array 21; specifically, the second control signal controls the 8 th high-level switch from the ground to the top to be closed in the second resistor R array 21, and the other high-level switches are all opened; the voltage across the high-side conversion module 20 is equal to the product of the second conversion current and 7 times the resistance value of the second resistor R.
If the third resistor R2 is not set at this time, that is, the fixed dc bias voltage is not superimposed in the first analog voltage Vout, the first analog voltage Vout output by the high-level conversion module 20 is equal to the product of the second conversion current and 7 times the resistance value of the second resistor r+the product of the second conversion current and the resistance value of the first resistor R1+3 times the product of the current of the first current source Ilsb and the resistance value of the first resistor R1.
The sectional digital-to-analog conversion circuit provided by the invention has the beneficial effects that:
1. high linearity: the low-order conversion module 10 is formed by a current source array 11, a first switch array 12 and a first resistor R1; compared with the prior art that a large resistance network is used as the small resistance network of the low-order conversion module 10 and the high-order conversion module 20 in parallel, the influence on the linearity of the digital-to-analog conversion circuit due to the equivalent resistance change of the digital-to-analog conversion circuit caused by the parallel connection of the resistors and the on resistance of the switch is avoided, so that the linearity of the digital-to-analog conversion circuit is improved.
The embodiment of the invention also provides an electronic circuit which comprises the segmented digital-to-analog conversion circuit.
The embodiment of the invention also provides electronic equipment comprising the electronic circuit.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (11)
1. A segmented digital-to-analog conversion circuit for converting a first digital signal into a first analog voltage, wherein the first digital signal is composed of low bits and high bits, wherein the low bits are L bits, and the high bits are M bits, the circuit comprising:
the low-order current source array comprises a current source array, a first switch array and a first resistor; wherein a first end and a second end of a first switch array are coupled to a first end of the first resistor and a first end of the current source array, respectively; the first switch array is used for controlling the on and off of a switch of the first switch array according to the value of the low L bit of the first digital signal; the second end of the current source array is coupled to the power end; the current source array is used for providing a first conversion current for the first resistor according to the on and off of a switch in the first switch array; the second end of the first resistor is grounded; the first resistor is used for outputting a second analog voltage according to the first conversion current;
the first end of the high-order resistor array is coupled to the power end, and the second end of the high-order resistor array is coupled to the first end of the first resistor; the high-order conversion module is used for outputting the first analog voltage according to the high-order M-bit value of the first digital signal; the first analog voltage is a voltage obtained by superposing two ends of the high-order conversion module on the basis of the second analog voltage; wherein M and L are integers, M is more than or equal to 1, and L is more than or equal to 1.
2. The segmented digital to analog conversion circuit of claim 1, wherein the current source array comprises (2 L -1) first current sources;
a second end of each first current source is used as a second end of the current source array; a first end of each first current source is used as a first end of the current source array; the currents output by each first current source are equal.
3. According to claimThe segmented digital to analog conversion circuit of claim 1, wherein said first switch array comprises (2 L -1) low-level switches;
a first end of each low-level switch is used as a first end of the first switch array; the second end of each low-level switch is used as the second end of the first switch array; wherein each low-level switch corresponds to one first current source.
4. The segmented digital to analog conversion circuit of claim 1, wherein said high-order conversion module comprises a second current source, a second resistor array;
the first end of the second current source is used as the first end of the high-order conversion module, and the second end of the second current source is coupled to the first end of the second resistor array; the second current source is used for providing a second switching current for the second resistor array;
the second end of the second resistor array is used as the second end of the high-order conversion module; the second resistor array is used for outputting the first analog voltage according to the high M bit value of the first digital signal, the second conversion current and the second analog voltage.
5. The segmented digital to analog conversion circuit of claim 4, wherein said second resistor array comprises (2 M -1) a second resistor and 2 connected in series M A high-level switch;
the second end of each high-level switch is used as the output end of the second resistor array, and all the high-level switches are used for controlling the on/off of the high-level switches according to the high-M-bit value of the first digital signal;
the first end and the second end of each second resistor are respectively coupled with the first end of the high-level switch; all the second resistors are used for outputting the first analog voltage according to the second conversion current, the closed high-order switch and the second analog voltage.
6. The segmented digital to analog conversion circuit of claim 5, wherein parameters within said segmented digital to analog conversion circuit satisfy:
R·I msb ＝2 L ·R 2 ·I lsb ；
wherein R is used to characterize the second resistance; r2 is used to characterize the first resistance; i lsb A current magnitude for characterizing the first current source; i msb For characterizing the current magnitude of the second current source.
7. The segmented digital to analog conversion circuit of claim 6, further comprising a third resistor;
the first and second ends of the third resistor are coupled to the second end of the second resistor array and the first end of the first resistor, respectively.
8. The digital-to-analog conversion circuit of any one of claims 1 to 5, further comprising a first control unit;
the first control unit is coupled to all the low-level switches and all the high-level switches respectively, and is used for converting the first digital signal into a first control signal and a second control signal and controlling the on and off of all the low-level switches and the on and off of all the high-level switches respectively by using the first control signal and the second control signal; wherein the first control signal is used to characterize a set of level signals converted from the low L bits of the first digital signal; the second control signal is used to characterize a set of level signals converted from the high M-bit values of the first digital signal.
9. The segmented digital to analog conversion circuit of claim 8, wherein said first control unit comprises a decoder.
10. An electronic circuit comprising the segmented digital-to-analog conversion circuit of any one of claims 1 to 9.
11. An electronic device comprising the electronic circuit of claim 10.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310843816.XA CN117134770A (en) | 2023-07-10 | 2023-07-10 | Sectional type digital-to-analog conversion circuit, electronic circuit and electronic equipment |
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| CN202310843816.XA CN117134770A (en) | 2023-07-10 | 2023-07-10 | Sectional type digital-to-analog conversion circuit, electronic circuit and electronic equipment |
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