CN219834120U - Digital-to-analog conversion circuit, digital-to-analog conversion chip and electronic equipment - Google Patents

Abstract

The utility model relates to a digital-to-analog conversion circuit, a digital-to-analog conversion chip and electronic equipment. The digital-to-analog conversion circuit comprises a conversion network, wherein the conversion network is connected between a first reference voltage end of the digital-to-analog conversion circuit and an analog voltage output end of the digital-to-analog conversion circuit, and outputs an analog voltage signal mapped with an input digital signal through the analog voltage output end; and the voltage offset circuit is connected with the analog voltage output end and generates a set voltage offset at the analog voltage output end.

Description

Digital-to-analog conversion circuit, digital-to-analog conversion chip and electronic equipment

Technical Field

The utility model relates to the technical field of digital-to-analog conversion, in particular to a digital-to-analog conversion circuit, a digital-to-analog conversion chip and electronic equipment.

Background

A digital-to-analog converter (Digital to Analog Converter, DAC) is a device that converts a digital signal into an analog signal. In general, the data converter typically implements digital-to-analog conversion of signals using a conversion network, which may be configured as an R2R resistor network architecture, a resistor string network architecture, or the like. However, the analog voltage signals output by the conversion network are all adjusted from the time when the voltage value is 0, so that the configured digital-to-analog converter often needs a higher adjustment bit number.

Disclosure of Invention

An object of the present utility model is to provide a digital-to-analog conversion circuit, a digital-to-analog conversion chip and an electronic device.

According to a first aspect of the present utility model there is provided a digital to analogue conversion circuit comprising:

the conversion network is connected between a first reference voltage end of the digital-to-analog conversion circuit and an analog voltage output end of the digital-to-analog conversion circuit, and outputs an analog voltage signal mapped with an input digital signal through the analog voltage output end; the method comprises the steps of,

and the voltage offset circuit is connected with the analog voltage output end and generates a set voltage offset at the analog voltage output end.

Optionally, the switching network includes a resistor network and a switch network connected with the resistor network, the switch state of the switch network is mapped with the digital signal, and the switching network has a plurality of circuit structures corresponding to a plurality of switch states one by one; at least a portion of the resistance of the voltage offset circuit is the resistance of the resistor network.

Optionally, the digital-to-analog conversion circuit further includes a first operational amplifier circuit, an input end of the first operational amplifier circuit is connected to a first reference voltage input end of the digital-to-analog conversion circuit, and an output end of the first operational amplifier circuit is connected to the conversion network as the first reference voltage end.

Optionally, the voltage offset circuit is connected between the second reference voltage terminal of the digital-to-analog conversion circuit and the analog voltage output terminal.

Optionally, the digital-to-analog conversion circuit further includes a second operational amplifier circuit, an input end of the second operational amplifier circuit is connected to a second reference voltage input end of the digital-to-analog conversion circuit, and an output end of the second operational amplifier circuit is connected to the voltage offset circuit as the second reference voltage end.

Optionally, the resistor network is an R2R resistor network, the resistor network includes a plurality of first resistors and a plurality of second resistors, the second resistors have a resistance value 2 times that of the first resistors, and the voltage offset circuit includes the plurality of first resistors of the R2R resistor network.

Optionally, the plurality of first resistors of the R2R resistor network are sequentially connected, where the second end of the previous first resistor is connected to the first end of the next first resistor, the second end of the first resistor at the end is connected to the analog voltage output end, the first end of the first resistor at the beginning is connected to the switch network through the first second resistor in the first branch, and the first end of the first resistor at the end is connected to the second reference voltage input end through the second resistor in the second branch;

the voltage offset circuit includes the second resistor and the plurality of first resistors.

Optionally, the voltage offset circuit is connected between the first reference voltage terminal and the analog voltage output terminal.

Optionally, the resistor network is an R2R resistor network, and the voltage offset circuit includes a voltage dividing resistor and the conversion network, where the voltage dividing resistor is connected between the first reference voltage terminal and the analog voltage output terminal.

According to a second aspect of the present utility model, there is provided a digital-to-analog conversion chip, the chip comprising a housing, a digital-to-analog conversion circuit encapsulated in the housing, and pins exposed through the housing, wherein the digital-to-analog conversion circuit is the digital-to-analog conversion circuit of the first aspect, and an external connection end of the digital-to-analog conversion circuit is connected with corresponding pins.

According to a third aspect of the present utility model there is provided an electronic device comprising a digital to analogue conversion circuit as described in the first aspect, or comprising a digital to analogue conversion chip as described in the second aspect.

The utility model has the technical effects that by arranging the voltage offset circuit, the analog voltage signal output by the conversion circuit in combination with the set voltage offset can be adjusted in the demand range directly from the minimum voltage value of the analog voltage signal in the demand range, thereby achieving the purpose of reducing the adjustment bit number of the digital-to-analog converter.

Other features of the present utility model and its advantages will become apparent from the following detailed description of exemplary embodiments of the utility model, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description, serve to explain the principles of the utility model.

FIG. 1 is a block diagram of the overall architecture of a digital to analog conversion circuit according to one embodiment;

FIG. 2 is a circuit diagram of a digital to analog conversion circuit according to one embodiment;

FIG. 3 is a circuit diagram of a digital to analog conversion circuit according to another embodiment;

fig. 4 is an equivalent circuit diagram of a digital-to-analog conversion circuit according to another embodiment;

fig. 5 is a circuit diagram of a digital-to-analog conversion circuit according to another embodiment.

Reference numerals illustrate:

a switching network 100; a switching network 110; a resistor network 120; a voltage offset circuit 200.

Detailed Description

Various exemplary embodiments of the present utility model will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present utility model unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the utility model, its application, or uses.

Techniques and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the related art, when a plurality of digital-to-analog converters with different digits are input with the same reference voltage, the digital-to-analog converter with a larger number of adjustment digits has smaller absolute value of adjustment steps, and thus some inherent deviations caused by processes and the like have larger influence on the digital-to-analog converters, which affects the accuracy of analog voltage signals obtained by converting digital signals. Specifically, for example, the adjustable range of the output analog voltage signal is 3-12mV, and since the existing digital-to-analog converter needs to be adjusted from 0, in order to meet the set adjustable range of 3-12mV, the actual adjustable voltage range is 0-12mV, so that the number of adjustment bits required is increased, and further the problem that the number of adjustment bits of the digital-to-analog converter is wasted affects the accuracy of the analog voltage signal output by the digital-to-analog converter.

In order to solve the problem of bit waste of the digital-to-analog conversion circuit, the disclosure provides a digital-to-analog conversion circuit, which can generate a set voltage offset at an analog voltage output end, so that an actual adjustable voltage range of the digital-to-analog conversion circuit is basically consistent with the set adjustable voltage range, and further the digital-to-analog conversion circuit with matched adjustment bit number can be selected according to the requirement of the adjustable voltage range, thereby avoiding the waste of adjustment bit number.

Fig. 1 is a schematic block diagram of a digital-to-analog conversion circuit according to an embodiment of the present utility model.

According to fig. 1, the digital-to-analog conversion circuit includes a conversion network 100, wherein the conversion network 100 is connected between a first reference voltage terminal of the digital-to-analog conversion circuit and an analog voltage output terminal of the digital-to-analog conversion circuit, and the conversion network 100 outputs an analog voltage signal Uout mapped with an input digital signal through the analog voltage output terminal.

In this embodiment, the switching network 100 may be a switching network based on a weighted resistor network, a switching network based on an R2R resistor network (or referred to as an inverted T resistor network), a switching network based on a weighted current network, or the like, which is not limited herein.

In the digital-to-analog conversion circuit, whatever type of conversion network, the conversion network 100 includes a switch network, the number of switches in the switch network is the same as the number of binary bits of the digital signal, the plurality of binary bits of the digital signal are in one-to-one correspondence with the plurality of switches of the switch network, each binary bit is used for controlling the switch state of the corresponding switch, that is, the digital signal is mapped with the switch state of the switch network, different digital signals correspond to different switch states of the switch network, and the switch network changes the voltage value of the analog voltage signal output by the analog voltage output end of the analog voltage conversion circuit under different switch states, so as to further realize the purpose of converting the digital signal into the analog voltage signal.

In this embodiment, as shown in fig. 1, in addition to the basic conversion network 100, the digital-to-analog conversion circuit further includes a voltage offset circuit 200, where the voltage offset circuit 200 is connected to an analog voltage output terminal, and the voltage offset circuit 200 generates a set voltage offset value at the analog voltage output terminal. The set voltage offset can be determined according to the adjustable voltage range required by the system.

In this embodiment, the system configuring the digital-to-analog conversion circuit may output an analog voltage signal mapped with a digital signal based on the first reference voltage Verf1 and a set voltage offset, that is, the system may input the first reference voltage Vref1 into the conversion network 100 through the first reference voltage terminal, then input the digital signal into the conversion network, and the conversion network outputs the first reference voltage Vref1 with a proportionality coefficient corresponding to the input digital signal, so as to obtain a converted analog voltage signal Uout. When the conversion network 110 inputs a digital signal with each binary bit being 0, under the action of the voltage offset circuit 200, the voltage value of the analog voltage signal Uout output by the analog voltage output end of the conversion network 100 is a set voltage offset, that is, the voltage value of the analog voltage signal Uout output at this time is the minimum voltage value Uomin of the analog voltage signal, where the set voltage offset can be determined according to the minimum voltage value Uomin of the analog voltage signal. In the case that the digital signal input by the conversion network 110 is in the set range, the conversion network 100 obtains the adjustable range of the analog voltage signal required by the system according to the input digital signal and the set voltage offset.

In other words, the output analog voltage signal is directly in the required adjustable range by the voltage offset circuit 200, so that the bit number requirement of the digital-to-analog converter can be effectively reduced, and the adjustment step size can be obviously increased under the condition of the same input reference voltage, so as to improve the adjustment precision of the analog voltage signal.

In some embodiments, in the adjustable range of the first reference voltage Vref1 output by the system, the maximum value vomax=15v of the first reference voltage Vref1, the maximum value vomin=3.6v of the first reference voltage Vref1, the adjustment step distance Δvo=12 mV, and the conversion of Vomax and Vomin into the corresponding relationship with Δvo is:

Vomax＝ΔVo×15/0.012＝1250×ΔVo (1)

Vomin＝ΔVo×3.6/0.012＝300×ΔVo (2)

the minimum adjustment steps required by the system are:

(Vomax-Vomin)/ΔVo＝1250-300＝950 (3)

i.e. the corresponding DAC may only require 10 bits, n=10

The number of adjustable segments of the corresponding DAC is n=2n—1=1023 (4)

If the maximum output value of the DAC is Uomax and the initial minimum value of the DAC is Uomin, there are:

ΔUo＝(Uomax-Uomin)/(2n-1) (5)

where Δuo is the adjustment stride of the DAC.

Since the output of the DAC is proportional to the output of the system, its settling steps are also proportional, and the scaling factor here can be denoted by K, namely:

Vout＝Uout×K (6)

ΔVo＝ΔUo×K (7)

meanwhile, output uh=vomax/K of DAC corresponding to Vomax

The combinations (1) and (7) are:

UH＝Vomax/K＝1250×ΔVo/(ΔVo /ΔUo)＝1250×ΔUo (8)

similarly, output ul=vomin/K of DAC corresponding to Vomin

The combinations (2) and (7) are:

UL＝Vomin/K＝300×ΔVo/(ΔVo /ΔUo)＝300×ΔUo (9)

considering that the output range of the DAC is required to meet the adjustment range of the system, the combination (9) comprises:

Uomin.ltoreq.UL, i.e.Uomin.ltoreq.DeltaUox300 (10)

According to (8), uomax.gtoreq.DELTA.Uox.times.1250 (11)

In combination with (4) and (11), there are:

(Uomax＝Uomin+ΔUo×1023)≥ΔUo×1250 (12)

Uomin≥(ΔUo×1250-1023×ΔUo)＝227×ΔUo (13)

i.e. if Uomin < Δuox 227, uomax will not reach the output maximum required by the system.

Combining (10) and (13), it is possible to obtain:

ΔUo×227≤Uomin≤ΔUo×300 (14)

meanwhile, the correspondence between the maximum voltage value Uomax of the analog voltage signal and the minimum voltage value Uomin of the analog voltage signal is:

Uomax＝Uomin+1023×ΔUo (15)

in some embodiments, the conversion network 100 includes a resistor network 120 and a switch network 110 connected to the resistor network 120, the switch states of the switch network 110 are mapped with digital signals, and the conversion network 100 has a plurality of circuit structures corresponding to a plurality of switch states one by one; at least a portion of the resistance of the voltage offset circuit 200 is the resistance of the resistor network 120.

In some embodiments, the switching network 110 may be provided with a plurality of switches, i.e., switches Sn-1, sn-2, … …, S1, S0, with different switches opening or closing corresponding to different switch states. Taking fig. 2 as an example, the switch is a single-pole double-throw switch, a first fixed end of one single-pole double-throw switch is connected with a first reference voltage end, a second fixed end of the single-pole double-throw switch is grounded, and a movable end of the single-pole double-throw switch is connected with a corresponding circuit structure. The movable terminal is connected with the first fixed terminal, so that the switch can be considered to be closed, and the circuit structure can perform digital-to-analog conversion processing. The movable terminal is connected with the second stationary terminal, which can be regarded as that the switch is disconnected, and the input digital signal cannot be input into the circuit structure. In other words, the input digital signals are different, and the number of the corresponding closed switches is also different, so as to realize the output of voltage values with different proportions in the adjustable range of the analog voltage signal.

In one example, in the case where the input digital signal corresponds to the minimum voltage value Uomin of the analog voltage signal, all switches are opened, the resistor network 120 is opened, and the conversion network 100 may output the analog voltage signal corresponding to the voltage offset by using the resistor of the voltage offset circuit 200. In case the digital signal corresponds to the maximum voltage value Uomax of the analog voltage signal, all switches are closed and the resistive network 120 is closed, the conversion network 100 can output the maximum voltage value Uomax of the analog voltage signal using the voltage offset circuit 200 and the resistive network 120. In the case that the digital signal corresponds to an analog voltage signal within the above-mentioned adjustable range, the switch corresponding to the digital signal is closed, and the conversion network 100 may output the corresponding analog voltage signal. In other words, with the switching network 110, an analog voltage signal in an adjustable range can be output to meet the requirements of the above system.

In some embodiments, the digital-to-analog conversion circuit further comprises a first operational amplifier circuit, an input terminal of the first operational amplifier circuit is connected to a first reference voltage input terminal of the digital-to-analog conversion circuit, and an output terminal of the first operational amplifier circuit is connected to the conversion network 100 as the first reference voltage terminal.

In one example, the digital signal may be preprocessed, e.g., filtered, amplified, etc., by the first operational amplifier U1, so that the input terminal of the first operational amplifier U1 may output the relatively stable first reference voltage Vref1 to the conversion network 100, so as to further improve the adjustment accuracy of the output analog voltage signal.

In one embodiment, the voltage offset circuit 200 is connected between the second reference voltage terminal of the digital-to-analog conversion circuit and the analog voltage output terminal.

In one example, a first reference voltage terminal of the digital-to-analog conversion circuit outputs a first reference voltage Vref1 to the conversion network 100, and a second reference voltage terminal of the digital-to-analog conversion circuit outputs a second reference voltage Vref2 based on the voltage offset circuit 200. The difference between the first reference voltage Vref1 and the first reference voltage Vref2 is input to the conversion network 100, and the conversion network 100 can generate a set voltage offset at the analog voltage output end, so that the output analog voltage signal can be within the required adjustable range. In other words, the voltage offset circuit 200 is connected between the second reference voltage terminal and the analog voltage output terminal of the digital-to-analog conversion circuit, so that the adjustment can be directly started from the minimum voltage value of the analog voltage signal in the required range.

In one embodiment, the digital-to-analog conversion circuit further includes a second operational amplifier circuit, an input terminal of the second operational amplifier circuit is connected to a second reference voltage input terminal of the digital-to-analog conversion circuit, and an output terminal of the second operational amplifier circuit is connected to the voltage offset circuit 200 as a second reference voltage terminal.

In the embodiment of fig. 2, the second operational amplifier U2 may perform preprocessing, such as filtering, amplifying, etc., on the second reference voltage Vref2, so that the input end of the second operational amplifier U2 may output a relatively stable second reference voltage Vref2 to the conversion network 100, the difference between the first reference voltage Vref1 and the second reference voltage Vref2 is input to the conversion network 100, and the analog voltage output end of the conversion network 100 may output a desired adjustable range, so as to achieve direct adjustment from the minimum voltage value of the analog voltage signal within the desired range.

In the embodiment of fig. 2, the second operational amplifier circuit outputs a given second reference voltage Vref2, and accordingly, the digital-to-analog conversion circuit adjusts the step size:

ΔUo＝(Vref1-Vref2)/2n (16)

Uout＝ΔUo×N+Vref2 (17)

wherein, N is the adjustment level of the digital-to-analog conversion circuit, and for the digital-to-analog conversion circuit of 10 bits, the maximum is 1023, and the minimum is 0, namely:

when n=0, uout=uomin=vref 2 (18)

When n=1023, uout=uomax= (Vref 1-Vref 2) × (2N-1)/2n+vref2=vref 1- Δuo

Vref1＝Uomax+ΔUo (19)

According to (14) and (18), vref2 has a range of values: ΔUoX105.ltoreq.Vref 2.ltoreq.300 XΔUo

According to (15), (18) and (19) there are: vref 1=vref 2+1024×Δuo (20)

It can be seen that the smaller the corresponding adjustment step size of Vref2, the larger the corresponding adjustment step size ΔUo for the same Vref 1. But within the Vref2 adjustable range, the step size is not greatly different.

If the first reference voltage Vref1 of the DAC is 2.7V, and the second reference voltage Vref2 = 227 x deltauo,

according to (20), the adjustment step size can be obtained: Δuo=2.16 mV

When Vref2 = 300 x Δuo, a step size Δuo = 2.04mV is obtained

In other words, the same second reference voltage Vref2 is input, and the accuracy of the output analog voltage signal can be effectively improved by the second operational amplifier circuit.

In one embodiment, the resistor network 120 is an R2R resistor network 120, the resistor network 120 includes a plurality of first resistors and a plurality of second resistors, the second resistors have a resistance value 2 times that of the first resistors, and the voltage offset circuit 200 includes a plurality of first resistors of the R2R resistor network 120.

In other words, the R2R resistor network 120 may be composed of one second resistor, a first resistor, and another second resistor connected in parallel to form one resistor ladder, so that the R2R resistor network 120 may output a corresponding analog voltage signal.

In the embodiment of fig. 2, a plurality of first resistors of the R2R resistor network 120 are sequentially connected, wherein a second end of a previous first resistor is connected to a first end of a next first resistor, a second end of a terminal first resistor is connected to an analog voltage output terminal, a first end of a starting first resistor is connected to the switch network 110 through a first second resistor in a first branch, and a second branch is connected to a second reference voltage input terminal through a second resistor; the voltage offset circuit 200 includes a second resistor and a plurality of first resistors.

In one embodiment, the voltage offset circuit 200 is connected between the first reference voltage terminal and the analog voltage output terminal. Taking fig. 3 as an example, the voltage offset circuit 200 may include a voltage dividing resistor R0, where one end of the voltage dividing resistor R0 is connected to the first reference voltage terminal, and the other end of the voltage dividing resistor R0 is connected to a connection point between the second resistor of the terminal and the first resistor of the terminal. By arranging the voltage offset circuit 200 between the first reference voltage terminal and the analog voltage output terminal, it is possible to achieve an adjustment directly from the minimum voltage value of the analog voltage signal within the required range.

In one embodiment, the resistor network 120 is an R2R resistor network 120, and the voltage offset circuit 200 includes a voltage dividing resistor R0 and the conversion network 100, where the voltage dividing resistor R0 is connected between the first reference voltage terminal and the analog voltage output terminal.

In the embodiment of fig. 3, the voltage offset circuit 200 may include a voltage dividing resistor R0 and the conversion network 100 in a digital-to-analog conversion circuit. That is, for the digital-to-analog conversion circuit of the R2R resistor network 120, the digital-to-analog conversion circuit has a minimum voltage value Uomin of the analog voltage signal, and the analog voltage signal Uout output by the digital-to-analog conversion circuit is:

Uout＝Vref1×N+Uomin (21)

for n=0, the equivalent circuit of Uomin, which is the minimum voltage value of the analog voltage signal, is shown in fig. 4, where R1 is equivalent to the overall resistance of the R2R resistor network 120, and the result is Uomin is:

Uomin＝Vref1×R1/(R1+R0) (22)

Vref1＝ΔUo×1024+Uomin (23)

the combinations (22) and (23) are: uomin=Δuo× (1024×r1/R0) (24)

Combining (14) and (24) there are: r0 is larger than or equal to 1024×R1/300 and is smaller than or equal to 1024×R1/227

Obtaining 3.413R1R 0 is less than or equal to 4.511R1 (25)

R0 may take the integer value 4R1 in view of resistance matching.

From (22), the minimum voltage value uomin=vref 1/5 (26) of the analog voltage signal at this time is obtained

If the first reference voltage Vref1 is 2.7V, combining (23) and (26), there are:

2.7×4/5＝ΔUo×1024 (27)

the adjustment step of the digital to analog conversion circuit of 10 bits here Δuo=2.7×0.8/1024=2.11 mV.

In other words, the same first reference voltage Vref1 is input, and the accuracy of the output analog voltage signal can be effectively improved by the voltage dividing resistor R0 and the conversion network 100.

In the embodiment of fig. 5, the input terminal of the second operational amplifier circuit is connected to the second reference voltage input terminal of the digital-to-analog conversion circuit, the output terminal of the second operational amplifier circuit is connected to the voltage offset circuit 200 as the second reference voltage terminal, and at the same time, the voltage dividing resistor is connected between the first reference voltage terminal and the analog voltage output terminal. In other words, by inputting the additional second reference voltage Vref2 and the voltage dividing resistor R0, the rising speed of the analog voltage signal initially output by the digital-to-analog converter can be further increased, so that the purpose of increasing the adjustment step under the same input of the first reference voltage Vref1 can be achieved, and the adjustment accuracy of the digital-to-analog converter can be further improved.

In the embodiment of fig. 2, a filtering unit is disposed between the analog voltage output end and the conversion network 100, the filtering unit includes a filtering resistor R2 and a filtering capacitor C1, one end of the filtering resistor R2 is connected to a connection point between the first resistor and the second resistor at the end, the other end of the filtering resistor R2 is connected to the analog voltage output end, the connection point between the filtering resistor R2 and the analog voltage output end is connected to one end of the filtering capacitor C1, and the other end of the filtering capacitor C1 is grounded.

The present disclosure provides a digital-to-analog conversion chip, which includes a housing, a digital-to-analog conversion circuit encapsulated in the housing, and pins exposed through the housing, where the digital-to-analog conversion circuit is the digital-to-analog conversion circuit of any one of the above embodiments, and an external connection end of the digital-to-analog conversion circuit is connected with the corresponding pin.

In other words, in the case that the digital-to-analog conversion chip uses the digital-to-analog conversion circuit, the accuracy of the analog voltage signal output by the digital-to-analog conversion chip can be effectively improved.

The present disclosure provides an electronic device, such as a digital-to-analog conversion circuit of any one of the above embodiments, or including a digital-to-analog conversion chip of any one of the above embodiments.

In other words, in the case where the electronic device uses the digital-to-analog conversion circuit or the digital-to-analog conversion chip, the accuracy of the analog voltage signal output by the electronic device can be effectively improved.

While certain specific embodiments of the utility model have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the utility model. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the utility model. The scope of the utility model is defined by the appended claims.

Claims (11)

1. A digital-to-analog conversion circuit, comprising:

the conversion network is connected between a first reference voltage end of the digital-to-analog conversion circuit and an analog voltage output end of the digital-to-analog conversion circuit, and outputs an analog voltage signal mapped with an input digital signal through the analog voltage output end; the method comprises the steps of,

and the voltage offset circuit is connected with the analog voltage output end and generates a set voltage offset at the analog voltage output end.

2. The digital-to-analog conversion circuit according to claim 1, wherein the conversion network comprises a resistor network and a switch network connected with the resistor network, the switch states of the switch network are mapped with the digital signals, and the conversion network has a plurality of circuit structures corresponding to a plurality of switch states one by one; at least a portion of the resistance of the voltage offset circuit is the resistance of the resistor network.

3. The digital to analog conversion circuit of claim 1, further comprising a first operational amplifier circuit having an input coupled to a first reference voltage input of the digital to analog conversion circuit, an output coupled to the conversion network as the first reference voltage.

4. The digital to analog conversion circuit of claim 2, wherein the voltage offset circuit is connected between a second reference voltage terminal of the digital to analog conversion circuit and the analog voltage output terminal.

5. The digital to analog conversion circuit of claim 4, further comprising a second operational amplifier circuit, an input of the second operational amplifier circuit being coupled to a second reference voltage input of the digital to analog conversion circuit, an output of the second operational amplifier circuit being coupled to the voltage offset circuit as the second reference voltage terminal.

6. The digital to analog conversion circuit of claim 5, wherein the resistor network is an R2R resistor network, the resistor network comprising a plurality of first resistors and a plurality of second resistors having a resistance value that is 2 times a resistance value of the first resistors, the voltage offset circuit comprising the plurality of first resistors of the R2R resistor network.

7. The digital to analog conversion circuit of claim 6, wherein a plurality of first resistors of the R2R resistor network are connected in sequence, wherein a second end of a previous first resistor is connected to a first end of a next first resistor, a second end of a terminal first resistor is connected to the analog voltage output terminal, a first end of a terminal first resistor is connected to the switch network through a first second resistor in a first branch, and a second end of a terminal first resistor is connected to the second reference voltage input terminal through a second resistor;

the voltage offset circuit includes the second resistor and the plurality of first resistors.

8. The digital to analog conversion circuit of claim 2, wherein the voltage offset circuit is connected between the first reference voltage terminal and the analog voltage output terminal.

9. The digital to analog conversion circuit of claim 8, wherein the resistor network is an R2R resistor network, the voltage offset circuit comprises a divider resistor and the conversion network, the divider resistor is connected between the first reference voltage terminal and the analog voltage output terminal.

10. The digital-to-analog conversion chip is characterized by comprising a shell, a digital-to-analog conversion circuit packaged in the shell and pins exposed through the shell, wherein the digital-to-analog conversion circuit is the digital-to-analog conversion circuit according to any one of claims 1 to 9, and an external connecting end of the digital-to-analog conversion circuit is connected with the corresponding pins.

11. An electronic device comprising the digital-to-analog conversion circuit of any one of claims 1 to 9 or the digital-to-analog conversion chip of claim 10.