CN116800272A - High-speed sectional digital-to-analog conversion circuit, electronic circuit and electronic equipment - Google Patents

High-speed sectional digital-to-analog conversion circuit, electronic circuit and electronic equipment Download PDF

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Publication number
CN116800272A
CN116800272A CN202310843804.7A CN202310843804A CN116800272A CN 116800272 A CN116800272 A CN 116800272A CN 202310843804 A CN202310843804 A CN 202310843804A CN 116800272 A CN116800272 A CN 116800272A
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China
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low
resistor
current source
current
order
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Inventor
丁齐兵
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Guangdong Hongyixin Automobile Electronic Technology Co ltd
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Guangdong Hongyixin Automobile Electronic Technology Co ltd
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Priority to CN202310843804.7A priority Critical patent/CN116800272A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators

Abstract

The invention provides a high-speed sectional digital-to-analog conversion circuit, an electronic circuit and an electronic device, which are used for converting a digital signal into a first analog voltage, wherein the digital signal consists of low L bits and high M bits, and the circuit comprises: the low-order conversion module comprises a first low-order conversion unit formed by a current source array, a corresponding second resistor, a second low-order conversion unit formed by the current source array and a corresponding third resistor; the first low-order conversion unit and the second low-order conversion unit are respectively used for respectively exciting the second resistor and the third resistor according to the low L-order numerical value of the digital signal so as to output a second analog voltage and a third analog voltage; the high-order conversion module is used for outputting a first analog voltage according to the high M-order numerical value of the digital signal under the excitation of a voltage source; the first analog voltage is a voltage obtained by adding the second analog voltage to the third analog voltage and adding the voltages at two ends of the high-order conversion module.

Description

High-speed sectional digital-to-analog conversion circuit, electronic circuit and electronic equipment
Technical Field
The present invention relates to the field of digital-to-analog converters, and in particular, to a high-speed segmented digital-to-analog conversion circuit, an electronic circuit, and an electronic device
Background
Digital-to-analog conversion circuits are widely used in the field of integrated circuits and are an important bridge linking the digital world and the analog world. In order to improve the output accuracy of the digital-to-analog converter, there are several approaches; 1) The device size of the digital-to-analog conversion circuit is increased, but the area of the chip and the bit number of the digital-to-analog conversion circuit are in an exponential relation; when the number of bits is greater than 10, the cost of the chip is greatly increased by increasing the device size only to improve the precision; 2) Calibrating the matching device; the scheme firstly has complex technology, increases the design period, and secondly, the performance of the calibrated device can change according to the process, voltage and temperature (process, voltage, temperature-PVT) changes and is unstable. In order to have a good tradeoff between chip area and output accuracy, one skilled in the art will typically choose a segmented digital-to-analog converter.
Referring to fig. 1, the basis for determining the conversion speed is: the larger R is, the slower the conversion speed of the digital-to-analog conversion circuit is; conversely, the faster; wherein R is used to characterize the equivalent resistance of the voltage output with respect to ac ground and C is used to characterize the load capacitance at the voltage output. The segmented digital-to-analog conversion circuit in the prior art generally adopts a high-order conversion module which is connected in series with small resistors, and a low-order conversion module which is connected in series with large resistors and connected in parallel with the large resistors connected in series with the small resistors; when the analog voltage is selected to be output at the middle position of the series large resistor, the equivalent resistor of the output point relative to the ground terminal is increased, so that the conversion speed of the segmented digital-to-analog conversion circuit is greatly reduced; meanwhile, the parallel connection of the small resistance network of the high-order conversion module and the large resistance network of the low-order conversion module affects the equivalent resistance of the whole circuit, so that the actual voltage obtained by the high-order conversion module after parallel connection is different from an ideal value, and further the voltage output by the segmented digital-to-analog conversion circuit is deviated, and the Integral Nonlinearity (INL) and the Differential Nonlinearity (DNL) of the circuit are affected.
Disclosure of Invention
The invention provides a high-speed sectional digital-to-analog conversion circuit, an electronic circuit and electronic equipment, which are used for realizing the high-speed high-linearity sectional digital-to-analog conversion circuit on the basis of small chip area.
According to a first aspect of the present invention, a high-speed segmented digital-to-analog conversion circuit is provided for converting a first digital signal into a first analog voltage; wherein, the first digital signal comprises low order and high order, wherein the digit of low order is L, the digit of high order is M, and this circuit includes:
a reference voltage source; the second end of the reference voltage source is grounded, and the reference voltage source is used for outputting a reference voltage;
a low-order conversion module; the low-order conversion module comprises a first low-order conversion unit and a second low-order conversion unit; the first low-order conversion unit comprises a first current source array and a second resistor; the second low-order conversion unit comprises a second current source array and a third resistor; wherein:
the output end of the first current source array is coupled to the second end of the second resistor, the input end of the first current source array is connected with the power end, and the first current source array is used for outputting a first conversion current according to the low L-bit value of the first digital signal; the first end of the second resistor is coupled to the first end of the reference voltage source, and the second resistor is used for generating a second analog voltage according to the first conversion current;
the output end of the second current source array is coupled to the first end of the third resistor, the input end of the second current source array is connected with the power end, and the second current source array is used for outputting a second conversion current according to the low L-bit value of the first digital signal; the second end of the third resistor is grounded, and the third resistor is used for generating a third analog voltage according to the second conversion current;
a high-order conversion module, wherein a first end and a second end of the high-order conversion module are respectively coupled to a second end of the second resistor and a first end of the third resistor; the high-order conversion module is used for outputting the first analog voltage according to the high-order M-bit value of the first digital signal and the reference voltage, wherein the first analog voltage is obtained by adding the voltage at two ends of the high-order conversion module to the second analog voltage and the third analog voltage; wherein M and L are integers, M is more than or equal to 1, and L is more than or equal to 1.
Optionally, the first current source array comprises (2 L -1) a first current source and (2 L -1) a first low-level switch;
the output end of each first current source is coupled to the second end of the second resistor through the first low-level switch; the input end of each first current source is connected with the power supply end; wherein the first current source and the first low-level switch are in one-to-one correspondence; the current output by each first current source is equal;
each first low-level switch controls the on and off of the first current source according to the value of the low L bit of the first digital signal, and each first current source outputs first current according to the on of the corresponding first low-level switch; wherein the first switching current is the sum of all the first currents.
Optionally, the second current source array comprises (2 L -1) a second current source and (2 L -1) a second low-level switch;
the output end of each second current source is coupled to the first end of the third resistor through the second low-level switch; the input end of each second current source is connected with the power supply end; wherein the second current source and the second low-level switch are in one-to-one correspondence; the currents output by each second current source are equal;
each second low-level switch controls the closing and opening of the second low-level switch according to the value of the low L bit of the first digital signal, and each second current source outputs second current according to the closing of the corresponding second low-level switch; wherein the second switching current is the sum of all the second currents, and the second current is equal to the first current.
Optionally, the high-order conversion module includes (2 M -1) first resistors and 2 connected in series M A high-level switch;
the second end of each high-level switch is used as the output end of the high-level conversion module, and each high-level switch is used for controlling the on/off of the high-level switch according to the high-M-bit value of the first digital signal;
the first end and the second end of each first resistor are respectively coupled with the first end of the high-level switch; all the first resistors are used for outputting the first analog voltage according to the reference voltage and the closing of the high-order switch; the first analog voltage is a voltage obtained by adding the second analog voltage to the third analog voltage and adding the voltages at two ends of the high-order conversion module.
Optionally, the resistance value of the second resistor is equal to the resistance value of the third resistor.
Optionally, the parameters of the high-speed segmented digital-to-analog conversion circuit satisfy:
wherein V is ref For characterizing the reference voltage; r is used for representing the resistance value of the first resistor; r is R all The resistor is used for representing the sum of resistance values of all resistors in the high-speed segmented digital-to-analog conversion circuit; r is R lsb The resistor is used for representing the resistance value of the second resistor or the resistance value of the third resistor; i lsb For characterizing the first current or the second current.
Optionally, the high-speed segmented digital-to-analog conversion circuit further includes a fourth resistor and a fifth resistor;
the first end and the second end of the fourth resistor are respectively coupled to the second end of the second resistor and the first end of the high-order conversion module;
the first end and the second end of the fifth resistor are respectively coupled to the second end of the high-order conversion module and the first end of the third resistor.
Optionally, the high-speed segmented digital-to-analog conversion circuit further comprises a first control unit;
the first control unit is coupled to all the first low-level switches and all the second low-level switches and all the high-level switches respectively, and is used for converting the first digital signal into a first control signal and a second control signal, controlling the first control signal to close and open all the first low-level switches and all the second low-level switches respectively, and controlling the second control signal to close and open all the high-level switches; wherein the first control signal is used to characterize a set of level signals converted by the low L bits of the first digital signal; the second control signal is used to characterize a set of level signals converted by the upper M bits of the first digital signal.
Optionally, the first control unit includes a decoder.
According to a second aspect of the present invention there is provided an electronic circuit comprising the high speed segmented digital to analogue conversion circuit of the first aspect of the present invention and optionally provided.
According to a third aspect of the present invention there is provided an electronic device comprising the electronic circuit provided by the second aspect of the present invention.
Compared with the prior art that a large-resistance network is used as a small-resistance network of a low-order conversion module and a high-order conversion module to be connected in parallel, the high-speed segmented digital-to-analog conversion circuit reduces the influence of the large-resistance network on the conversion speed of the segmented digital-to-analog conversion circuit and improves the digital-to-analog conversion speed of the circuit; meanwhile, the degradation of linearity of the digital-to-analog conversion circuit caused by equivalent resistance change of the digital-to-analog conversion circuit due to the fact that the resistors are connected in parallel and the on-state resistance of the switch in the low-order conversion module is reduced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a prior art segmented digital to analog conversion circuit;
fig. 2 is a block diagram of a high-speed segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 3 is a circuit configuration diagram of a high-speed segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 4 is a circuit configuration diagram of a high-speed segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 5 is a circuit configuration diagram III of a high-speed segmented digital-to-analog conversion circuit according to an embodiment of the present invention;
fig. 6 is a circuit structure diagram of a first current source or a second current source according to an embodiment of the present invention. Description of the drawings:
a 10-low level conversion module;
11-a first low-order conversion unit;
111-a first current source array;
12-a second lower conversion unit;
121-a second current source array;
a 20-high conversion module;
vout-the first analog voltage;
vdd-power supply terminal;
vref—a reference voltage source;
r-a first resistor;
ros 1-fourth resistance;
ros 2-fifth resistance;
r1-a first resistor;
r2-a third resistor;
rlsb 1-second resistance;
rlsb 2-third resistance;
imsb-a second current source;
ilsb 1-a first current source;
ilsb 2-a second current source;
ilsb-a first low-level current source;
ilsb-i low current source;
Ilsb-L-L low current source;
an amp-amplifier;
rx-sixth resistance;
m1-a first MOS tube;
m2-a second MOS tube;
m3-third MOS tube.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Before explaining the embodiment of the invention, the design idea of the invention is briefly introduced:
in the prior art of the segmented digital-to-analog conversion circuit, the parallel connection of the small resistance network of the high-order conversion module 20 and the large resistance network of the low-order conversion module 10 is adopted to influence the equivalent resistance of the whole circuit, so that the actual voltage obtained by the high-order conversion module 20 and the low-order conversion module 10 after being connected in parallel is different from an ideal value, and further the voltage output by the segmented digital-to-analog conversion circuit is deviated, and the linearity of the segmented digital-to-analog conversion circuit is deteriorated. In the low-level conversion module 10, the on-resistance of each switch further affects the equivalent resistance of the whole circuit, and the linearity of the segmented digital-to-analog conversion circuit is deteriorated. Meanwhile, when the analog voltage is selected to be output at the middle position of the large-resistance network, the equivalent resistance of the output end relative to the ground end can be increased, so that the conversion speed of the sectional digital-to-analog conversion circuit is greatly reduced. Therefore, the key to improving the linearity and conversion speed of the segmented digital-to-analog conversion circuit is to reduce the influence of the parallel connection of the resistor network and the on-resistance of the switch on the equivalent resistance of the whole circuit, and to make the equivalent resistance of the output point relative to the ground as small as possible when the analog voltage is output at the middle position of the resistor network. The invention replaces the large resistance network of the original low-level conversion module 10 and the switch array for controlling the output voltage of the large resistance network with two groups of current source arrays and the switch array for controlling the whole output current of the current source arrays correspondingly, and the currents output by the two groups of current source arrays respectively flow through the two resistors so as to jointly realize the voltage output of the low-level conversion module 10. Because the current output by the current source array cannot be changed due to the change of the whole equivalent resistance of the circuit, the influence of the parallel connection of the resistor network and the on-resistance of the switch on the whole equivalent resistance of the circuit can be effectively avoided, and the linearity and the conversion speed of the sectional digital-to-analog conversion circuit are improved.
Referring to fig. 2, an embodiment of the present invention provides a high-speed segmented digital-to-analog conversion circuit for converting a first digital signal into a first analog voltage Vout; wherein, the first digital signal comprises low order and high order, wherein the digit of low order is L, the digit of high order is M, and this circuit includes:
a reference voltage source Vref; the second end of the reference voltage source Vref is grounded, and the reference voltage source Vref is used for outputting a reference voltage;
a low-level conversion module 10; the low-order conversion module 10 includes a first low-order conversion unit 11 and a second low-order conversion unit 12; the first low-order conversion unit 11 includes a first current source Ilsb1 array 111 and a second resistor Rlsb1; the second low-level conversion unit 12 includes a second current source Ilsb2 array 121 and a third resistor Rlsb2, specifically: the resistance value of the second resistor Rlsb1 is equal to the resistance value of the third resistor Rlsb 2; wherein:
the output end of the first current source Ilsb1 array 111 is coupled to the second end of the second resistor Rlsb1, the input end of the first current source Ilsb1 array 111 is connected to the power supply Vdd, and the first current source Ilsb1 array 111 is configured to output a first conversion current according to the low L bit value of the first digital signal; the first end of the second resistor Rlsb1 is coupled to the first end of the reference voltage source Vref, and the second resistor Rlsb1 is configured to generate a second analog voltage according to the first conversion current;
the output end of the second current source Ilsb2 array 121 is coupled to the first end of the third resistor Rlsb2, the input end thereof is connected to the power supply terminal Vdd, and the second current source Ilsb2 array 121 is configured to output a second switching current according to the low L bit value of the first digital signal; the second end of the third resistor Rlsb2 is grounded, and the third resistor Rlsb2 is configured to generate a third analog voltage according to the second switching current;
a high-level conversion module 20, wherein a first end and a second end of the high-level conversion module 20 are coupled to a second end of the second resistor Rlsb1 and a first end of the third resistor Rlsb2, respectively; the high-order conversion module 20 is configured to output the first analog voltage Vout according to the high-order value of the first digital signal and the reference voltage, where the first analog voltage Vout is a voltage obtained by adding the third analog voltage to the second analog voltage and superimposing the voltages at two ends of the high-order conversion module 20; wherein M and L are integers, M is more than or equal to 1, and L is more than or equal to 1.
Referring to fig. 3, as an embodiment, the first current source Ilsb1 array 111 includes (2 L -1) first current sources Ilsb1 and (2 L -1) a first low-level switch;
the output end of each first current source Ilsb1 is coupled to the second end of the second resistor Rlsb1 through the first low-level switch; the input end of each first current source Ilsb1 is connected with the power supply end Vdd; the first current sources Ilsb1 and the first low-level switches are in one-to-one correspondence; wherein, the current outputted by each first current source Ilsb1 is equal;
each first low-level switch controls the on and off of the first low-level switch according to the value of the low L bit of the first digital signal, and each first current source Ilsb1 outputs first current according to the on of the corresponding first low-level switch; wherein the first switching current is the sum of all the first currents.
As a kind ofIn one embodiment, the second current source Ilsb2 array 121 comprises (2 L -1) second current sources Ilsb2 and (2 L -1) a second low-level switch;
the output end of each second current source Ilsb2 is coupled to the first end of the third resistor Rlsb2 through the second low-level switch; the input end of each second current source Ilsb2 is connected with the power supply end Vdd; wherein the second current source Ilsb2 corresponds to the second low-level switch one by one; wherein, the current output by each second current source Ilsb2 is equal;
each second low-level switch controls the on and off of the second low-level switch according to the value of the low L bit of the first digital signal, and each second current source Ilsb2 outputs a second current according to the on of the corresponding second low-level switch; wherein the second switching current is the sum of all the second currents, and the second current is equal to the first current.
Referring to fig. 4, as an alternative embodiment, the first current source Ilsb1 array 111 and the second current source Ilsb2 array 121 each include a first low-level current source Ilsb-a to an L-th low-level current source Ilsb-L and a low-level switch corresponding to each low-level current source;
the input ends of the first low-level current source Ilsb-a and the L-th low-level current source Ilsb-L are coupled to the power supply terminal Vdd; wherein the current magnitude of the first low-level current source Ilsb-a is equal to the first current or the second current; from the first low-level current source Ilsb-a to the L-th low-level current source Ilsb-L, the current magnitude of each current source increases by 2 times in turn; specific: the current level of the i-th low-level current source Ilsb-i is 2 i-1 The current magnitude of the first low-order current source Ilsb-a is multiplied. The low-level switch corresponding to each low-level current source controls the on-off of the low-level switch according to the low-level L value of the first digital signal; the output end of the first low-level current source Ilsb-a to the output end of the L-th low-level current source Ilsb-L output corresponding current according to the closing of the corresponding low-level switch. The alternative embodiment has the beneficial effects of reducing the number of current sources to reduceSmall chip area and low production cost.
Referring to fig. 3, as an embodiment, the high-order conversion module 20 includes (2 M -1) first resistors R and 2 connected in series M A high-level switch;
the second end of each high-level switch is used as an output end of the high-level conversion module 20, and each high-level switch is used for controlling the on/off of the high-level switch according to the high-M-bit value of the first digital signal;
the first end and the second end of each first resistor R are respectively coupled with the first end of the high-level switch; all the first resistors R are used for outputting the first analog voltage Vout according to the reference voltage and the closing of the high-order switch; the voltage across the high-order conversion module 20 is superimposed on the first analog voltage Vout, which is the second analog voltage plus the third analog voltage.
As a specific embodiment, original 2 M High-order switches connected in parallel, i.e. 2 M The parallel single-stage decoding switches may also be changed into multi-stage decoding switches, which are not limited herein.
As a specific implementation manner, in order to reduce the differential nonlinearity of the segmented digital-to-analog conversion circuit provided by the embodiment of the present invention, the parameters of the high-speed segmented digital-to-analog conversion circuit satisfy:
wherein V is ref For characterizing the reference voltage; r is used for representing the resistance value of the first resistor R; r is R all The resistor is used for representing the sum of resistance values of all resistors in the high-speed segmented digital-to-analog conversion circuit; r is R lsb The resistor value of the second resistor Rlsb1 or the resistor value of the third resistor Rlsb2 is used for representing; i lsb For characterizing the first current or the second current. That is, when the reference voltage source Vref applies excitation to a single first resistor r=the first low-order switch is closed, the first current source Ilsb1 array 111 is dividedWhen the sum of the excitations applied to the second resistor Rlsb1 and the third resistor Rlsb2 and the second low-level switch are both closed, the second current source Ilsb2 array 121 applies the sum of the excitations applied to the second resistor Rlsb1 and the third resistor Rlsb2, respectively.
Referring to fig. 5, as a specific embodiment, the high-speed segmented digital-to-analog conversion circuit further includes a fourth resistor Ros1 and a fifth resistor Ros2;
the first end and the second end of the fourth resistor Ros1 are coupled to the second end of the second resistor Rlsb1 and the first end of the high-level conversion module 20, respectively;
the first and second ends of the fifth resistor Ros2 are coupled to the second end of the high-level conversion module 20 and the first end of the third resistor Rlsb2, respectively. The sum of the excitation applied by the reference voltage source Vref to the fourth resistor Ros1 and the fifth resistor Ros2 is a fixed dc bias voltage of the high-speed segmented digital-to-analog conversion circuit, and the fixed dc bias voltage is also superimposed in the first analog voltage Vout output by the high-level conversion module 20 to be used as a starting voltage of the first analog voltage Vout. For example, when the high-order value and the low-order value of the first digital signal are zero, the voltages at the two ends of the second analog voltage, the third analog voltage and the high-order conversion module 20 are equal to zero, and then the first analog voltage Vout is equal to the fixed dc bias voltage; the formula of the fixed DC bias voltage is as follows:
wherein; r is R all For characterizing the sum of all said first resistances R.
Referring to fig. 6, as a specific embodiment, the specific structure of the first current source Ilsb1 or the second current source Ilsb2 is: comparator amp, first MOS pipe M1, second MOS pipe M2, third MOS pipe M3, sixth resistance Rx.
The reference voltage is input to the non-inverting input end of the comparator amp; the first end of the sixth resistor Rx is connected with the inverting input end of the comparator amp; the output end of the comparator amp is connected with the grid electrode of the first MOS tube M1;
the first end of the first MOS tube M1 is connected with the first end of the sixth resistor Rx, and the second end of the first MOS tube M2 is connected with the second end of the second MOS tube;
the second MOS tube M2 and the third MOS tube M3 form a current mirror; the grid electrode of the second MOS tube M2 is respectively connected with the second end of the second MOS tube M2 and the grid electrode of the third MOS tube M3; the first end of the second MOS tube M2 and the first end of the third MOS tube M3 are both connected with the power supply end Vdd; the second end of the third MOS transistor M3 is used as an output end of the first current source Ilsb1 or the second current source Ilsb2, and outputs the first current or the second current; wherein the formula of the first current or the second current is:
wherein M is used for representing the ratio of the width-to-length ratio of the third MOS tube M3 to the width-to-length ratio of the second MOS tube M2; r is R x And the resistance value of the sixth resistor is used for representing.
As a specific embodiment, the segmented digital-to-analog conversion circuit further includes a first control unit;
the first control unit is coupled to all the first low-level switches and all the second low-level switches and all the high-level switches respectively, and is used for converting the first digital signal into a first control signal and a second control signal, controlling the first control signal to close and open all the first low-level switches and all the second low-level switches respectively, and controlling the second control signal to close and open all the high-level switches; wherein the first control signal is used to characterize a set of level signals converted by the low L bits of the first digital signal; the second control signal is used to characterize a set of level signals converted by the upper M bits of the first digital signal. Specific: the first control unit includes a decoder. Of course, the first control unit may be other devices capable of converting the digital signal into a corresponding level signal, which is not limited herein.
Taking the first digital signal as 6 bits, the first 3 bits of the first digital signal as low bits, and the last 3 bits as high bits as examples, the working flow of the high-speed segmented digital-to-analog conversion circuit provided by the embodiment of the invention is introduced:
the first digital signal is 111010, but may be any other 6-bit binary number, which is not limited herein. The first control unit converts 111010 into the first control signal and the second control signal; wherein the first control signal is used to characterize the set of level signals converted by 010 and the second control signal is used to characterize the set of level signals converted by 111.
The first control signals are used for respectively controlling the on and off of all the first low-level switches and all the second low-level switches; specifically, the first control signal controls all the first low-level switches, wherein the first low-level switch is closed to the second low-level switch, and the third low-level switch is opened to the seventh low-level switch; the first switching current output by the first current source Ilsb1 array 111 via all of the first low-side switches is equal to 2 times the first current; however, this is limited to the first current source Ilsb1 array 111 including 7 first current sources Ilsb1 having equal current, if the first current source Ilsb1 array 111 including the first to third low-level current sources Ilsb-a to Ilsb-a having current values of each current source sequentially increasing by 2 times in the first current source Ilsb1 array 111, only the low-level switch corresponding to the second low-level current source is closed, and the low-level switches corresponding to the first and third low-level current sources are opened. Meanwhile, the first control signal also controls all the second low-level switches, wherein the first second low-level switch is closed to the second low-level switch, and the third second low-level switch is opened to the seventh low-level switch; then the second switching current output by the second current source Ilsb2 array 121 via all of the second low-side switches is equal to 2 times the second current; however, this is limited to the second current source Ilsb2 array 121 including 7 second current sources Ilsb2 having equal current, if the second current source Ilsb2 array 121 includes first to third low-level current sources Ilsb-a to Ilsb-a each of which has a current level sequentially increased by 2 times, only the low-level switch corresponding to the second low-level current source is turned on, and the low-level switches corresponding to the first and third low-level current sources Ilsb-a are turned off. When the voltage drops of the second resistor Rlsb1 and the third resistor Rlsb2 relative to the ground are the same, so that the voltage drop across the upper conversion module 20 is 0, and no current flows, the currents output by the first current source Ilsb1 and the second current source Ilsb2 array 111 flow to the second resistor Rlsb1 and the third resistor Rlsb2 respectively, and therefore, the voltage drop across the first resistor Rlsb1 and the third resistor Rlsb2 array 121 is 2 times the second current or the product of the second current and the third resistor Rlsb1 or the third resistor Rlsb2, because the second resistor Rlsb1, the upper conversion module 20, and the third resistor Rlsb2 have a symmetrical structure relative to the ground.
The second control signal is used for controlling the on and off of all the high-level switches; specifically, the second control signal controls the 8 th high-level switch from the ground end far away from the reference voltage source Vref to be closed in all the high-level switches, and the other high-level switches are all opened; the voltage at the two ends of the high-order conversion module 20 is equal to the product of the reference voltage and 7 times of the resistance R of the first resistor, and then divided by the resistance of the whole equivalent resistor of the circuit; wherein the resistance of the equivalent resistor of the circuit is equal to =the resistance of the second resistor Rlsb 1+the resistance of the third resistor Rlsb 2+the resistance of the fourth resistor Ros 1+the resistance of the fifth resistor Ros 2+ (2) M -1) times the first resistanceResistance value of R.
If the fourth resistor Ros1 and the fifth resistor Ros2 are not set at this time, that is, the first analog voltage Vout is not superimposed with the fixed dc bias voltage, the first analog voltage Vout output by the high-level conversion module 20 is equal to 2 times the second current or the product of the first current and the resistance value of the second resistor Rlsb1 or the resistance value of the third resistor Rlsb 2+the product of the reference voltage and the resistance value of the first resistor Rlsb 7 times, and then divided by the resistance value of the circuit overall equivalent resistor.
The high-speed segmented digital-to-analog conversion circuit provided by the invention has the beneficial effects that:
1. high linearity and high switching speed: the invention replaces the large resistance network of the original low-level conversion module 10 and the switch array for controlling the output voltage of the large resistance network with two groups of current source arrays and the switch array for controlling the whole output current of the current source arrays correspondingly, and the currents output by the whole of the two groups of current source arrays respectively flow through the two resistors so as to jointly realize the voltage output of the low-level conversion module 10, because the current output by the current source arrays cannot be changed due to the change of the whole equivalent resistance of the circuit, the influence of the parallel connection of the resistance network and the on resistance of the switch on the whole equivalent resistance of the circuit can be effectively avoided, and the linearity and the conversion speed of the sectional digital-to-analog conversion circuit are improved.
The embodiment of the invention also provides an electronic circuit which comprises the high-speed segmented digital-to-analog conversion circuit.
The embodiment of the invention also provides electronic equipment comprising the electronic circuit.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (11)

1. A high-speed sectional digital-to-analog conversion circuit is used for converting a first digital signal into a first analog voltage; wherein, the first digital signal comprises low order and high order, wherein the digit of low order is L, the digit of high order is M, its characterized in that, this circuit includes:
a reference voltage source; the second end of the reference voltage source is grounded, and the reference voltage source is used for outputting a reference voltage;
a low-order conversion module; the low-order conversion module comprises a first low-order conversion unit and a second low-order conversion unit; the first low-order conversion unit comprises a first current source array and a second resistor; the second low-order conversion unit comprises a second current source array and a third resistor; wherein:
the output end of the first current source array is coupled to the second end of the second resistor, the input end of the first current source array is connected with the power end, and the first current source array is used for outputting a first conversion current according to the low L-bit value of the first digital signal; the first end of the second resistor is coupled to the first end of the reference voltage source, and the second resistor is used for generating a second analog voltage according to the first conversion current;
the output end of the second current source array is coupled to the first end of the third resistor, the input end of the second current source array is connected with the power end, and the second current source array is used for outputting a second conversion current according to the low L-bit value of the first digital signal; the second end of the third resistor is grounded, and the third resistor is used for generating a third analog voltage according to the second conversion current;
a high-order conversion module, wherein a first end and a second end of the high-order conversion module are respectively coupled to a second end of the second resistor and a first end of the third resistor; the high-order conversion module is used for outputting the first analog voltage according to the high-order M-bit value of the first digital signal and the reference voltage, wherein the first analog voltage is obtained by adding the voltage at two ends of the high-order conversion module to the second analog voltage and the third analog voltage; wherein M and L are integers, M is more than or equal to 1, and L is more than or equal to 1.
2. The high-speed segmented digital-to-analog conversion circuit of claim 1, wherein said first current source array comprises (2 L -1) a first current source and (2 L -1) a first low-level switch;
the output end of each first current source is coupled to the second end of the second resistor through the first low-level switch; the input end of each first current source is connected with the power supply end; wherein the first current source and the first low-level switch are in one-to-one correspondence; the current output by each first current source is equal;
each first low-level switch controls the on and off of the first current source according to the value of the low L bit of the first digital signal, and each first current source outputs first current according to the on of the corresponding first low-level switch; wherein the first switching current is the sum of all the first currents.
3. The high-speed segmented digital-to-analog conversion circuit of claim 2, wherein said second current source array comprises (2 L -1) a second current source and (2 L -1) a second low-level switch;
the output end of each second current source is coupled to the first end of the third resistor through the second low-level switch; the input end of each second current source is connected with the power supply end; wherein the second current source and the second low-level switch are in one-to-one correspondence; the currents output by each second current source are equal;
each second low-level switch controls the closing and opening of the second low-level switch according to the value of the low L bit of the first digital signal, and each second current source outputs second current according to the closing of the corresponding second low-level switch; wherein the second switching current is the sum of all the second currents, and the second current is equal to the first current.
4. A high-speed segmented digital-to-analog conversion circuit according to claim 3, wherein said high-order conversion module comprises (2 M -1) first resistors and 2 connected in series M A high-level switch;
the second end of each high-level switch is used as the output end of the high-level conversion module, and each high-level switch is used for controlling the on/off of the high-level switch according to the high-M-bit value of the first digital signal;
the first end and the second end of each first resistor are respectively coupled with the first end of the high-level switch; all the first resistors are used for outputting the first analog voltage according to the reference voltage and the closing of the high-order switch; the first analog voltage is a voltage obtained by adding the second analog voltage to the third analog voltage and adding the voltages at two ends of the high-order conversion module.
5. The high-speed segmented digital-to-analog conversion circuit according to claim 4, wherein a resistance value of the second resistor is equal to a resistance value of the third resistor.
6. The circuit of any one of claims 1 to 5, wherein the parameters of the circuit satisfy:
wherein V is ref For characterizing the reference voltage; r is used for representing the resistance value of the first resistor; r is R all The resistor is used for representing the sum of resistance values of all resistors in the high-speed segmented digital-to-analog conversion circuit; r is R lsb The resistor is used for representing the resistance value of the second resistor or the resistance value of the third resistor; i lsb For characterizing the first current or the second current.
7. The high-speed segmented digital-to-analog conversion circuit of claim 6, further comprising a fourth resistor and a fifth resistor;
the first end and the second end of the fourth resistor are respectively coupled to the second end of the second resistor and the first end of the high-order conversion module;
the first end and the second end of the fifth resistor are respectively coupled to the second end of the high-order conversion module and the first end of the third resistor.
8. The high-speed segmented digital to analog conversion circuit of claim 7, further comprising a first control unit;
the first control unit is coupled to all the first low-level switches and all the second low-level switches and all the high-level switches respectively, and is used for converting the first digital signal into a first control signal and a second control signal, controlling the first control signal to close and open all the first low-level switches and all the second low-level switches respectively, and controlling the second control signal to close and open all the high-level switches; wherein the first control signal is used to characterize a set of level signals converted by the low L bits of the first digital signal; the second control signal is used to characterize a set of level signals converted by the upper M bits of the first digital signal.
9. The high-speed segmented digital-to-analog conversion circuit of claim 8, wherein said first control unit comprises a decoder.
10. An electronic circuit comprising the high-speed segmented digital-to-analog conversion circuit of any one of claims 1 to 9.
11. An electronic device comprising the electronic circuit of claim 10.
CN202310843804.7A 2023-07-10 2023-07-10 High-speed sectional digital-to-analog conversion circuit, electronic circuit and electronic equipment Pending CN116800272A (en)

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CN202310843804.7A CN116800272A (en) 2023-07-10 2023-07-10 High-speed sectional digital-to-analog conversion circuit, electronic circuit and electronic equipment

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CN116800272A true CN116800272A (en) 2023-09-22

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