TW202323846A - Jtag adapter circuit board - Google Patents
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一種轉接電路板,尤其是指一種聯合測試工作群組介面轉換時可省略對訊號腳位定義核實以提高訊號傳輸效率的JTAG轉接電路板。An adapter circuit board, in particular a JTAG adapter circuit board which can omit the definition and verification of signal pins during interface conversion of a joint test workgroup to improve signal transmission efficiency.
現有的連接介面轉接電路板提供不同連接介面的轉換,在透過連接介面轉接電路板進行不同連接介面的轉換時,會因為不同連接介面對於腳位定義的不同,而需要進行訊號腳位定義的核實,進行訊號腳位定義的核實則會影響現場連接效率,除此之外,原連接介面無匹配電路也會影響到訊號傳輸的效率。The existing connection interface conversion circuit board provides the conversion of different connection interfaces. When the conversion of different connection interfaces is performed through the connection interface conversion circuit board, it is necessary to define the signal pins because of the different definitions of pins for different connection interfaces. The verification of the signal pin definition will affect the efficiency of field connection. In addition, the original connection interface without a matching circuit will also affect the efficiency of signal transmission.
綜上所述,可知先前技術中長期以來一直存在現有轉換電路板因需要進行訊號腳位定義核實影響現場連接效率且原連接介面無匹配電路也會影響到訊號傳輸效率的問題,因此有必要提出改進的技術手段,來解決此一問題。To sum up, it can be seen that the existing conversion circuit boards have long existed in the prior art because of the need for signal pin definition verification to affect the efficiency of on-site connection, and the lack of a matching circuit on the original connection interface will also affect the signal transmission efficiency. Therefore, it is necessary to propose Improved technical means to solve this problem.
有鑒於先前技術存在現有轉換電路板因需要進行訊號腳位定義核實影響現場連接效率且原連接介面無匹配電路也會影響到訊號傳輸效率的問題,本發明遂揭露一種JTAG轉接電路板,其中:In view of the problems existing in the prior art that the conversion circuit board needs to carry out signal pin definition verification to affect the field connection efficiency, and the original connection interface without a matching circuit will also affect the signal transmission efficiency, the present invention discloses a JTAG conversion circuit board, in which :
本發明所揭露的JTAG轉接電路板,其包含:具有C類型通用序列匯流排(Universal Serial Bus, USB Type-C)插槽以及聯合測試工作群組(Joint Test Action Group,JTAG)插槽的JTAG轉接電路板。The JTAG transfer circuit board disclosed by the present invention includes: a C-type universal serial bus (Universal Serial Bus, USB Type-C) slot and a joint test work group (Joint Test Action Group, JTAG) slot JTAG transfer board.
JTAG轉接電路板的C類型通用序列匯流排插槽包含有上排腳位組以及下排腳位組,上排腳位組中具有上排測試資料輸入(Test Data In,TDI)腳位、上排測試資料輸出(Test Data Out,TDO)腳位、上排測試時鐘(Test Clock,TCK)腳位、上排測試模式選擇(Test Mode Select,TMS)腳位、多個上排接地(Ground,GND)腳位,下排腳位組中具有下排測試資料輸入腳位、下排測試資料輸出腳位、下排測試時鐘腳位、下排測試模式選擇腳位以及多個下排接地腳位。The C-type universal serial bus slot of the JTAG transfer circuit board includes the upper row of pin groups and the lower row of pin groups. The upper row of pin groups has the upper row of test data input (Test Data In, TDI) pins, The upper test data output (Test Data Out, TDO) pin, the upper test clock (Test Clock, TCK) pin, the upper test mode selection (Test Mode Select, TMS) pin, multiple upper ground (Ground , GND) pins, the lower row pin group has lower row test data input pins, lower row test data output pins, lower row test clock pins, lower row test mode selection pins and multiple lower row grounding pins bit.
JTAG轉接電路板的聯合測試工作群組(Joint Test Action Group,JTAG)插槽,聯合測試工作群組插槽具有左右兩側的卡扣固定部件、防呆空槽以及十個腳位,腳位呈現上下兩排且每一排具有五個腳位,腳位中的測試時鐘腳位、測試模式選擇腳位、測試資料輸入腳位、測試資料輸出腳位以及接地腳位為固定的腳位位置。The Joint Test Action Group (JTAG) slot of the JTAG transfer circuit board, the Joint Test Action Group slot has buckle fixing parts on the left and right sides, a fool-proof empty slot, and ten pins. There are two rows up and down and each row has five pins. Among the pins, the test clock pin, test mode selection pin, test data input pin, test data output pin and ground pin are fixed pins. Location.
其中,測試時鐘腳位分別與上排測試時鐘腳位以及下排測試時鐘腳位形成電性連接,測試模式選擇腳位分別與上排測試模式選擇腳位以及下排測試模式選擇腳位形成電性連接,測試資料輸入腳位分別與上排測試資料輸入腳位以及下排測試資料輸入腳位形成電性連接,以及測試資料輸出腳位分別與上排測試資料輸出腳位以及下排測試資料輸出腳位形成電性連接,接地腳位分別與上排接地腳位以及下排接地腳位形成電性連接。Among them, the test clock pins are electrically connected to the upper test clock pins and the lower test clock pins, and the test mode selection pins are electrically connected to the upper test mode selection pins and the lower test mode selection pins respectively. The test data input pins are electrically connected to the upper row of test data input pins and the lower row of test data input pins, and the test data output pins are respectively connected to the upper row of test data output pins and the lower row of test data The output pins are electrically connected, and the grounding pins are respectively electrically connected to the upper row of grounding pins and the lower row of grounding pins.
本發明所揭露的電路板如上,與先前技術之間的差異在於透過在聯合測試工作群組插槽設計有防呆機制,藉以提供聯合測試工作群組插槽中的各訊號腳位的位置固定,在實現聯合測試工作群組介面轉換時可省略對訊號腳位定義核實以提高訊號傳輸效率。The difference between the circuit board disclosed by the present invention and the prior art is that the position of each signal pin in the joint test work group slot is fixed by designing a fool-proof mechanism in the joint test work group slot. In order to improve the signal transmission efficiency, the verification of the signal pin definition can be omitted when realizing the interface conversion of the joint test work group.
透過上述的技術手段,本發明可以達成提高聯合測試工作群組介面轉換訊號傳輸效率的技術功效。Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the transmission efficiency of the interface conversion signal of the joint test working group.
以下將配合圖式及實施例來詳細說明本發明的實施方式,藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。The implementation of the present invention will be described in detail below in conjunction with the drawings and examples, so as to fully understand and implement the implementation process of how the present invention uses technical means to solve technical problems and achieve technical effects.
以下首先要說明本發明所揭露的JTAG轉接電路板,並請參考「第1圖」所示,「第1圖」繪示為本發明JTAG轉接電路板的電路板方塊圖。The JTAG adapter circuit board disclosed by the present invention will be explained firstly below, and please refer to "Fig. 1", which is a circuit board block diagram of the JTAG adapter circuit board of the present invention.
本發明所揭露的JTAG轉接電路板,其包含:具有C類型通用序列匯流排插槽11以及聯合測試工作群組插槽12的JTAG轉接電路板10。The JTAG transfer circuit board disclosed in the present invention includes: a JTAG
請參考「第2圖」所示,「第2圖」繪示為本發明JTAG轉接電路板的C類型通用序列匯流排插槽腳位示意圖。Please refer to "Figure 2", which is a schematic diagram of the pin position of the C-type universal serial bus slot of the JTAG switching circuit board of the present invention.
JTAG轉接電路板10的C類型通用序列匯流排插槽11包含有上排腳位組111以及下排腳位組112,上排腳位組111中具有上排測試資料輸入(Test Data In,TDI)腳位1111、上排測試資料輸出(Test Data Out,TDO)腳位1112、上排測試時鐘(Test Clock,TCK)腳位1113、上排測試模式選擇(Test Mode Select,TMS)腳位1114、多個上排接地(Ground,GND)腳位1115,下排腳位組112中具有下排測試資料輸入腳位1121、下排測試資料輸出腳位1122、下排測試時鐘腳位1123、下排測試模式選擇腳位1124以及多個下排接地腳位1125。The C-type universal
上排腳位組111具有十二個腳位,上排腳位組111的腳位順序為由右至左配置,上排測試資料輸入腳位1111、上排測試資料輸出腳位1112、上排測試時鐘腳位1113、上排測試模式選擇腳位1114分別為上排腳位組111的第六腳位、第七腳位、第二腳位以及第十一腳位,上排腳位組111其餘的腳位皆為上排接地腳位1115。The
下排腳位組112具有十二個腳位,下排腳位組112的腳位順序為由左至右配置,下排測試資料輸入腳位1121、下排測試資料輸出腳位1122、下排測試時鐘腳位1123、下排測試模式選擇腳位1124分別為下排腳位組112的第六腳位、第七腳位、第二腳位以及第十一腳位,下排腳位組112其餘的腳位皆為下排接地腳位1125。The
請參考「第1圖」以及「第3圖」所示,「第3圖」繪示為本發明JTAG轉接電路板的聯合測試工作群組插槽腳位示意圖。Please refer to "Fig. 1" and "Fig. 3". "Fig. 3" is a schematic diagram of the joint test working group slot pin position of the JTAG transfer circuit board of the present invention.
JTAG轉接電路板10的聯合測試工作群組插槽12,聯合測試工作群組插槽12具有左右兩側的卡扣固定部件121、防呆空槽122以及十個腳位,腳位呈現上下兩排且每一排具有五個腳位,腳位中的測試時鐘腳位124、測試模式選擇腳位125、測試資料輸入腳位126、測試資料輸出腳位127以及接地腳位128為固定的腳位位置。The joint test
值得注意的是,聯合測試工作群組插槽12中上排的五個腳位皆為接地腳位128,聯合測試工作群組插槽12中下排的五個腳位由右至左分別為測試時鐘腳位124、測試模式選擇腳位125、測試資料輸入腳位126、測試資料輸出腳位127以及空腳位129。It is worth noting that the five pins in the upper row in the
聯合測試工作群組插槽12以及測試存取控制器的測試存取埠(Test Access Port,TAP)是以聚合物材質所製成,卡扣固定部件121以及防呆空槽122是提供給測試存取控制器的測試存取埠與聯合測試工作群組插槽12的連接固定使用,測試存取控制器的測試存取埠設置有與防呆空槽122相對應的第一凸出防呆部以及卡扣固定部件121相對應的第二凸出防呆部件,卡扣固定部件121與第二凸出防呆部件呈現相同的幾何形狀,第二凸出防呆部件的尺寸大小小於或等於卡扣固定部件121的尺寸大小,在測試存取控制器的測試存取埠插入聯合測試工作群組插槽12形成電性連接時,藉由卡扣固定部件121與第二防呆部件此此的卡扣固定以提供測試存取控制器的測試存取埠與聯合測試工作群組插槽12彼此之間的卡扣固定,以及藉由防呆空槽122以及第一凸出防呆部件的相互配合提供測試存取控制器的測試存取埠與聯合測試工作群組插槽12彼此之間的防呆插入技術功效。The joint test
測試時鐘腳位124分別與上排測試時鐘腳位1113以及下排測試時鐘腳位1123形成電性連接,測試模式選擇腳位125分別與上排測試模式選擇腳位1114以及下排測試模式選擇腳位1124形成電性連接,測試資料輸入腳位126分別與上排測試資料輸入腳位1111以及下排測試資料輸入腳位1121形成電性連接,以及測試資料輸出腳位127分別與上排測試資料輸出腳位1112以及下排測試資料輸出腳位1122形成電性連接,接地腳位128分別與上排接地腳位1115以及下排接地腳位1125形成電性連接。The
請再次參考「第1圖」所示,JTAG轉接電路板10更具有一組左右相對位置的一組定位凹槽13,定位凹槽13提供JTAG轉接電路板10與檢測機台的檢測平台的固定定位與防呆,檢測機台的檢測平台例如是以電木材質、金屬材質…等所製成,在此僅為舉例說明之,並不以此侷限本發明的應用範疇。Please refer again to "Fig. 1", the JTAG
C類型通用序列匯流排插槽提供與檢測雙列直插式記憶體模組(Dual In-line Memory Module,DIMM)插槽治具電性連接之用,聯合測試工作群組插槽提供與測試存取控制器的測試存取埠(Test Access Port,TAP)電性連接之用。The C-type universal serial bus socket is used to provide and test the electrical connection of the dual in-line memory module (Dual In-line Memory Module, DIMM) socket fixture, and the joint test work group provides and tests the socket It is used for the electrical connection of the test access port (Test Access Port, TAP) of the access controller.
綜上所述,可知本發明與先前技術之間的差異在於透過在聯合測試工作群組插槽設計有防呆機制,藉以提供聯合測試工作群組插槽中的各訊號腳位的位置固定,在實現聯合測試工作群組介面轉換時可省略對訊號腳位定義核實以提高訊號傳輸效率。In summary, it can be seen that the difference between the present invention and the prior art lies in that the position of each signal pin in the joint test work group slot is fixed by designing a fool-proof mechanism in the joint test work group slot. When implementing joint test workgroup interface conversion, the verification of signal pin definition can be omitted to improve signal transmission efficiency.
藉由此一技術手段可以來解決先前技術所存在現有轉換電路板因需要進行訊號腳位定義核實影響到訊號傳輸效率的問題,進而達成提高聯合測試工作群組介面轉換訊號傳輸效率的技術功效。This technical means can solve the problem in the prior art that the existing conversion circuit board needs to verify the signal pin definition and affect the signal transmission efficiency, so as to achieve the technical effect of improving the interface conversion signal transmission efficiency of the joint test work group.
雖然本發明所揭露的實施方式如上,惟所述的內容並非用以直接限定本發明的專利保護範圍。任何本發明所屬技術領域中具有通常知識者,在不脫離本發明所揭露的精神和範圍的前提下,可以在實施的形式上及細節上作些許的更動。本發明的專利保護範圍,仍須以所附的申請專利範圍所界定者為準。Although the embodiments disclosed in the present invention are as above, the content described above is not intended to directly limit the patent protection scope of the present invention. Anyone with ordinary knowledge in the technical field to which the present invention belongs can make some changes in the forms and details of the implementation without departing from the disclosed spirit and scope of the present invention. The scope of patent protection of the present invention must still be defined by the appended patent application scope.
10:JTAG轉接電路板 11:C類型通用序列匯流排插槽 111:上排腳位組 1111:上排測試資料輸入腳位 1112:上排測試資料輸出腳位 1113:上排測試時鐘腳位 1114:上排測試模式選擇腳位 1115:上排接地腳位 112:下排腳位組 1121:下排測試資料輸入腳位 1122:下排測試資料輸出腳位 1123:下排測試時鐘腳位 1124:下排測試模式選擇腳位 1125:下排接地腳位 12:聯合測試工作群組插槽 121:卡扣固定部件 122:防呆空槽 124:腳位中的測試時鐘腳位 125:測試模式選擇腳位 126:測試資料輸入腳位 127:測試資料輸出腳位 128:接地腳位 13:定位凹槽 10: JTAG transfer circuit board 11: Type C universal serial bus socket 111: Upper row foot group 1111: Upper test data input pin 1112: Upper test data output pin 1113: Upper row test clock pin 1114: Upper test mode selection pin 1115: Upper row ground pin 112: Lower row foot group 1121: Lower test data input pin 1122: Lower test data output pin 1123: Lower test clock pin 1124: Lower test mode selection pin 1125: Lower row ground pin 12:Joint test workgroup slot 121: buckle fixing part 122: Anti-fool empty slot 124: Test clock pins in pins 125: Test mode selection pin 126: Test data input pin 127: Test data output pin 128: Ground pin 13: positioning groove
第1圖繪示為本發明JTAG轉接電路板的電路板方塊圖。 第2圖繪示為本發明JTAG轉接電路板的C類型通用序列匯流排插槽腳位示意圖。 第3圖繪示為本發明JTAG轉接電路板的聯合測試工作群組插槽腳位示意圖。 Figure 1 is a circuit board block diagram of the JTAG adapter circuit board of the present invention. FIG. 2 is a schematic diagram of the pin position of the C-type universal serial bus socket of the JTAG switching circuit board of the present invention. FIG. 3 is a schematic diagram of the socket pins of the joint test working group of the JTAG switching circuit board of the present invention.
10:JTAG轉接電路板 10: JTAG transfer circuit board
11:C類型通用序列匯流排插槽 11: Type C universal serial bus socket
12:聯合測試工作群組插槽 12:Joint test workgroup slot
121:卡扣固定部件 121: buckle fixing part
122:防呆空槽 122: Anti-fool empty slot
13:定位凹槽 13: positioning groove
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