TWM577498U - Electronic apparatus - Google Patents

Abstract

An electronic apparatus for testing a connector on a printed circuit board (PCB) is provided. The electronic apparatus includes a processor and a test card. The processor is compatible with a processor slot of the PCB, and configured to receive first serial data from a test apparatus and transform the first serial data to first parallel data. The test card is compatible with the connector and coupled to the test apparatus. When the processor is plugged in the processor slot and the test card is plugged in the connector, the processor is further configured to send the first parallel data toward the test card through the connector. The first parallel data is transformed to second serial data according to a connection status of the connector and the test card, and the second serial data is sent back to the test apparatus.

Description

Electronic device

The present invention relates to a board testing technique, and more particularly to an electronic device for testing a printed circuit board.

The focus of the factory in the manufacture of printed circuit boards (PCBs) lies in the quality of the process. Therefore, it is necessary to ensure that each integrated circuit (IC), resistors, capacitors, inductors, and other electronic components on the PCB PCB soldering.

In terms of motherboards, various connectors such as Dual In-line Memory Module (DIMM) slots and Peripheral Component Interconnect Express (PCI-E) slots Whether each contact of the add-on card is normal or not directly reflects the quality of the motherboard. However, testing these slots can take a considerable amount of time. For example, the general server board will be equipped with 24 DIMM slots and 6 PCI-E slots, which can be turned on for more than 10 minutes at a time, and it is often necessary to find out the problematic slots. Reboot again. In addition, testing the slot of a motherboard can take up to several hours if you consider retesting caused by unstable test equipment.

The electronic device of the present invention is adapted to test a connector on a printed circuit board. The electronic device includes a processor and a test card. The processor is compatible with the processor socket of the printed circuit board and is configured to receive the first sequence of data from the test instrument and to convert the first sequence of data into the first parallel data. The test card is compatible with the connector and coupled to the test instrument. When the processor is inserted into the processor socket, and the test card is inserted into the connector, the processor is further configured to send the first parallel data to the connector, and the test card is configured to receive the corresponding first parallel data from the connector. The second parallel data converts the second parallel data into the second sequence data and sends the second sequence data to the test instrument.

The electronic device of another embodiment of the present invention is adapted to test a connector on a printed circuit board. The electronic device includes a processor and a test card. The processor is compatible with the processor socket of the printed circuit board and is configured to receive the first sequence of data from the test instrument and to convert the first sequence of data into the first parallel data. The test card is compatible with the connector and includes a plurality of first contact pairs, wherein each first contact pair forms a signal loop within the test card. When the processor is inserted into the processor slot, and the test card is inserted into the connector, the processor is further configured to send the first parallel data to the plurality of first contact pairs through the connector, and receive from the connector Corresponding to the second parallel data of the first parallel data, the second parallel data is converted into the second sequence data, and the second sequence data is sent to the test instrument.

The above described features and advantages of the present invention will become more apparent and understood from the following description.

The electronic device proposed by the novel creation embodiment supports a boundary scan function, and can be tested with a test instrument such as an x1149 boundary scan analyzer to test pluggable connectors and electronic devices on a printed circuit board by using JTAG technology. Test the connection status of the card, and then know the process quality of the connector, including, for example, the soldering status of each contact of the connector and the degree of engagement of the slot or the cassette. The following example will introduce an electronic device that tests a dual in-line memory module (DIMM) connector and a Peripheral Component Interconnect Express (PCI-E) connector. However, this new creation is not limited to this.

FIG. 1A is a schematic diagram of an electronic device according to an embodiment of the present invention. Referring to FIG. 1, the electronic device can be used to test the connectors 220-1, 220-2, 220-3, 220-4 on the printed circuit board 200. In this embodiment, the connectors 220-1, 220-2, 220-3, and 220-4 are respectively DIMM connectors, but the present invention is not limited thereto, and the electronic device in the novel creation embodiment may also be used. To test other various types of connectors. In addition to the connectors 220-1, 220-2, 220-3, and 220-4, the printed circuit board 200 to be tested in this embodiment further includes a processor socket 210 and an adapter 230, wherein the processor is inserted The slots 210 are electrically connected to the connectors 220-1, 220-2, 220-3, 220-4 and the adapter 230 through wires on the printed circuit board 200, but the present invention is not limited thereto.

The electronic device includes a processor 110 and test cards 120-1, 120-2, 120-3, 120-4. In the present embodiment, processor 110 is configured to be compatible with processor socket 210 on printed circuit board 200, and each test card 120-1, 120-2, 120-3, 120-4 is configured to The connectors 220-1, 220-2, 220-3, 220-4 are compatible with the printed circuit board 200. It should be noted that the novel creation does not limit the number of test cards and the connection interface, and the test card is set corresponding to the number of connectors and the connection interface on the printed circuit board to be tested.

FIG. 1B is a schematic diagram of a test card according to an embodiment of the present invention. The test card 120-1 is taken as an example in FIG. 1B, and the other test cards 120-2, 120-3, 120-4 can be deduced by analogy. Referring to FIG. 1B, the interface and shape of the test card 120-1 are designed to be compatible with the connector 220-1, and include a controller 121, a signal input terminal 122, a signal output terminal 123, and a plurality of contacts 124, wherein the signal The input terminal 122, the signal output terminal 123 and the plurality of contacts 124 are electrically connected to the controller 121 through the wiring on the test card 120-1.

Returning to FIG. 1A, test cards 120-1, 120-2, 120-3, 120-4 are coupled to test instrument 300. In this embodiment, the test instrument 300 is a JTAG test instrument supporting the boundary scan function, and includes two JTAG interfaces (for example, a first JTAG interface I1 and a second JTAG interface I2), and each JTAG interface includes test data input ( Test Data Input (TDI), Test Data Output (TDO), Test Clock (TCK), and Test Mode Selection (TMS) are four contacts.

In the present embodiment, test cards 120-1, 120-2, 120-3, 120-4 are connected in series with test instrument 300 to form a signal loop. For example, the TDO contact of the first JTAG interface I1 of the test instrument 300 is connected to the signal input end 122 of the test card 120-1, and the signal output end 123 of the test card 120-1 is connected to the test card 120-2. The signal input end 122 of the test card 120-2 is connected to the signal input end 122 of the test card 120-3, and the signal output end 123 of the test card 120-3 is connected to the signal input of the test card 120-4. End 122, and signal output 123 of test card 120-4 is a TDI contact connected to first JTAG interface I1.

In the present embodiment, the second JTAG interface I2 of the test instrument 300 is coupled to the adapter 230 of the printed circuit board 200 and, in turn, to the processor socket 210. Therefore, when the processor 110 is plugged into the processor socket 210, and the test cards 120-1, 120-2, 120-3, 120-4 are plugged into the connectors 220-1, 220-2, 220-3, At 220-4, the second JTAG interface I2, the processor 110, the respective connectors 220-1, 220-2, 220-3, 220-4 and the first JTAG interface I1 also form a signal loop. In this way, the test instrument 300 can test the various connectors 220-1, 220-2, 220-3, 220-4 through the JTAG data.

The following is described in the test mode of the connector 220-2, and the tests of the other connectors 220-1, 220-3, and 220-4 can be deduced by analogy.

The test instrument 300 first transmits a first sequence data SD1 (eg, JTAG test data) to the processor 110, and the processor 110 records the first sequence data SD1.

In this embodiment, the test instrument 300 transmits the first sequence data SD1 to the processor 110 through the second JTAG interface I2. For example, the first sequence material SD1 may include the same number of bits (for example, 64-bit) as the number of contacts (for example, 64) of the connector 220-2, but the present creation is not limited thereto.

Next, the processor 110 converts the first sequence data SD1 into a first parallel data (not shown), and then transmits the first parallel data in parallel to each of the contacts of the connector 220-2.

In this embodiment, the test instrument 300 transmits a control signal to switch the test card 120-2 to a state ready to receive data. For example, by connecting the test cards 120-1, 120-2 in series, the test instrument 300 sends a control signal to the signal input terminal 122 of the test card 120-1 through the first JTAG interface I1, and then tests the card 120-1. The signal output terminal 123 transmits the control signal to the signal input terminal 122 of the test card 120-2.

In this embodiment, the test instrument 300 then instructs the processor 110 to convert the first sequence data SD1 into the first parallel data through the second JTAG interface I2, and sends the first parallel data to the connector 220-2 in parallel. Every contact. For example, the first sequence data SD1 includes data of 64 consecutive bits transmitted by the same contact, and the first parallel data is simultaneously transmitted by spatially consecutive 64 contacts. 64-bit data, wherein the first sequence data in the first sequence data SD1 has the same bit value as the first bit value in the first parallel data, and the second time-ordered bit in the first sequence data SD1 The meta-value is the same as the second-ordered bit value in the first parallel data, and so on. Accordingly, the 64 contacts of the connector 220-2 will receive data of 64 bits of the first parallel data of 64 bits in parallel.

Since the test card 120-2 is plugged into the connector 220-2, the test card 120-2 receives the second parallel data (not shown) corresponding to the first parallel data from the connector 220-2. It is worth mentioning that if the connection between the test card 120-2 and the connector 220-2 is good, the first parallel data will be identical to the second parallel data. On the other hand, if there is a problem in the connection status between the test card 120-2 and the connector 220-2, for example, when the connection of a certain contact is poor, the bit value corresponding to the problem contact in the first parallel data is parallel to the second. The bit values in the data corresponding to the problem junction will be different.

Subsequently, the controller 121 of the test card 120-2 converts the second parallel data into the second sequence data SD2 and sends it back to the test instrument 300.

Similar to the manner in which the processor 110 converts the first sequence data SD1 into the first parallel data, in the present embodiment, the controller 121 of the test card 120-2 converts the second parallel data into the second sequence data SD2. For example, the second parallel data is a 64-bit data transmitted simultaneously by spatially consecutive 64 contacts, and the second sequence data SD2 includes a temporally consecutive 64 transmitted by the same contact. The data of one bit, wherein the first bit value of the second parallel data is the same as the first time bit of the second sequence data SD2, and the second bit of the second parallel data is the same. Same as the second bit value in the second sequence data SD2, and so on. Subsequently, the controller 121 of the test card 120-2 transmits the second sequence data SD2 to the signal input terminal 122 of the test card 120-3 through the signal output terminal 123 of the test card 120-2, and the signal output of the test card 120-3 is output. The terminal 123 then transmits the second sequence data SD2 to the signal input terminal 122 of the test card 120-4, and then the signal output terminal 123 of the test card 120-4 transmits the second sequence data SD2 back to the first JTAG interface of the test instrument 300. .

In this way, the test apparatus 300 can determine the connection state between the connector 220-2 and the test card 120-2 according to the first sequence data SD1 and the received second sequence data SD2.

In this embodiment, the test apparatus 300 can compare the first sequence data SD1 with the second sequence data SD2 to find the difference between the first sequence data SD1 and the second sequence data SD2, and the difference corresponds to the connector 220- 2 The connection between the test card 120-2 and the test card 120-2 is poor. For example, if the bit value of the first sequence data SD1 time-sorted fifth is 1 and the bit value of the second sequence data SD2 time-sorted fifth is 0, it means that the connector 220-2 is spatially ranked fifth. There may be a problem with the point.

In the above manner, multiple connectors on the printed circuit board can be tested and the contact points that may be problematic can be located without having to repeatedly plug and unplug the expansion card and reboot.

2 is a schematic diagram of an electronic device according to another embodiment of the present invention. The electronic device of the embodiment of FIG. 2 can be used to test connectors on the printed circuit board 200 for transmitting differential signals, such as PCI-E connectors, Universal Serial Bus (USB) connectors, or serial high technology. Configuration (Serial Advanced Technology Attachment, SATA) connector, etc., but the novel creation is not limited to this.

Referring to FIG. 2, the electronic device is used to test the connector 240 on the printed circuit board 200. In the present embodiment, the connector 240 is a PCI-E connector, but the present creation is not limited thereto. In addition to the connector 240, the printed circuit board 200 to be tested in this embodiment further includes a processor socket (not shown in FIG. 2) similar to the embodiment of FIG. 1A and an adapter (not shown in the figure). 2).

In this embodiment, the test instrument 300 is also a JTAG test instrument supporting boundary scan function, including a JTAG interface, and the JTAG interface includes four contacts of TDI, TDO, TCK and TMS. The test instrument 300, the processor socket 210 of the printed circuit board 200, and the adapter 230 of the printed circuit board 200 are connected to the test instrument 300, the processor socket 210 of the printed circuit board 200, and the processor socket 210 of the printed circuit board 200. The connection relationship between the adapters 230 of the printed circuit board 200 is the same, and therefore will not be described herein. In addition, the processor socket is electrically connected to the connector 240 through wiring on the printed circuit board.

The electronic device includes a processor 110 and a test card 120'. In the present embodiment, processor 110 is configured to be compatible with a processor socket on printed circuit board 200, and test card 120' is configured to be compatible with connector 240 on printed circuit board 200. It should be noted that the novel creation does not limit the number of test cards and the connection interface, and the test card is set corresponding to the number of connectors and the connection interface on the printed circuit board to be tested.

In the present embodiment, the test card 120' includes a controller 121', a changeover switch 125, a first contact pair 126, and a second contact pair 127. In detail, the connector 240 includes a plurality of pairs of contacts connected to the processor 110, but may also include at least one pair of contacts for receiving other electrical signals (eg, power signal, ground (GND) signal, and The MISC signal, etc.) is not connected to the processor 110. The first contact pair 126 in the test card 120' is disposed at a plurality of pairs of contacts connected to the processor 110 on the connector 240, and the second contact pair 127 is not connected to the processor 110 on the corresponding connector 240. At least one pair of contacts to set. For example, the leftmost first pair of second contact pairs 127 of the test card 120' of FIG. 2 (including the first and second contacts from the left side) are on the corresponding connector 240. The second pair of second contact pairs 127 (including the leftmost side) are set from the contacts for receiving the power signal and the ground signal, and counting from the leftmost side of the test card 120' of FIG. The fourth and fourth contacts are arranged corresponding to the contacts on the connector 240 for receiving the MISC signals, but the novel creation is not limited thereto.

Each first contact pair 126 forms a signal loop in the test card 120'. For example, when the connection status is normal, the processor 110 transmits a signal (eg, PCIE_TXi (i=0~n)) from a contact (eg, P _2i ) through the connector 240 to the test card 120'. The first contact is sent to one of the contacts 126, and the signal of the signal (for example, PCIE_RXi (i=0~n)) will pass through the other contact of the same first contact pair 126. Connector 240 passes back to the corresponding other contact in processor 110 (e.g., P _2i+1 ). In other words, if one of the signals is not passed back to the processor 110, it may indicate that there is a problem with the corresponding contact in the connector 240 (e.g., the contact of the corresponding processor 110 contact P _2i or P _2i+1 ).

The second contact pair 127 is coupled to the controller 121'. Since each of the second contact pairs 127 corresponds to one of the electrical signals, each contact is in a normal connection state. Will correspond to a bit value. For example, in the case that the connection state is normal, the two contacts of the second contact pair 127 corresponding to the contact of the power signal and the ground signal respectively correspond to the bit values of 1 and 0.

In this embodiment, a switch circuit 125 is disposed on the signal loop of one of the first contact pairs 126 of the test card 120'. The switch 125 is coupled to the controller 121' and can be controlled by the controller 121'. The controller 121' compares the electrical signal from the second contact pair 127 with the preset signal. If the electrical signal from the second contact pair 127 matches the preset signal, the switch 125 is turned on, and vice versa. The electrical signal from the second contact pair 127 does not match the preset signal, so that the switch 125 is not turned on. For example, the controller 121' determines whether the two contacts of the second contact pair 127 corresponding to the contact of the power signal and the ground signal respectively receive the preset signals of the bit values of 1 and 0, and if so, The switch 125 is turned on, otherwise the switch 125 is not turned on.

Accordingly, if the signal transmitted from the processor 110 to the first contact pair 126 corresponding to the switch 125 is not transmitted back to the processor 110, it may indicate that the contact of the second contact pair 127 in the connector 240 may have a problem.

The test method of the connector 240 (shown in FIG. 2) on the printed circuit board 200 will be described below. In this embodiment, the connector of the connector 240 includes a first contact (for example, corresponding to PCIE_TX0, PCIE_RX0, PCIE_TX1, PCIE_RX1, ..., PCIE_TXn, PCIE_RXn, 2n+2) and a second contact (for example, a corresponding power supply) , grounding and 4 MISC signals, wherein the first contact is a contact corresponding to the first contact pair 126 in the test card 120', and the second contact corresponds to the second in the test card 120' The contact of the contact pair 127. More specifically, the connector connected to the processor 110 on the connector 240 is the first contact, and the contact not connected to the processor 110 is the second contact. Wherein, since 2n+2 is the number of the first contacts of the connector 240, n+1 is the number of the first contact pairs 126 on the test card 120', and since 4 is the second contact on the connector 240 The number, therefore 2, is the number of second contact pairs 127 on the test card 120', but the novel creation is not limited thereto.

The test instrument 300 first transmits a first sequence data SD1 (eg, JTAG test data) to the processor 110, and the processor 110 records the first sequence data SD1.

In this embodiment, the test instrument 300 transmits the first sequence data SD1 to the processor 110 through the TDO contact of the JTAG interface. For example, the first sequence data SD1 may include n+1 bits of the same number as the first contact pair 126, such that each bit can be transmitted through one of PCIE_TXi (i=0~n) However, this new creation is not limited to this.

Next, the processor 110 converts the first sequence data SD1 into the first parallel data (not shown), and then sends the first parallel data to the connector 240 in parallel (for example, through PCIE_TXi (i=0~n)) And simultaneously receiving the second parallel data (not shown) corresponding to the first parallel data from the connector 240 (eg, through PCIE_RXi (i=0-n)).

In the present embodiment, the processor 110 defines a portion of the junction between it and the printed circuit board 200 as a transfer contact (eg, P ₀ , P ₂ . . . P _2n ) and associates it with the printed circuit board 200. Another portion of the junction between them is defined as a receiving junction (eg, for example, P ₁ , P ₃ ... P _2n+1 ). Subsequently, the processor 110 converts the first sequence material SD1 into the first parallel data of the same number of bits (eg, n+1) in a manner similar to the foregoing embodiment, and each bit of the first parallel data Transmitting from the transmitting contact through the PCIE_TXi (i=0~n) to the plurality of first contacts of the connector 240, and the bit data is from the plurality of first contacts of the connector 240 via the test card 120. After the first contact pair 260 returns to the connector 240, it is converted into the second parallel data and then transmitted back to the receiving contact of the processor 110 through the PCIE_RXi (i=0~n), and the first parallel data is parallel to the second parallel data. Differences in data will reflect contacts that may be problematic in connector 240.

In detail, one of the first contact pairs 260 of the test card 120' (for example, corresponding to the transmitting contact P _2n and the receiving contact P _2n+1 ) is provided with a switch 125 on the signal loop, so if sent to The bit data of the first contact pair 260 is not correctly returned, indicating the second contact pair 270 of the test card 120' and the second contact of the connector 240 (for example, for transmitting power, ground or MISC signals) A problem may occur in the connection between the contacts) that causes the switch 125 to be turned on by the controller 121' without being turned on.

On the other hand, in addition to the first contact pair 260 provided with the switch 125 on the signal loop, if the bit data sent to a certain first contact pair 260 is not correctly returned, it indicates that the test card 120' A problem may occur in the connection between the first contact pair 260 and the first contact on the connector 240 corresponding to the first contact pair 260 that does not correctly return the material.

Subsequently, the processor 110 converts the received second parallel data into the second sequence data SD2 and transmits it back to the test instrument 300. The manner in which parallel data is converted into sequence data has been detailed in the preceding paragraphs and will not be described here.

In this way, the test apparatus 300 can determine the connection state between the connector 240 and the test card 120' based on the first sequence data SD1 and the received second sequence data SD2.

In the above manner, it is only necessary to use a JTAG interface to test the connector for transmitting the differential signal, which saves the use of a JTAG interface better than the embodiment of FIGS. 1A and 1B.

3 is a schematic diagram of a test system in accordance with an embodiment of the present invention.

Referring to FIG. 3, the electronic device in the embodiment of FIGS. 1A, 1B, and 2 can be integrated into the test system 10, for example. The test system 10 is used for performing a boundary scan test and is embodied as a box, and includes an upper cover 11, a lower seat 12, and a pneumatic valve 13, wherein the air pressure valve 13 closes the upper cover 11 and the lower seat 12.

The printed circuit board 200 to be tested is placed in the lower seat 12, and the printed circuit board 200 may include a processor socket 210, a connector 220-i (eg, i=1 to N, N such as, but not limited to 4), and a connector 240. The connector 220-i and the connector 240 are connected to the processor socket 210 through wires on the printed circuit board, respectively.

The processor 110, the test card 120-i, and the test card 120' are all disposed on the upper cover 11, wherein the processor 110 is disposed corresponding to the processor socket 210, the test card 120-i is disposed corresponding to the connector 220-i, and the test card is The test card 120 can be plugged into the processor socket 210, and the test card 120-i can be plugged into the connector 220-i. And the test card 120' can be plugged into the connector 240.

In the present embodiment, the test instrument 300 can be connected to the adapter 230 (not shown) of the printed circuit board 200 and the test card 120-i via a line in the test system, for example, and the test instrument 300 can be powered to provide printing. The power required for the circuit board 200.

When testing, it is only necessary to close the upper cover 11 and the lower seat 12 through the air pressure valve 13, turn on the power and start the processor 110, and the test instrument 300 can use the method described in the foregoing embodiment to print the circuit board. The connector 220-i on the 200 and the connector 240 are tested and the contacts that may be problematic are located.

In summary, the electronic device proposed by the novel creation embodiment utilizes a specially designed expansion card type test card and a processor to more accurately locate a problem contact on a printed circuit board through a test instrument, and Improve test speed. In the novel authoring embodiment, the specially designed test card and processor can support the existing boundary scan function and use the JTAG interface which can only be used to test the contacts soldered on the circuit board for the printed circuit board. The connector on the connector is tested and the problem contact in the connector can be more conveniently located without multiple reboots.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.

10‧‧‧Test system

11‧‧‧Upper cover

12‧‧‧The lower seat

13‧‧‧Pneumatic valve

110‧‧‧ processor

120-1, 120-2, 120-3, 120-4, 120-i, 120'‧‧‧ test cards

121, 121’‧‧‧ controller

122‧‧‧Signal input

123‧‧‧Signal output

124‧‧‧Contacts

125‧‧‧Toggle switch

126‧‧‧ first contact pair

127‧‧‧second contact pair

200‧‧‧Printed circuit board

210‧‧‧Processor slot

220-1, 220-2, 220-3, 220-4, 220-i, 240‧‧‧ connectors

230‧‧‧Adapter

300‧‧‧Testing equipment

I1‧‧‧First JTAG interface

I2‧‧‧Second JTAG interface

P ₀ , P ₁ , P ₂ , P ₃ , P _2n , P _2n+1 ‧‧‧ processor contacts

SD1‧‧‧ first sequence data

SD2‧‧‧Second sequence data

FIG. 1A is a schematic diagram of an electronic device according to an embodiment of the present invention. FIG. 1B is a schematic diagram of a test card according to an embodiment of the present invention. 2 is a schematic diagram of an electronic device according to another embodiment of the present invention. 3 is a schematic diagram of a test system in accordance with an embodiment of the present invention.

Claims (10)

An electronic device adapted to test a connector on a printed circuit board, the electronic device comprising: a processor compatible with a processor socket of the printed circuit board and configured to receive a a sequence of data, and converting the first sequence of data into a first parallel data; and a test card compatible with the connector and coupled to the test instrument, wherein when the processor is plugged into the processor When the test card is inserted into the connector, the processor is further configured to send the first parallel data to the connector, wherein the test card is configured to receive the first parallel data from the connector. a second parallel data, the second parallel data is converted into a second sequence data, and the second sequence data is sent to the test instrument. The electronic device of claim 1, wherein the test card comprises: a signal output coupled to the test instrument; and a controller coupled to the signal output for the connector Receiving the second parallel data corresponding to the first parallel data, converting the second parallel data into the second sequence data, and outputting the second sequence data through the signal output end. The electronic device of claim 2, wherein the test card further comprises: a signal input end coupled to a signal output end of the other test card, wherein the controller is coupled to the signal input And receiving another second sequence data from the another test card, and outputting the another second sequence data through the signal output end. The electronic device of claim 1, wherein the connector is a dual in-line memory module connector. The electronic device of claim 1, wherein the first sequence of data comprises JTAG test data, and the test instrument comprises a JTAG test instrument. An electronic device adapted to test a connector on a printed circuit board, the electronic device comprising: a processor compatible with a processor socket of the printed circuit board and configured to receive a a sequence of data, and converting the first sequence of data into a first parallel data; and a test card compatible with the connector and including a plurality of first contact pairs, wherein each of the first contact pairs is Forming a signal loop in the test card, wherein when the processor is inserted into the processor socket, and the test card is inserted into the connector, the processor is further configured to pass the first parallel data through the connector Sending to the first pair of contacts, receiving a second parallel data corresponding to the first parallel data from the connector, converting the second parallel data into a second sequence data, and sending the second sequence data To the test instrument. The electronic device of claim 6, wherein the test card further comprises: a second contact pair for receiving an electrical signal; a controller coupled to the second contact pair; and a a switch, coupled to the controller, and disposed on the signal loop of one of the first contact pairs, wherein the controller is configured to connect the second contact pair to the received electrical signal The preset signals are compared, and the switch is controlled to notify the test instrument of an alignment result. The electronic device of claim 7, wherein the electrical signal comprises one of a power signal, a ground signal, and a MISC signal, or a combination thereof. The electronic device of claim 6, wherein the connector is one of a PCI-E connector, a USB connector, and a SATA connector. The electronic device of claim 6, wherein the first sequence of data comprises JTAG test data, and the test instrument comprises a JTAG test instrument.