CN209182424U - Testing tool - Google Patents
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- CN209182424U CN209182424U CN201821910889.7U CN201821910889U CN209182424U CN 209182424 U CN209182424 U CN 209182424U CN 201821910889 U CN201821910889 U CN 201821910889U CN 209182424 U CN209182424 U CN 209182424U
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Abstract
A kind of testing tool.The testing tool is suitable for the connector on testing of printed circuit board；The testing tool includes a processor and a test suite；The processor is compatible with a processor slot of the printed circuit board, and to be converted to one first panel data from test host one First ray data of reception, and by a First ray data；The test suite is compatible with the connector and is coupled to the test host, wherein when the processor is plugged in the processor slot, and when the test suite is plugged in the connector, the processor is also to be sent to the connector for first panel data, wherein the test suite is to receive one second panel data for corresponding to first panel data from the connector, second panel data is converted into one second sequence data, and second sequence data is sent to the test host.The utility model precise positioning goes out the problem contact on printed circuit board, promotes test speed, supports existing boundary scanning function.
Description
Technical field
The utility model relates to a kind of testing tools, and in particular to a kind of test work for testing of printed circuit board
Tool.
Background technique
The place that factory focuses on when manufacturing printed circuit board (Printed Circuit Board, PCB) is
Processing procedure quality, it is therefore desirable to ensure each integrated circuit (Integrated Circuit, IC) on PCB, resistance, capacitor and
The welding of the electronic components such as inductance and PCB.
For motherboard, various connector such as dual inline memory modules (Dual In-line Memory
Module, DIMM) slot and quick Peripheral Component Interconnect standard (Peripheral Component Interconnect
Express, PCI-E) whether slot etc. normal with each contact of expansion card (add-on card), also directly reflect host
The quality of plate.However, the considerable time can be expended by testing these slots.For example, the host of general server
Plate can carry 24 dimm sockets and 6 PCI-E slots, and the time being once switched on just is up to more than ten minutes, and to have found out and ask
The slot of topic generally requires to turn back on by multiple.If being resurveyed in addition, considering further that test equipment is unstable caused,
The slot for testing a motherboard will expend the time for being up to a few hours.
Accordingly, it is desirable to provide a kind of testing tool solves the above problems.
Utility model content
The testing tool of an embodiment of the present invention is suitable for a connector tested on a printed circuit board, the test
Tool includes a processor and a test suite；The processor is compatible with a processor slot of the printed circuit board, and
To be converted to one first panel data from test host one First ray data of reception, and by the First ray data；It should
Test suite is compatible with the connector and is coupled to the test host, wherein when the processor is plugged in the processor slot,
And when the test suite is plugged in the connector, the processor also first panel data is sent to the connector,
Wherein the test suite to from the connector receive correspond to first panel data one second panel data, by this second
Panel data is converted to one second sequence data, and second sequence data is sent to the test host.
The testing tool of another embodiment of the utility model is suitable for a connector on a testing of printed circuit board, the survey
Trial work tool includes a processor and a test suite；The processor is compatible with a processor slot of the printed circuit board, and
And to be converted to one first panel data from test host one First ray data of reception, and by the First ray data；
The test suite is compatible with the connector and including multiple first contact pair, wherein respectively first contact is in the test suite
One signal circuit of interior formation, wherein when the processor is plugged in the processor slot, and the test suite is plugged in the connection
When device, the processor is also to pass through the connector to those first contacts to transmission, from the connection for first panel data
Device receives the second panel data for corresponding to first panel data one, which is converted to one second sequence number
According to, and second sequence data is sent to the test host.
The testing tool that the utility model embodiment is proposed, using the test suite of the expansion card form of special designing with
And processor, the problem contact on printed circuit board can be more accurately oriented by test host, and promote test
Speed.In the utility model embodiment, the test suite and processor of special designing can support existing boundaries to scan function
Can, and the jtag interface for being welded contact on circuit boards using test is traditionally only capable of, to be directed on printed circuit board
The contact of connector is tested, and can conveniently be oriented the problems in connector without multiple turning back on and be connect
Point.
In order to make the above-mentioned features and advantages of the utility model more obvious and understandable, special embodiment below, and appended by cooperation
Attached drawing is described in detail below.
Detailed description of the invention
Figure 1A is painted the schematic diagram of the testing tool of an embodiment of the present invention.
Figure 1B is painted the schematic diagram of the test suite of an embodiment of the present invention.
Fig. 2 is painted the schematic diagram of the testing tool of another embodiment of the utility model.
Fig. 3 is painted the schematic diagram of the test macro of an embodiment of the present invention.
Primary clustering symbol description:
10 test macros
11 upper covers
12 lower seats
13 air pressure valves
110 processors
120-1,120-2,120-3,120-4,120-i, 120 ' test suites
121,121 ' controller
122 signal input parts
123 signal output ends
124 contacts
125 switching switches
126 first contacts pair
127 second contacts pair
200 printed circuit boards
210 processor slots
220-1,220-2,220-3,220-4,220-i, 240 connectors
230 adapters
300 test hosts
The first jtag interface of I1
The second jtag interface of I2
P0、P1、P2、P3、P2n、P2n+1Processor contact
SD1 First ray data
The second sequence data of SD2
Specific embodiment
The testing tool that the utility model embodiment is proposed supports boundary scan (boundary scan) function, can
Collocation x1149 boundary scan analysis instrument etc. tests host to utilize pluggable company on JTAG technical testing printed circuit board
The connection status of the test suite in device and testing tool is connect, and then learns the processing procedure quality of connector, for example including connector
The welding situation and slot of each contact or the conjugation grade of trip etc..Following embodiment will be with dual-in-line memories mould
Block (Dual In-line Memory Module, DIMM) connector and quick Peripheral Component Interconnect standard (Peripheral
Component Interconnect Express, PCI-E) testing tool of connector is introduced, but the utility model is simultaneously
It is without being limited thereto.
Figure 1A is painted the schematic diagram of the testing tool of an embodiment of the present invention.Fig. 1 is please referred to, testing tool can be used for
Connector 220-1,220-2,220-3,220-4 on testing of printed circuit board 200.In the present embodiment, connector 220-1,
220-2,220-3,220-4 are DIMM connector respectively, but the utility model is not limited to this, in the utility model embodiment
Testing tool can also be used to test other various types of connectors.In addition to connector 220-1,220-2,220-3,220-4
Except, it on printed circuit board 200 to be measured further include processor slot 210 and adapter 230 in the present embodiment, wherein handling
Device slot 210 is electrically connected by the wiring (trace) on printed circuit board 200 in connector 220-1,220-2,220-
3,220-4 and adapter 230, but the utility model is not limited to this.
Testing tool includes processor 110 and test suite 120-1,120-2,120-3,120-4.In the present embodiment
In, processor 110 is configured to the processor slot 210 being compatible on printed circuit board 200, and each test suite 120-
1,120-2,120-3,120-4 be configured to the connector 220-1,220-2 being compatible on printed circuit board 200,220-3,
220-4.It should be noted that the utility model is not intended to limit the quantity and connecting interface of test suite, test suite is corresponding
It is configured in the quantity of the connector on printed circuit board to be measured with connecting interface.
Figure 1B is painted the schematic diagram of the test suite of an embodiment of the present invention.It is with test suite 120-1 in Figure 1B
Example is illustrated, and 120-2,120-3,120-4 can the rest may be inferred other test suites.Please refer to Figure 1B, test suite
The interface and shape of 120-1 is all designed as being compatible with connector 220-1, and including controller 121, signal input part 122, letter
Number output end 123 and multiple contacts 124, wherein signal input part 122, signal output end 123 and multiple contacts 124 are all logical
The wiring crossed on test suite 120-1 is electrically connected at controller 121.
Figure 1A is gone back to, test suite 120-1,120-2,120-3,120-4 are coupled to test host 300.In this implementation
In example, test host 300 is the jtag test host for supporting boundary-scan function, and including two jtag interfaces (for example, the
One jtag interface I1 and the second jtag interface I2), each jtag interface include test data input (Test Data Input,
TDI), test data output (Test Data Output, TDO), test clock (Test Clock, TCK) and test pattern
Select (Test Mode Selection, TMS) four contacts.
In the present embodiment, test suite 120-1,120-2,120-3,120-4 and test host 300 are to be connected in series
To form a signal circuit.For example, the TDO contact for testing the first jtag interface I1 of host 300 is to be connected to test
The signal output end 123 of the signal input part 122 of component 120-1, test suite 120-1 is connected to test suite 120-2
Signal input part 122, the signal output end 123 of test suite 120-2 are the signal input parts for being connected to test suite 120-3
The signal output end 123 of 122, test suite 120-3 are the signal input parts 122 for being connected to test suite 120-4, and are tested
The signal output end 123 of component 120-4 is the TDI contact for being connected to the first jtag interface I1.
In the present embodiment, the second jtag interface I2 for testing host 300 is connected to the adapter of printed circuit board 200
230, and then it is connected to processor slot 210.Therefore, when processor 110 is plugged in processor slot 210, and test suite
When 120-1,120-2,120-3,120-4 are plugged in connector 220-1,220-2,220-3,220-4, the second jtag interface I2,
Processor 110, each connector 220-1,220-2,220-3,220-4 and the first jtag interface I1 also will form a signal
Circuit.In this way, test host 300 just and can be tested by JTAG data each connector 220-1,220-2,220-3,
220-4。
It is illustrated below with the test mode of connector 220-2, the test of other connectors 220-1,220-3,220-4
It can the rest may be inferred.
Test host 300 sends First ray data SD1 (for example, jtag test data) to processor 110 first, and locates
Reason device 110 will record this First ray data SD1.
In the present embodiment, test host 300 can send First ray data SD1 to processing by the second jtag interface I2
Device 110.For example, First ray data SD1 may include identical position with the number of contacts of connector 220-2 (for example, 64)
First number (for example, 64-bit), but the utility model is not limited to this.
Then, First ray data SD1 can be converted to the first panel data (not being painted) by processor 110, then by the
One panel data is sent to each contact of connector 220-2 in parallel.
In the present embodiment, test host 300 can send control signal and test suite 120-2 is switched to preparation reception
The state of data.For example, by concatenated test suite 120-1,120-2, testing host 300 can be connect by the first JTAG
Mouth I1 sends a control signal to the signal input part 122 of test suite 120-1, then the signal output end of test suite 120-1
123 can be transferred to this control signal the signal input part 122 of test suite 120-2.
In the present embodiment, test host 300 then can indicate processor 110 by first by the second jtag interface I2
Sequence data SD1 is converted to the first panel data, and the first panel data is sent to each of connector 220-2 in parallel
A contact.For example, First ray data SD1 includes continuous in time 64 bit transmitted by the same contact
Data, and the first panel data is then to carry out while transmitting the data of 64 bits by spatially continuous 64 contacts,
The bit value of time-sequencing first is identical to the bit of spatial classification first in the first panel data in middle First ray data SD1
It is worth, the bit value of time-sequencing second is identical to the position of spatial classification second in the first panel data in First ray data SD1
Member value, and so on.Accordingly, 64 contacts of connector 220-2 can be received in parallel in 64 the first panel datas of bit
64 bits data.
Since test suite 120-2 is to be plugged in connector 220-2, test suite 120-2 can be from connector 220-2
Receive the second panel data (not being painted) corresponding to the first panel data.It is noted that if test suite 120-2 with
Connection state between connector 220-2 is good, then the first panel data can be identical to the second panel data.Conversely, if test
Connection state between component 120-2 and connector 220-2 goes wrong, for example, some contact bad connection when, first
It will not corresponding to the bit value for corresponding to problem contact in the bit value and the second panel data of problem contact in panel data
Together.
Then, the second panel data can be converted to the second sequence data SD2 by the controller 121 of test suite 120-2, and
And send test host 300 back to.
It is similar that First ray data SD1 is converted into the mode of the first panel data with processor 110, in the present embodiment
In, the second panel data can be converted to the second sequence data SD2 by the controller 121 of test suite 120-2.For example,
Two panel datas are the data for carrying out while transmitting 64 bits by spatially continuous 64 contacts, and the second sequence data
SD2 includes the data of continuous in time 64 bit transmitted by the same contact, wherein the second panel data is hollow
Between the bit value of sequence first be identical to the bit value of time-sequencing first in the second sequence data SD2, in the second panel data
The bit value of spatial classification second is identical to the bit value of time-sequencing second in the second sequence data SD2, and so on.With
Afterwards, the controller 121 of test suite 120-2 can be by the signal output end 123 of test suite 120-2 by the second sequence data
SD2 is transferred to the signal input part 122 of test suite 120-3, and the signal output end 123 of test suite 120-3 is again by the second sequence
Column data SD2 is transferred to the signal input part 122 of test suite 120-4, then the signal output end 123 of test suite 120-4
Second sequence data SD2 is passed back to the first jtag interface of test host 300 again.
It just can be according to First ray data SD1 that it is issued and institute received the in this way, test host 300
Two sequence data SD2 judge the connection status between connector 220-2 and test suite 120-2.
In the present embodiment, test host 300 can compare First ray data SD1 and the second sequence data SD2, to look for
The difference of First ray data SD1 and the second sequence data SD2 out, and this difference can correspond to connector 220-2 and test group
The contact of bad connection between part 120-2.For example, if the bit value of First ray data SD1 time-sequencing the 5th be 1 and second
The bit value of sequence data SD2 time-sequencing the 5th is 0, then it represents that connector 220-2 spatially sorts the 5th contact can
It can go wrong.
By above-mentioned mode, without duplicate plug expansion card with turn back on, it will be able to on printed circuit board
Multiple connectors are tested, and orienting may problematic contact.
Fig. 2 is painted the schematic diagram of the testing tool of another embodiment of the utility model.The testing tool of Fig. 2 embodiment is available
In the connector on testing of printed circuit board 200 to differential signal transmission, such as PCI-E connector, universal serial bus
(Universal Serial Bus, USB) connector or Serial Advanced Technology Attachment (Serial Advanced Technology
Attachment, SATA) connector etc., but the utility model is not limited to this.
Referring to figure 2., testing tool is for the connector 240 on testing of printed circuit board 200.In the present embodiment, even
Connecing device 240 is PCI-E connector, but the utility model is not limited to this.It is to be measured in the present embodiment other than connector 240
Printed circuit board 200 on further include similar to Figure 1A embodiment processor slot (not being illustrated in Fig. 2) and adapter (not
It is illustrated in Fig. 2).
In the present embodiment, test host 300 is equally to support the jtag test host of boundary-scan function, including one
Jtag interface, and this jtag interface includes tetra- contacts of TDI, TDO, TCK and TMS.Test host 300, printed circuit board 200
Processor slot 210 and printed circuit board 200 adapter 230 between connection relationship and Fig. 1 embodiment in test lead
Connection relationship between the adapter 230 of machine 300, the processor slot 210 of printed circuit board 200 and printed circuit board 200
It is identical, therefore details are not described herein.In addition, processor slot is electrically connected at connector by the wiring on printed circuit board
240。
Testing tool includes processor 110 and test suite 120 '.In the present embodiment, processor 110 is configured to
The processor slot being compatible on printed circuit board 200, and test suite 120 ' is configured to be compatible on printed circuit board 200
Connector 240.It should be noted that the utility model is not intended to limit the quantity and connecting interface of test suite, test suite
The quantity of the connector corresponded on printed circuit board to be measured is configured with connecting interface.
In the present embodiment, test suite 120 ' include controller 121 ', switching switch 125, the first contact to 126 and
Second contact is to 127.Specifically, it is to be connected to processor 110 that connector 240, which includes multipair contact, it is also possible to including extremely
A few docking point be to receive other electric signals (for example, power supply (Power) signal, ground connection (Ground, GND) signal with
And MISC signal etc.) and be not attached to processor 110.The first contact in test suite 120 ' is to be correspondingly connected with device 240 to 126
On be connected to the multipair contact of processor 110 to be arranged, and the second contact is to be correspondingly connected on device 240 to be not attached to 127
At least docking point of processor 110 is arranged.For example, first pair second of leftmost in the test suite 120 ' of Fig. 2
Contact to 127 (including first and second contact counted from left side) is correspondingly connected on device 240 to receive power supply
Signal and the contact of ground signalling are arranged, and count second pair second of the leftmost of the test suite 120 ' from Fig. 2 connects
O'clock (including counting third and the 4th contact from leftmost side) are correspondingly connected on device 240 to receive MISC letter to 127
Number contact be arranged, however the utility model is not limited to this.
Each first contact forms signal circuit to 126 in test suite 120 '.For example, connection status all
In normal situation, when processor 110 by signal (for example, PCIE_TXi (i=0~n)) from a contact (for example, P2i) pass through
The first contact from connector 240 to test suite 120 ' to 126 one of contact transmission, the return path signal of this signal
(for example, PCIE_RXi (i=0~n)) will be passed 126 another contact by connector 240 from same first contact
Return processor 110 in another corresponding contact (for example, P2i+1).In other words, if some in signal is not transmitted back to place
Device 110 is managed, may indicate that corresponding contact is (for example, 110 contact P of alignment processing device in connector 2402iOr P2i+1Contact) go out
Existing problem.
Second contact is all coupled to controller 121 ' to 127, since the second contact is all pair to each of 127 contacts
One of electric signal should be arrived, therefore in the normal situation of connection status, each contact can correspond to a bit value.
For example, in the normal situation of connection status, the second contact of the contact of corresponding power signal and ground signalling is to 127
Two contacts respectively correspond the bit value to 1 and 0.
In the present embodiment, one of them first contact in test suite 120 ' on 126 signal circuit to being provided with
Switch switch 125, switching switch 125 is coupled to controller 121 ' and can be controlled by controller 121 '.121 ' meeting of controller
127 electric signal will be compared with preset signals from the second contact, if from the second contact to 127 electric signal
It is consistent with preset signals, then makes to switch the conducting of switch 125, if otherwise electric signal and default letter from the second contact to 127
Number it is not consistent, then makes to switch switch 125 and be not turned on.For example, controller 121 ' judges corresponding power signal and ground connection is believed
Number contact the second contact to 127 two contacts whether be respectively received 1 and 0 bit value preset signals, if then
Make switch switch 125 be connected, it is on the contrary then make switching switch 125 be not turned on.
Accordingly, 126 signal is not passed back if being transferred to switching corresponding first contact of switch 125 from processor 110
Processor 110, then it represents that corresponding second contact is likely to occur problem to 127 contact in connector 240.
The test mode of connector 240 (as shown in Figure 2) on printed circuit board 200 is illustrated below.In this implementation
In example, the contact of connector 240 includes the first contact (for example, corresponding PCIE_TX0, PCIE_RX0, PCIE_TX1, PCIE_
RX1 ..., PCIE_TXn, PCIE_RXn total 2n+2) and the second contact (for example, corresponding power, ground connection and two MISC
Signal totally 4), wherein the first contact corresponds to the first contact in test suite 120 ' to 126 contact, and the second contact is
Corresponding to the second contact in test suite 120 ' to 127 contact.More particularly, processor 110 is connected on connector 240
Contact be the first contact, and be not attached to processor 110 contact be the second contact.Wherein, since 2n+2 is connector 240
The first contact quantity, therefore n+1 be test suite 120 ' on the first contact to 126 quantity, and due to 4 be connector
The quantity of second contact on 240, therefore 2 be the second contact on test suite 120 ' to 127 quantity, but the utility model is not
It is limited to this.
Test host 300 sends First ray data SD1 (for example, jtag test data) to processor 110 first, and locates
Reason device 110 will record this First ray data SD1.
In the present embodiment, test host 300 can send First ray data SD1 extremely by the TDO contact of jtag interface
Processor 110.For example, First ray data SD1 may include with the first contact to 126 the identical n+1 bit of quantity,
Each of which bit is set to transmit by one of PCIE_TXi (i=0~n), but the utility model is not limited to this.
Then, First ray data SD1 can be converted to the first panel data (not being painted) by processor 110, then by the
One panel data is sent to connector 240 (for example, by PCIE_TXi (i=0~n)), and at the same time from connector in parallel
240 receive the second panel data (not being painted) (for example, passing through PCIE_RXi (i=0~n)) for corresponding to the first panel data.
In the present embodiment, a part of its contact between printed circuit board 200 can be defined as passing by processor 110
Send contact (for example, P0、P2…P2n), and another part of its contact between printed circuit board 200 is defined as receiving
Contact is (for example, for example, P1、P3…P2n+1).Then, processor 110 can be in a similar manner to the embodiments described above by First ray
Data SD1 is converted to the first panel data of identical bit number (for example, n+1), and by each position of the first panel data
Member is sent to multiple first contacts of connector 240 by PCIE_TXi (i=0~n) from transmission contact in parallel, and these positions
Metadata returns to connector 240 to 260 via the first contact of test suite 120 ' from multiple first contacts of connector 240
The second panel data can be converted to afterwards passes through the reception contact that PCIE_RXi (i=0~n) passes processor 110 back again, and first is flat
Row data and the difference of the second panel data will reflect that may problematic contact in connector 240.
Specifically, the first contact of one of them of test suite 120 ' is to 260 (for example, corresponding to transmission contact P2nWith
Receive contact P2n+1) signal circuit on be provided with switching switch 125, if therefore being sent to this first contact to 260 bit
Data do not return correctly, indicate the second contact of test suite 120 ' to 270 with the second contact of connector 240 (for example,
For transmitting the contact of power supply, ground connection or MISC signal) between connection be likely to occur problem cause switch switch 125 controlled
Device 121 ' is opened and is not turned on.
On the other hand, other than being provided with the first contact for switching switch 125 on signal circuit to 260, if being sent to
Some first contact does not return 260 bit Data correctly, indicate test suite 120 ' the first contact to 260 with
The first contact on connector 240 corresponding to no correct return data is likely to occur the connection between 260 the first contact
Problem.
Then, the second received panel data can be converted to the second sequence data SD2 by processor 110, and be returned
Reach test host 300.The mode that panel data is converted to sequence data has been described in detail in aforementioned paragraphs, thus it is no longer superfluous herein
It states.
It just can be according to First ray data SD1 that it is issued and institute received the in this way, test host 300
Two sequence data SD2 judge the connection status between connector 240 and test suite 120 '.
By above-mentioned mode, it is only necessary to the connection for differential signal transmission can be tested using a jtag interface
Device, the embodiment compared to Figure 1A and Figure 1B more preferably save the use of a jtag interface.
Fig. 3 is painted the schematic diagram of the test macro of an embodiment of the present invention.
Referring to figure 3., the testing tool in Figure 1A, Figure 1B and Fig. 2 embodiment can for example be integrated into test macro 10.It surveys
Test system 10 be for carrying out boundary scan testing and being implemented as the shape of chest, including upper cover 11, lower seat 12 and
Air pressure valve 13, wherein air pressure valve 13 keeps upper cover 11 closely sealed when covering with lower seat 12.
Printed circuit board 200 to be measured is placed in lower seat 12, and printed circuit board 200 may include processor slot 210, connect
4) and connector 240 meeting device 220-i, (such as i=1~N, N are such as, but not limited to, and connector 220-i and connector 240 are distinguished
Processor slot 210 is connected to by the wiring on printed circuit board.
Processor 110, test suite 120-i and test suite 120 ' are all set to upper cover 11, wherein processor 110 with
Processor slot 210 is correspondingly arranged, and test suite 120-i is correspondingly arranged with connector 220-i, and test suite 120 ' and company
It connects device 240 to be correspondingly arranged, when so that upper cover 11 and lower seat 12 covering and are closely sealed, processor 110 can be plugged in processor slot
210, test suite 120-i can be plugged in connector 220-i, and test suite 120 ' can be plugged in connector 240.
In the present embodiment, test host 300 for example can be via the connection in test macro in printed circuit board
200 adapter 230 (not being painted) and test suite 120-i, and test host 300 can connect electricity to provide printed circuit board
Power supply needed for 200.
When testing, it is only necessary to upper cover 11 and lower seat 12 snugly be covered by air pressure valve 13, open power supply simultaneously
And starting processor 110, test host 300, which is just able to use the method that previous embodiment is introduced, to be come to printed circuit board 200
On connector 220-i and connector 240 tested, and orienting may problematic contact.
In conclusion the testing tool that the utility model embodiment is proposed, the expansion card form of special designing is utilized
Test suite and processor can more accurately orient the problem contact on printed circuit board by test host, and
And promote test speed.In the utility model embodiment, test suite and the processor of special designing can be supported existing
Boundary-scan function, and the jtag interface for being welded contact on circuit boards using test is traditionally only capable of, to be directed to printing
The contact of connector on circuit board is tested, and can conveniently be oriented in connector without multiple turning back on
The problem of contact.
Although the utility model is disclosed as above with embodiment, it is not intended to limit the utility model, Ren Hesuo
Belonging to those of ordinary skill in technical field should can make a little in the case where not departing from the spirit and scope of the utility model
Change and retouch, therefore the protection scope of the utility model should regard subject to appended claims institute defender.
Claims (10)
1. a kind of testing tool, which is characterized in that the testing tool is suitable for a connector tested on a printed circuit board, described
Testing tool includes:
One processor, the processor are compatible with a processor slot of the printed circuit board, and to receive from test host
One First ray data, and the First ray data are converted into one first panel data；And
One test suite, the test suite are compatible with the connector and are coupled to the test host,
Wherein when the processor is plugged in the processor slot, and the test suite is plugged in the connector, the processor
Also first panel data is sent to the connector, wherein the test suite is somebody's turn to do to receive to correspond to from the connector
Second panel data is converted to one second sequence data by one second panel data of the first panel data, and by this
Two sequence datas are sent to the test host.
2. testing tool as described in claim 1, which is characterized in that the test suite includes:
One signal output end, the signal output end are coupled to the test host；And
One controller, the controller are coupled to the signal output end, to receive corresponding first panel data from the connector
Second panel data, which is converted into second sequence data, and defeated by the signal output end
Second sequence data out.
3. testing tool as claimed in claim 2, which is characterized in that the test suite further include:
One signal input part, a signal output end of the signal input part to be coupled to another test suite,
Wherein the controller is coupled to the signal input part, and to receive another second sequence from another test suite
Column data, and another second sequence data is exported by the signal output end.
4. testing tool as described in claim 1, which is characterized in that the connector is dual inline memory modules connection
Device.
5. testing tool as described in claim 1, which is characterized in that the First ray data include jtag test data, and
And the test host includes jtag test host.
6. a kind of testing tool, which is characterized in that the testing tool is suitable for a connector tested on a printed circuit board, described
Testing tool includes:
One processor, the processor are compatible with a processor slot of the printed circuit board, and to receive from test host
One First ray data, and the First ray data are converted into one first panel data；And
One test suite, the test suite are compatible with the connector and including multiple first contacts pair, wherein respectively this first connects
Point to forming a signal circuit in the test suite,
Wherein when the processor is plugged in the processor slot, and the test suite is plugged in the connector, the processor
Also first panel data is passed through the connector to those first contacts to transmission, receives to correspond to from the connector and be somebody's turn to do
Second panel data is converted to one second sequence data by one second panel data of the first panel data, and by this
Two sequence datas are sent to the test host.
7. testing tool as claimed in claim 6, which is characterized in that the test suite further include:
One second contact pair, second contact is to receive an electric signal；
One controller, the controller are coupled to second contact pair；And
One switching switch, the switching switch be coupled to the controller, and be set to those first contacts to one of
On the signal circuit,
Wherein the controller is the received electric signal of institute to be compared with a preset signals for second contact, and
Switching switch is controlled so that a comparison result is notified the test host.
8. testing tool as claimed in claim 7, which is characterized in that the electric signal includes a power supply signal, a ground connection letter
Number and one of a MISC signal or combinations thereof.
9. testing tool as claimed in claim 6, which is characterized in that the connector be PCI-E connector, USB connector with
And one of SATA connector.
10. testing tool as claimed in claim 6, which is characterized in that the First ray data include jtag test data, and
And the test host includes jtag test host.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| WO2021073048A1 (en) * | 2019-10-15 | 2021-04-22 | 芯创智（北京）微电子有限公司 | Apparatus and method for debugging pcie device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021073048A1 (en) * | 2019-10-15 | 2021-04-22 | 芯创智（北京）微电子有限公司 | Apparatus and method for debugging pcie device |
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