GB2405945A

GB2405945A - Printed circuit board test apparatus

Info

Publication number: GB2405945A
Application number: GB0321268A
Authority: GB
Inventors: John Edward Nigel Kirby; Alan Hutchison; John Laird; William Swanston
Original assignee: Agilent Technologies Inc
Current assignee: Agilent Technologies Inc
Priority date: 2003-09-11
Filing date: 2003-09-11
Publication date: 2005-03-16
Anticipated expiration: 2023-09-11
Also published as: GB0321268D0; GB2405945B

Abstract

A test apparatus (1) includes a receiver (2) and a cassette (3). The cassette (3) comprises a bed-of nails test fixture (9) having a plurality of electric probes (10) for contacting predetermined pads (11) and/or pins on a printed circuit board assembly (12) to be tested. The printed circuit board assembly (12) to be tested includes a plurality of Boundary Scan enabled devices (13) which may form one or more Boundary Scan chains, the input and outputs of which are provided by particular ones of the pads (11). The receiver (2) includes a loop-back card (4) having a plurality of programmable Boundary Scan devices (6) mounted on one side thereof, as well as other components, as required to ensure the functionality of the loop-back card, which are not shown. A Boundary Scan Control module (7) provides control of the testing procedure of the Boundary Scan devices (13) on the printed circuit board (12) to be tested, as well as capability for programming the Boundary Scan devices (6) on the loop-back card (4) to provide the appropriate functionality for the loop-back card (4) to emulate a back-plane or motherboard that the printed circuit board assembly (12) under test would be connected to in normal operation. The bed of nails (9) is located in casette (3), allowing it to be removed and changed according to the type of PCB under test.

Description

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1 2405945 Printed Circuit Board Assembly Test Apparatus

Technical Field

1] The present invention relates, in general, to a test apparatus for testing a printed circuit board assembly having various different types of components mounted thereon, including components that are capable of socalled Boundary Scan testing.

Background Art

2] The use of double-sided, multi-layer printed circuit assemblies with custom application-specific integrated circuits (ASICs) and miniature surface mount technology (SMT) components is now commonplace. Technologies are constantly being developed to enable the spacing between the components to be reduced. Similarly, the spacing between the pins of components (pitch) is being reduced, with a pin spacing of 0.6mm or less now becoming typical across a wide range of package types, including ballgrid arrays (BGAs), chip-scale packages (CSPs), leadless lead-frame packages (LLPs) and extra-fine pitch (XFP) components.

10003] The combination of component miniaturization, reduced spacing between devices and pins and greatly increased pin count on integrated circuits, coupled with an increased complexity of electronic devices is making it very difficult to test whether an electronic device or component has been loaded correctly, soldered to the printed circuit board correctly and is fully operational. As the number of leads on integrated circuit packages continues to increase and the pitch between the leads decreases, the design and manufacture of test probes and fixtures becomes more and more difficult.

With more crowded and densely populated printed circuit board assemblies, there is now less space on the printed circuit board for test pads and test probe access. Even with test pad access, the integrated circuit packages are becoming so complex that it is very difficult and extremely time consuming to write an effective test program to verify the connectivity and functionality of all the components on a printed circuit board assembly. - 2

4] One known method of testing such printed circuit board assemblies is to use a so-called "bed of nails" test fixture. Such a test fixture, for example of the type available from Agilent Technologies, comprises a number of probes extending generally vertically, which are spring loaded to provide electrical contact with predetermined points on a printed circuit board under test. The probe pattern is predetermined according to the printed circuit board assembly to be tested and, when the ends of the probes, which are usually fairly sharp thin ends are in contact with the desired contact points on the printed circuit board assembly, signal paths are thereby formed between a controller of the bed of nails test fixture and the particular nodes on the printed circuit board assembly so that appropriate signals can be transmitted through the signal paths to the various devices on the printed circuit board assembly and sensed from the circuit board assembly to determine whether the devices and/or printed connections on the printed circuit board itself are faulty.

5] However, densely populated printed circuit board assemblies often have inaccessible signal paths, such as wire traces beneath multiple layers on the printed circuit board assembly, thereby hampering the use of such a bed of nails test fixture. Another disadvantage of using a conventional bed of nails in-circuit tester is the expense of developing a different one having a particular probe array pattern for each different printed circuit board assembly to be tested. With this expense compared to the reduced lifecycle of new products being developed today, there is a reduced return on investment (ROI) with such a conventional bed of nails fixture, especially in the low volume, high mix (LVHM) environment, so that they are becoming uneconomic.

6] As such test fixtures grow in complexity to match the growing complexity of the assemblies they are to test, especially with doublesided "clam-shell" fixtures, it becomes more and more difficult to determine if the test fixtures themselves were properly built or if there are any incorrectly wired probes. Apart from the initial testing for fixture manufacturing defects, there is also a need to consider the on-going need for maintenance and diagnostics.

7] At least partly because of these problems, the Boundary Scan test method was developed as an effective test method for determining if a particular device is defective or not. Boundary Scan is also known also as IEEE 1149.1 or Joint Test Action Group (JTAG), and is a specialized non contact four-wire serial interface (a fifth wire is optional) to access complex digital integrated circuits, such as ASICs, DSPs, CPLDs, and microprocessors. Boundary Scan testing is, in effect, a standard test method to which devices are manufactured that allows for only four pins (ports) to be contacted by an in-circuit tester and to be able to test the full functionality of the device from those four ports (or in some cases five ports). In general test data enters the chip on the Test Data In (TDI) pin, is stored in one of the data registers or the instruction register, and shifted out from the chip on the Test Data Out (TOO) pin. The Boundary Scan logic is clocked by Test Clock (TCK), independent of the system clock. The Test Mode Select (TMS) signal is the input which determines the mode of operation for the Boundary Scan test circuitry within a device and controls the state changes of the Test Access Port (TAP) controller. The Test Access Port (TAP) is part of a Boundary Scan device, the operation of which is defined by the IEEE 1149. 1 Standard, and consists of circuitry and signals which determine the operation of the test support functions of the device and the way in which the Boundary Scan registers are used. A Test Reset (TRST) pin is part of the TAP (Test Access Port) and is an optional input defined in the IEEE 1149.1 Standard. If present in a device, it can be used to reset the Boundary Scan logic.

8] If several devices that have Boundary Scan testing functionality are interconnected on a printed circuit board, the four (or five) contact probes need only contact the appropriate ports on the boundary of the several - 4 devices under test so that all the Boundary Scan devices are tested simultaneously. For example, a test data signal would enter the TDI pin on one device, and the test output would be read from the TDO pin from another of the devices, thereby also testing the printed circuit board between the Boundary Scan devices for structural faults that can occur during manufacturing and to perform in-circuit device programming - all via the standard JTAG test access ports.

9] As explained above, multiple Boundary Scan compatible integrated circuits may be serially interconnected on the printed circuit board, forming a Boundary Scan chain, and the board may contain more than one scan chain.

Such chains provide electrical access from the serial TAP interface to every pin on every integrated circuit that is part of the chain. The result is that each Boundary Scan cell becomes a virtual test point, significantly reducing the number of actual test pads needed on the board.

[00101 During the prototype phase of a new printed circuit board design when the design is typically not stable enough to justify the time and expense of developing an in-circuit test fixture or functional test program, Boundary Scan testing can help diagnose problems quickly without the need for a great deal of probing. As a result, the printed circuit boards can be turned on faster and the design can be debugged more quickly, with higher yields from the CM, at greatly reduced costs to the project.

[00111 One problem that arises in the early design phase of a prototype printed circuit board assembly is how to get both the power and JTAG (Boundary Scan) connections to the board under test. In final use, of course, the printed circuit board would often be connected to an instrument backplane or motherboard, which could be used, if available, but often in this preliminary design phase, such a motherboard is unavailable. Accordingly, flat-pack fixtures that involve connectors, cables and power supplies are often cobbled together for such preliminary testing. This can become quite messy and constant handling means that the hardware can be damaged. This damage is not always obvious, and in the case of motherboards, damaged or bent pins can affect the assemblies plugged into them. In effect, the motherboard, or backplane, becomes a virus, affecting every assembly plugged into it.

Irrespective of whether the connectors are soldered in, press fitted or surface mounted, the repairs are costly, time consuming and not always successful.

2] It is an object of the present invention, therefore, to provide a test apparatus for testing a printed circuit board assembly having Boundary Scan devices mounted thereon which overcomes, or at least reduces the problems of the known systems described above.

Disclosure of Invention

lO013] Accordingly, in a first aspect of the present invention, there is provided a test apparatus for testing a printed circuit board assembly having Boundary Scan devices mounted thereon, the apparatus comprising a bed-of- nails fixture having a plurality of electrical probes for making electrical contact with predetermined points of a printed circuit board assembly to be tested, the electrical probes being arranged for contacting at least suitable contact pads on the printed circuit board assembly for carrying out Boundary Scan testing of devices mounted thereon, for providing appropriate power supply and for providing printed circuit board assembly in/out signals, a loop-back card connected to the bed-of-nails fixture, the loop-back card having programmable Boundary Scan devices mounted thereon for providing appropriate loop-back functionality for the printed circuit board assembly to be tested a power supply module coupled to the loop-back card for supplying appropriate power to the loop-back card and the printed circuit board assembly to be tested and a Boundary Scan test control module coupled to the loop-back card for programming the Boundary Scan devices mounted thereon and for controlling testing of the Boundary Scan devices mounted on the printed circuit board assembly to be tested. - 6

l0014l The bed-of-nails fixture may be provided in a cassette for receiving the printed circuit board assembly to be tested, the cassette further comprising at least one connector for connection to the loop-back card.

5] The loop-back card may be provided in a receiver having at least one connector for connection to the bed-of-nails fixture.

6] The receiver and cassette may include complementary registration means for ensuring that the cassette is loaded into the receiver in a correct orientation for the connectors on the receiver and cassette to mate correctly.

7] A pneumatic means may be provided for facilitating the mating of the connectors on the receiver and cassette.

Brief Description of Drawings

8] One embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawing which is a schematic diagram of a printed circuit board assembly test apparatus according to one embodiment of the present invention.

Detailed Descrintion [0019] Thus, as shown in the drawing, a test apparatus 1 includes a receiver 2 and a cassette 3. The cassette 3 generally comprises a bed-of nails test fixture 9 having a plurality of electric probes 10 for contacting predetermined pads 11 and/or pins on a printed circuit board assembly 12 to be tested. The printed circuit board assembly 12 to be tested includes a plurality of Boundary Scan enabled devices 13 which may form one or more Boundary Scan chains, the input and outputs of which are provided by particular ones of the pads 11. The bed-of nails test fixture 9 is also provided with one or more connectors 14, which provide interconnection to the receiver 2.

0] The receiver 2 includes a loop-back card 4 having a plurality of programmable Boundary Scan devices 6 mounted on one side thereof, as well as other components, as required to ensure the functionality of the loopback card, which are not shown. The other side of the loop-back card 4 has mounted thereon a number of connectors 5, which provide interconnection to the connectors 14 of the cassette 3. The connectors 5 have a number of connections available therein to provide the input and output signals, as required, to and from the printed circuit board assembly 12 to be tested.

These input and output signals are routed to and from the Boundary Scan devices 6, as well as to and from a Boundary Scan Control module 7 and a Power Supply module 8.

1] The Boundary Scan Control module 7 provides control of the testing procedure of the Boundary Scan devices on the printed circuit board to be tested, in a manner known in the art, as well as capability for programming the Boundary Scan devices on the loop-back card 4 to provide the appropriate functionality for the loop-back card 4 to emulate a backplane or motherboard that the printed circuit board assembly 12 under test would be connected to in normal operation.

2] The Power Supply module 8 is arranged to provide whatever power level may be required for the particular printed circuit board assembly under test, and is controlled by a rocker switch on the Receiver 2 front panel.

3] In one particular embodiment, the receiver 2 can be formed by a steel base pan with rear panel cutouts for a Mains IEC connector, a 9-way D type plug connector for on-board device programming/configuring and a 15 way D-type for boundary scan interconnect testing. Front panel cutouts may be provided for a 3-way Rotary switch (for PSU selection) and a Mains Rocker switch. The sides may be fitted with carrying handles. - 8

[0024l A test platen of the Receiver 2 has a fixed screen plate, which accepts changeable test cassettes 3 (each cassette being specific for a particular printed circuit board assembly 12). An extended MTH-2 open top hat with +180 walls and +70 Pusher Bars (PCB area 400mm x 280mm) may be provided fixed to a moving screen which is pulled down against the test cassette 3 via four pneumatic cylinders and guide bearings. The top hat is fitted with a changeable pressure plate for each PCB type.

5] The connectors 5 on the Receiver 2 are formed by 1 x 15-way D type plug connector for boundary scan interconnect testing, 1 x 9-way D-type plug connector for on-board programming and 3 x 37-way D-type plug connectors fitted in 3 possible positions to suit nominated PSU requirements - one connector for each PSU in use.

6] Additional connections can be made to 6 x DIN41612 connectors (sockets on the cassette, plugs on Receiver 2, with a socket on rear of plug).

The DIN41612 connectors are wired to the loop-back card 4 to provide the desired input and output signals. The loop-back card 4 may comprise a plurality of l/O channels, each l/O channel being connected to a pin on a DIN41612 connector.

7] DIN connectors are only fitted to Test Cassettes 3 requiring the loopback interconnect functionality to minimize insertion and removal forces on the cassette 3.

8] The Boundary Scan connections on the cassette 3 may be 15-way Dtype connectors for printed circuit boards whose connection is accessible from the underside of the printed circuit board assembly. Surface Mount type connectors, where there is no testpad access on the underside, either untented via or testpad, can be contacted via top probes wired to a flying lead. This will plug into a further 15-way D-type connector on top of the test platen, which is provided parallel to the underside D- type connector. - 9 -

9] In its closed position, the top hat actuates/engages two interlock micro-switches used as to provide an enable pneumatics signal. A microswitch providing a signal indicative of whether a cassette is present may also be provided in the series safety wiring.

10030] Anti-open pins may be fitted to prevent the top hat opening whilst the pneumatics are actuated. A further alternating push button on the receiver front can be provided to actuate the pneumatics. The pneumatic system is driven by +12Volts and includes a standard on-board regulator and quick-release coupling.

1] An AC-DC Convertor provides the +12Volt supply for the pneumatic system, as well as mains switching relays. A front panel 3-way rotary switch can be provided to select one of three different power supply levels to power the printed circuit board assembly under test 12 and the loop-back card 4. A rocker switch can also be provided to enable power to the Power Supply module 8.

2] The three 37-way D-type connectors on the receiver 2 can, for example, be allocated as follows: Position 1: Power Supply supplying +/-12V, 3.3V, 5V, -5.2V Position 2: Customer specific 25. Position 3: Customer specific [0033] A mains switching box can be installed in the receiver 2 to accommodate up to 3 +12V relays. The +12V feed for each relay can be provided via the front panel rotary switch. The inputs for each relay can be provided from the switched mains from the front rocker switch. The outputs for each relay will feed a Mains IEC lead which plugs into the Power Supply module 8. The +12V internal Power Supply may be wired before the mains - 10 rocker switch i.e. enabled before power is switched to the Power Supply module 8.

4] The Test Cassette comprises a fixed probe plate and a moving screen plate, registered via linear bearings. The underside of the cassette 3 is fitted with a protective polycarbonate base plate.

10035] In one basic form, a cassette can be provided with probes in required power positions on the underside of the PCB assembly 12 plus a JTAG connector, either with pin-thru' hole, or surface mounted with testpad access. The probes 10 are wired to the D-types connectors using a standard Boundary Scan configuration. Alternatively, the cassette 3 can have further connections made to a loop-back card 4 inside the Receiver.

lO036] The pressure plate can be fitted with pusher rods/blocks to counteract probes on power connectors and boundary scan loop-back interconnect probes, if fitted. Lifting/removal handles may be fitted to the probe plate to ease cassette insertion/removal into and from the receiver 2.

10037] The loop-back card 4 provides a plurality of boundary-scan test channels that can be used to increase the test coverage of the unit under test. The nets between the external connector(s) and the Boundary Scan devices that drive the nets are not normally covered because there is no Boundary Scan access at the connectors. The loop-back card 4 provides Boundary Scan access at the connector enabling these nets to be fully covered. Each of the bidirectional test channels on the module is individually controllable. Test channels can be set to be an input, output, or set to a high impedance state.

lO038] All the test channels, test access port (TAP) signals, and power signals are available through a plurality of DIN41612 connectors. A plurality of programmable logic devices that provide boundary-scan access to their l/O - 11 pins control the test channels. Each pin has a control cell that allows the pin to be set as an input, output, or to a highimpedance state.

9] Thus, the embodiment of the invention described above aims to focus on handling improvements during the early design/development phase of a printed circuit board assembly and also offers a solution that can be used in volume production testing at low cost. The solution also offers on-board programming capability, which is an important value-added function that can be used to save manufacturer's time and money. Boundary Scan enables programming of CPLDs and FPGAs, and is especially useful for programming Flash when access to the Flash device is limited. The benefits of on-board programming include: Simplified inventory management (there being no need to have different part numbers and stores locations set-up for programmed and un-programmed parts) Fewer programming stations required, Elimination of the risk of having the wrong programmed device in the wrong reference location on the printed circuit assembly, Reduced risk of damage to device caused by additional handling, and Support for just-in-time programming and last minute engineering change orders (ECOs).

0] It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention. - 12

Claims

Claims 1. A test apparatus for testing a printed circuit board assembly

having Boundary Scan devices mounted thereon, the apparatus comprising: a bed-of- nails fixture having a plurality of electrical probes for making electrical contact with predetermined points of a printed circuit board assembly to be tested, the electrical probes being arranged for contacting at least suitable contact pads on the printed circuit board assembly for carrying out Boundary Scan testing of devices mounted thereon, for providing appropriate power supply and for providing printed circuit board assembly in/out signals; a loop-back card connected to the bed-of-nails fixture, the loop-back card having programmable Boundary Scan devices mounted thereon for providing appropriate loop-back functionality for the printed circuit board assembly to be tested; a power supply module coupled to the loop-back card for supplying appropriate power to the loop-back card and the printed circuit board assembly to be tested; and a Boundary Scan test control module coupled to the loop-back card for programming the Boundary Scan devices mounted thereon and for controlling testing of the Boundary Scan devices mounted on the printed circuit board assembly to be tested.
2. A test apparatus according to claim 1, wherein said bed-of-nails fixture is provided in a cassette for receiving the printed circuit board assembly to be tested, the cassette further comprising at least one connector for connection to the loop-back card.
3. A test apparatus according to either claim 1 or claim 2, wherein said loop-back card is provided in a receiver having at least one connector for connection to the bed-of-nails fixture. - 13
4. A test apparatus as claimed in Claim 3, when dependent on claim 2, wherein the receiver and cassette include complementary registration means for ensuring that the cassette is loaded into the receiver in a correct orientation for the connectors on the receiver and cassette to mate correctly.
5. A test apparatus as claimed in claim 4, further comprising pneumatic means for facilitating the mating of the connectors on the receiver and cassette.
6. A test apparatus substantially as hereinbefore described with reference to the accompanying drawing.