JP2001135778A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip-on-chip type semiconductor device with which the sate of electrical connection between semiconductor chips can be easily inspected. SOLUTION: A chip-on-chip structure is formed by bonding active surfaces of a parent chip 1 and a child chip 2 opposed to each other. A power source unit and a ground unit of the parent chip 1 and the child chip 2 are isolated electrically. A test probe is brought into contact with a signal connection bump BS1 of the parent 1 and a ground connection bump BG1 for supplying a ground potential to the child chip 2 to apply an inspection voltage. Thus, whether a circuit via a diode DD2 (protection diode or parasitic diode) is formed is inspected. Consequently, the bonding state between the signal connection bumps BS1, BS2 can be inspected. Since the power source unit and the ground unit of the parent chip 1 and the child chip 2 are isolated, there is no possibility of a circuit being formed via diodes DM1, DM2 on the parent chip 1 side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a so-called chip-on-chip structure.

[0002]

2. Description of the Related Art On a first semiconductor chip (parent chip),
It has been proposed to configure a semiconductor device having a chip-on-chip structure by joining a second semiconductor chip (child chip) face down, for example. In this case, electrical connection between the first and second semiconductor chips is achieved by joining bumps provided on the surface of each chip. External connection after the chip-on-chip structure is housed in a package of resin or the like, connection between the terminal portion of the lead frame and the external connection pad of the first semiconductor chip by wire bonding or the like. Is achieved by

In a stage before the first and second semiconductor chips are joined, it is checked whether or not each semiconductor chip is a non-defective product, for example, by applying a test probe to a bump. After joining the first and second semiconductor chips to each other to form a semiconductor device having a chip-on-chip structure, it must be ensured that the semiconductor device as a whole is good. Therefore, conventionally, after a chip-on-chip structure is housed in a package, a test signal is supplied from a lead frame to perform a function test.

[0004]

However, the function test is an advanced test method performed by inputting a complicated test signal. On the other hand, a defect of a semiconductor device having a chip-on-chip structure is a bump. The poor connection between them is the majority. Nevertheless, conventionally, there has not been provided a simple method for directly inspecting the quality of the connection between bumps. Had to be applied.

SUMMARY OF THE INVENTION An object of the present invention is to provide a chip-on-chip type semiconductor device which can easily inspect the electrical connection between semiconductor chips.

[0006]

Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor chip and a second semiconductor chip; A chip-on-chip type semiconductor device configured by joining the first semiconductor chip between the internal circuit (10) and the internal circuit (20) of the second semiconductor chip. A first signal connection portion (PS1, BS1) for transmitting and receiving signals, a first ground connection portion (BG1) for applying a ground potential to the second semiconductor chip, and a power supply to the second semiconductor chip. A first power supply connection portion for applying a potential; and a first power supply connection portion for supplying a potential, the second semiconductor chip being connected to a first signal connection portion of the first semiconductor chip. Connected second signal connection part (PS2, BS2) , First the first semiconductor chip
A second ground connection (PG2, BG) connected to the ground connection
2) and a second power supply connection portion (PP2, BP2) connected to the first power supply connection portion of the first semiconductor chip on the outermost surface of the semiconductor substrate, and the second signal connection portion. And a diode (DD2, DD1) formed on the semiconductor substrate so as to be interposed and connected between the first ground connection part and the second power supply connection part, respectively. In the semiconductor chip, the ground section (PE12) and the power supply section (PE11) of the first semiconductor chip
And the first ground connection portion and the first ground connection portion are electrically separated from each other.

[0007] Alphanumeric characters in parentheses represent corresponding components in the embodiment described later. According to the present invention, the first
By applying a test voltage between the signal connection portion and the first ground connection portion or the first power supply connection portion, it is possible to check whether a circuit passing through the diode of the second semiconductor chip is formed. The quality of the connection between the first signal connection and the second signal connection can be checked. Also, when a test voltage is applied between the first signal connection or the first ground connection and the first power supply connection, By checking whether a circuit passing through the diode of the second semiconductor chip is formed, it is possible to check the quality of the connection between the first power supply connection portion and the second power supply connection portion.

Furthermore, whether a circuit is formed through a diode of the second semiconductor chip when a test voltage is applied between the first signal connection or the first power supply connection and the first ground connection. Can be checked whether the connection between the first ground connection portion and the second ground connection portion is good or not.
When the second signal connection unit is a signal input unit, the diode may be, for example, a protection diode for protecting an internal circuit from a surge input. Also, the second
When the signal connection section is a signal output section, the signal connection section may be a parasitic diode parasitic on a transistor of the signal output circuit.

In general, a protection diode or a parasitic diode is interposed between a ground portion and a power supply portion also in a first signal connection portion of a first semiconductor chip. The grounding section and power section of the chip
Since it is electrically separated from the first ground connection portion and the first power supply connection portion, there is no possibility that a circuit passing through the diode in the first semiconductor chip is formed during each of the above-described tests. Therefore, the quality of the electrical connection between the first and second semiconductor chips can be reliably checked.

Note that the first and second signal connection portions,
The second ground connection portion and the first and second power supply connection portions may include a pad formed on the semiconductor substrate, or may include a bump formed by being raised on the outermost surface of the semiconductor substrate. Good. However, at least one of the first and second signal connection parts, at least one of the first and second ground connection parts, and at least one of the first and second power supply connection parts are bumps, respectively. Is preferable, whereby the respective connections can be made satisfactorily.

In the case where the first semiconductor chip is larger than the second semiconductor chip, the first signal connecting portion is connected to the second semiconductor chip.
It is preferable to have a lead portion formed by being pulled out to a region outside the semiconductor chip arrangement region. In this case, at least one of the first ground connection portion and the first power supply connection portion also has a lead portion formed to extend to a region outside the second semiconductor chip arrangement region. Is preferred.

With such a configuration, a test probe is applied to the bumps drawn out of the area of the second semiconductor chip on the surface of the first semiconductor chip,
The quality of the connection between the first signal connection and the second signal connection can be checked. At the same time, with respect to the connection portion of the first ground connection portion and the first power supply connection portion that is drawn out of the second semiconductor chip, the quality of the connection between the connection portion and the corresponding connection portion on the second semiconductor chip side is good. Can be inspected.

[0013]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a schematic sectional view of a semiconductor device using a semiconductor chip according to an embodiment of the present invention, and FIG. 2 is a schematic plan view of the semiconductor device. This semiconductor device has a parent chip 1 as a first semiconductor chip and a child chip 2 as a second semiconductor chip (indicated by a two-dot chain line in FIG. 2).
Have a chip-on-chip structure in which the active surfaces are joined to face each other. In this case, the active surface indicates a surface on the active surface layer region side on which a functional element including an active element such as a transistor and a passive element such as a resistor is formed. Each of the parent chip 1 and the child chip 2 may be a silicon chip, but may be another kind of semiconductor chip such as a germanium semiconductor or a compound semiconductor (such as gallium arsenide or gallium phosphide), or may be a parent chip. It is not necessary that the types of semiconductors of the semiconductor chip 1 and the child chip 2 match.

Signal connection pads PS1 and PS2 for transmitting and receiving signals between the internal circuits 10 and 20 are formed on the active surfaces of the parent chip 1 and the child chip 2, respectively. , And external connection pads PE are formed. The external connection pads PE include a power supply pad PE11 for supplying power to the parent chip 1;
And a ground pad PE12 for supplying a ground potential to the parent chip 1.

A power supply connection pad PP1 for supplying a power supply voltage to the child chip 2 is further provided on the outermost surface of the parent chip 1.
And a power supply pad PE21 (one of the external connection pads PE) to which an external power supply voltage to be supplied to the child chip 2 is applied. The power supply connection pad PP1 and the power supply pad PE21 are connected via a line L on the parent chip 1, and these are electrically connected to a power supply line (power supply unit) for operating the parent chip 1. Insulated.

A signal connection pad PS1 is provided on a semiconductor substrate (a P-type substrate in this embodiment) forming a base of the parent chip 1.
The diodes DM1 and DM2 are interposed between the power supply pad PE11 and the ground pad PE12, respectively. These diodes DM1 and DM2 are protection diodes for protecting the internal circuit 10 from surge input when the signal connection pad PS1 receives a signal input. When the signal connection pad PS1 outputs a signal to the outside, the signal connection pad PS1 is a parasitic diode parasitic on a transistor forming an output circuit.

On the outermost surface of the child chip 2, in addition to the signal connection pad PS2, a power supply connection pad PP2 to which a power supply voltage is supplied, and a ground connection pad PG2 to which a ground potential is supplied.
Are provided. On the semiconductor substrate (P-type substrate in this embodiment) forming the base of the slave chip 2, diodes DD1 and DD2 are interposed between the signal connection pad PS2 and the power supply connection pad PP2 and the ground connection pad PG2, respectively. Have been. These diodes DD1, DD
Reference numeral 2 denotes a protection diode for protecting the internal circuit 20 from a surge input when the signal connection pad PS2 receives a signal input. When the signal connection pad PS2 outputs a signal to the outside, the signal connection pad PS2 is a parasitic diode that is parasitic on a transistor forming an output circuit.

On the outermost surfaces of the parent chip 1 and the child chip 2, a surface protection film (not shown) made of a silicon nitride film or the like is formed, and pads PS1, PS2, PP
1, PP2, PG2, and PE are exposed from openings formed in the surface protective film. And parent chip 1 and child chip 2
Electrical connection and mechanical connection with the signal connection pads PS1, PS2, PP1, of the parent chip 1 and the child chip 2.
The signal connection bumps BS1, which are respectively arranged on PP2
This is achieved by joining BS2, BP1 and BP2 together.

The ground connection pad PG2 of the child chip 2
The ground connection bump BG2 is also formed on the upper surface, and the ground connection bump BG2
1 are provided, which are joined to each other.
The ground connection bump BG1 on the side of the parent chip 1 is formed on the surface protection film and is insulated from the semiconductor substrate forming the base of the parent chip 1, and is therefore electrically connected to the ground portion of the parent chip 1. It is in an insulated state.

In this embodiment, the parent chip 1 is larger than the child chip 2, and the external connection pads PE are arranged outside the arrangement area of the child chip 2. The external connection pad PE is connected to the terminal of the lead frame F via the bonding wire W.
Bumps BS2, BP2, formed on the surface of the
BG2 is formed in a limited area near corresponding pads PS2, PP2, PG2, whereas bumps BS1, BP1, BG1 formed on the surface of parent chip 1 are formed.
Have lead portions a, b, and c (see FIG. 2) which are not limited to the regions near the corresponding pads PS1, PP1, and PG1, but are drawn out of the region where the child chip 2 is arranged on the surface protective film. ing. The ground connection bump BG1 is drawn out to the vicinity of the periphery of the parent chip 1, and the end of the ground connection bump BG1 and the lead frame F are connected by the bonding wire W.

The bumps BS1, BP1, B on the parent chip 1
G1 is formed in the same step by depositing an oxidation-resistant metal (for example, gold) by electrolytic plating or electroless plating after the formation of the surface protective film. Similarly, BS2, BP2, and BG2 on the sub chip 2 are formed in the same step by depositing an oxidation-resistant metal (for example, gold) by electrolytic plating or electroless plating after the formation of the surface protective film. Is done.

FIG. 3 is an illustrative electric circuit diagram for explaining a method of checking the quality of the connection between the parent chip 1 and the child chip 2. When inspecting the quality of the connection between the signal connection bumps BS1 and BS2, the signal connection bumps BS1
The test probes T and T are respectively applied to a lead portion a of the ground connection bump BG1 (or a lead portion b of the power supply connection bump BP1). And
By applying a predetermined test voltage (for example, a voltage which becomes forward with respect to the diode DD2 (or DD1)), the diode DD is connected between the test probes T and T.
It is checked whether 2 (or DD1) is connected.

That is, from one test probe T,
Ground connection bump BG1 (or power supply connection bump BP)
1), ground connection bump BG2 (or power connection bump B
P2), the diode DD2 (or DD1), the signal connection bumps BS2 and BS1, and the other test probe T
Is formed, it can be confirmed that the connection between the signal connection bumps BS1 and BS2 is good. At this time, simultaneously, between the ground connection bumps BG1 and BG2 (or the power supply connection bumps BP1 and BP2).
It is also confirmed at the same time that the connection between (P2) is good.

If a test voltage is applied from the test probe T applied to the lead-out portion c (or a) and no current is detected in the test probe applied to the lead-out portion a (or b), the above-described circuit is used. Will be defective in any of the locations. In such a case, the chip-on-chip structure is determined to be defective and is excluded from the subsequent steps. The power supply connection bump BP1 (or the ground connection bump BG1) and the signal connection bump BS
1 or ground connection bump BG1 (or power supply connection bump BP1),
The quality of the connection between the power supply connection bumps BP1 and BP2 (or between the ground connection bumps BG1 and BG2) can be determined.

Since the power supply unit and the grounding unit of the parent chip 1 and the child chip 2 are electrically separated, a circuit that passes through the diodes DM1 and DM2 of the parent chip 1 is formed between the pair of test probes at the time of inspection. It will not be done.
Therefore, the quality of the electrical connection between the parent chip 1 and the child chip 2 can be reliably checked. As described above, in this embodiment, the power supply unit and the ground unit of the parent chip 1 and the child chip 2 are electrically separated from each other, so that the existing diodes DD1 and DD2 in the child chip 2 It is possible to easily inspect the electrical connection between the parent chip 1 and the child chip 2 without requiring a functional test. Then, only the chip-on-chip structure determined to be non-defective by the simple inspection is subjected to a packaging step using a sealing resin and a subsequent function test step.

This inspection is preferably performed prior to the wire bonding between the parent chip 1 and the lead frame F. However, when the inspection is performed after the wire bonding, the power supply unit between the parent chip 1 and the child chip 2 is required. In addition, it is necessary to secure a state where the grounding portion is electrically separated. Specifically, as shown in FIG. 1 and FIG. 2, the power supply pad PE11 and the power supply pad PE21 are connected to respective terminal portions of the lead frame F, and the grounding pad PE12 is connected to the ground connection. The bumps BG1 may be connected to different terminals of the lead frame F.

Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms. For example, in the above embodiment, the power supply to the child chip 2 is performed via the line L formed on the semiconductor substrate of the parent chip 1, but the power supply connection pad PP1 on the parent chip 1 side is omitted and the power supply The connection bump BP1 may be connected to the lead frame F by a bonding wire W. That is, the configuration may be the same as that of the ground connection bump BG1.

In the above-described embodiment, the bumps BS1, BS2, BP are provided on both the parent chip 1 and the child chip 2.
1, BP2, BG1, and BG2 are provided. For example, the bumps BS2, BP2, and BG2 on the child chip 2 are omitted, and the bumps BS1, BP1, and BG2 on the parent chip 1 are replaced with the pads PS2, PP2 on the child chip 2. It is good also as a structure directly joined to PG2. In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor device having a chip-on-chip structure using a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of the semiconductor device.

FIG. 3 is an illustrative electric circuit diagram for explaining a method of checking the quality of connection between chips;

[Explanation of symbols]

 Reference Signs List 1 parent chip (first semiconductor chip) 2 child chip (second semiconductor chip) 10 internal circuit of parent chip 20 internal circuit of child chip a lead part b lead part c lead part BG1 ground connection bump BG2 ground connection bump BP1 Power connection bump BP2 Power connection bump BS1 Signal connection bump BS2 Signal connection bump DD1 Diode DD2 Diode F Lead frame PE11 Power supply pad PE12 Grounding pad PE21 Power supply pad PG2 Ground connection pad PP1 Power connection pad PP2 Power connection pad PS1 Signal connection pad PS2 signal connection pad T test probe W bonding wire

Claims (1)

[Claims] 1. A chip-on-chip type semiconductor device comprising a first semiconductor chip and a second semiconductor chip which are superposed and joined together, wherein the first semiconductor chip has an internal structure. A first signal connection unit for transmitting and receiving signals between a circuit and an internal circuit of the second semiconductor chip, a first ground connection unit for applying a ground potential to the second semiconductor chip, A first power supply connection portion for applying a power supply potential to the second semiconductor chip, on the outermost surface of the semiconductor substrate, wherein the second semiconductor chip is provided with a first signal connection portion of the first semiconductor chip; A second signal connection to be connected; a second ground connection to be connected to a first ground connection of the first semiconductor chip; and a second connection to a first power supply connection of the first semiconductor chip. Two power supply connections are provided on the outermost surface of the semiconductor substrate Both have diodes formed on the semiconductor substrate so as to be interposed and connected between the second signal connection part, the second ground connection part, and the second power supply connection part, respectively. In the first semiconductor chip, a ground portion and a power supply portion of the first semiconductor chip are electrically separated from the first ground connection portion and the first ground connection portion, respectively. apparatus.