JPH09330963A - Semiconductor integrated circuit device and method for forming it in chip - Google Patents

Semiconductor integrated circuit device and method for forming it in chip

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Publication number
JPH09330963A
JPH09330963A JP15202696A JP15202696A JPH09330963A JP H09330963 A JPH09330963 A JP H09330963A JP 15202696 A JP15202696 A JP 15202696A JP 15202696 A JP15202696 A JP 15202696A JP H09330963 A JPH09330963 A JP H09330963A
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JP
Japan
Prior art keywords
chip
pads
external terminal
test
terminal pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15202696A
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Japanese (ja)
Inventor
Minoru Kayano
稔 茅野
Original Assignee
Nec Eng Ltd
日本電気エンジニアリング株式会社
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Publication date
Application filed by Nec Eng Ltd, 日本電気エンジニアリング株式会社 filed Critical Nec Eng Ltd
Priority to JP15202696A priority Critical patent/JPH09330963A/en
Publication of JPH09330963A publication Critical patent/JPH09330963A/en
Application status is Withdrawn legal-status Critical

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Abstract

PROBLEM TO BE SOLVED: To provide terminal pads for testing and sorting on an LSI chip in addition to terminal pads for assembly without deteriorating the electrical characteristics of the chip.
SOLUTION: The external terminal pads 5 for assembly of an internal LSI chip 3 are prevented from being damaged at the time of testing and sorting the chip 3 by connecting all power supply pads and GND (ground) pads of the external terminal pads 5 for assembly of the chip 3 to a power source and GND by providing an external terminal pad section 11 for testing and sorting on the outer periphery of the chip 3 and external terminal pads 4 for testing and sorting and power supply and GND lines 6 and 7 in the pad section 11 and connecting a probe to the pads 4 only. When the chip 3 is cut off from a semiconductor wafer 1 by dicing, the pad section 11 is also cut off simultaneously with the chip 3.
COPYRIGHT: (C)1997,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は半導体集積回路装置及びそのチップ化方法に関し、特にテスト選択用外部端子パッドを設けた半導体集積回路装置及びそのチップ化方法に関する。 BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device and a chip method, more particularly to a semiconductor integrated circuit device and a chip method is provided an external terminal pads test selection.

【0002】 [0002]

【従来の技術】バーンインを含むスクリーニング(選択)の目的で、図2に示すようにLSIチップ(半導体集積回路)2が、まだ半導体ウェーハ1から切り出され(ダイシング)ていない状態(ウェーハ状態)にあるままで、テスト選別されることが多い。 BACKGROUND ART For the purpose of screening, including a burn (selected), the LSI chip, as shown in FIG. 2 (semiconductor integrated circuit) 2, still cut from the semiconductor wafer 1 (dicing) Not state (wafer state) in some remains, it is often test selection. テスト選別時には、外部端子パッドにプローブを接触させる形でテスト回路(治具)に接続される。 During testing sorting, it is connected to the test circuit (fixture) in the form of contacting a probe to the external terminal pads.

【0003】従来、LSIチップの外部端子パッドは、 In the past, the external terminal pad of the LSI chip,
一つのパッドでテスト選別用端子と組立用端子を兼用していた。 The test selection for the terminal and the assembly for the terminal was also used in one of the pad. また、テスト選別において治具の共用化を図るため、電源あるいはグランド(GND;アース)パッドのすべてには、目的とする電位が印加されないことがあった。 Further, in order to common use of jigs in the test selection, power or ground; in all (GND Ground) pads, there is the potential for the purpose it is not applied.

【0004】図3に示すように、LSI組立時には基盤8上に設けられた配線9に、バンプ10を介して、LS [0004] As shown in FIG. 3, the wiring 9 provided on the base 8 at the time of LSI assembled, via the bumps 10, LS
Iチップ3上の外部端子パッドを確実に接続する必要がある。 It is necessary to reliably connect the external terminal pads on the I chip 3. テスト選別時にプローブが強く接触した場合は、 If the probe is in contact with strongly at the time of the test selection,
外部端子パッドに傷が付くことが多く、この傷が外部端子パッドの接続信頼度を低下させていた。 Often damage the external terminal pads are attached, the wound had reduced the connection reliability of the external terminal pads.

【0005】この問題を解決するために、特開平4−7 [0005] In order to solve this problem, JP-A-4-7
5358号あるいは特開昭62−287637号公報には、組立用端子パッドの他にテスト選別用端子パッドを設ける方法が提案されている。 The 5358 No. or JP 62-287637 discloses, in addition to providing the test selection terminal pads method of assembly terminal pads have been proposed.

【0006】 [0006]

【発明が解決しようとする課題】しかし、組み立てられたLSIチップに不要なパッドが残っていると、LSI [0006] However, if there remains unnecessary pad to the LSI chip that has been assembled, LSI
チップの電気特性を劣化させる可能性があって、好ましくない。 There may degrade the electrical characteristics of the chip, which is not preferable.

【0007】本発明の目的は、組立用端子パッドの他にテスト選別用端子パッドを設けるが、LSIチップの電気特性は劣化させない半導体集積回路装置及びそのチップ化方法を提供することである。 An object of the present invention, in addition to it providing the test selection terminal pad assembly terminal pads, electrical characteristics of the LSI chip is to provide a semiconductor integrated circuit device and a chip method does not degrade.

【0008】 [0008]

【課題を解決するための手段】本発明による半導体集積回路装置は、半導体ウェーハ上に形成された半導体集積回路チップと、このチップの周囲に配設されテスト選択用外部端子パッドが配列して設けられたテスト用端子パッド部とを含むことを特徴とする。 The semiconductor integrated circuit device according to the present invention SUMMARY OF] includes a semiconductor integrated circuit chip formed on a semiconductor wafer, provided with sequences provided by the external terminal pads for testing selected around the chip characterized in that it comprises a test terminal pad portion which is.

【0009】また本発明による半導体集積回路装置のチップ化方法は、複数のチップとこれ等チップの各外周にテスト選択用外部端子パッドが夫々配列して設けられたテスト用端子パッド部とを有する半導体ウェーハを準備し、前記チップの各々のテストを前記テスト選択用外部端子パッドを使用してテストを行ない、しかる後に前記チップを前記半導体ウェーハから分離する際に前記テスト用端子パッド部をも切り離すようにしたことを特徴とする。 [0009] Chip method of a semiconductor integrated circuit device according to the present invention includes a plurality of chips and which like test terminal pad portion external terminal pads for test selection provided to respectively arranged on each outer periphery of the chip prepare the semiconductor wafer performs testing each test of the chip using an external terminal pads for the test selection, disconnecting also the test terminal pad portion in separating the chip from the semiconductor wafer and thereafter characterized in that way the.

【0010】 [0010]

【発明の実施の形態】本発明の作用は次の通りである。 Operation of the present invention DETAILED DESCRIPTION OF THE INVENTION is as follows.
ウェーハ状態で内部LSIチップ(本体)の外側にテスト選別用外部端子パッド部を設け、このテスト選別用外部端子パッド部にテスト選別用外部端子パッドや電源供給及びGNDライン等を設け、テスト完了後、内部LS An external terminal pad unit test screening outside the inner LSI chip (body) provided in the wafer state, a test sorting external terminal pads and the power supply and GND line or the like is provided on the external terminal pad portions for the test screening, after completion of the test , internal LS
Iチップを半導体ウェーハからダイシングにより切り出すときに、テスト選別用外部端子パッド部を内部LSI When cut by dicing I chip from the semiconductor wafer, the LSI an external terminal pad unit test screening
チップから切り落とす。 Cut off from the chip.

【0011】以下に、本発明の実施例について図面を参照して説明する。 [0011] Hereinafter, will be described with reference to the accompanying drawings embodiments of the present invention.

【0012】図1は本発明による半導体集積回路の実施例の構成を示す上面図であり、図2,3と同等部分は同一符号にて示している。 [0012] Figure 1 is a top view showing a configuration of an embodiment of a semiconductor integrated circuit according to the present invention, FIGS. 2, 3 and like parts are denoted by the same reference numerals. なお、重複する説明は省略する。 It is to be noted that the description thereof is omitted.

【0013】図1において、内部LSIチップ(LSI [0013] In FIG. 1, the LSI chip (LSI
チップ本体)3の周囲部に、テスト選別用外部端子パッド部11を設け、このテスト選別用外部端子パッド部1 The periphery of the chip body) 3, a test sorting external terminal pad portion 11 is provided, the external terminal pad unit 1 for the test screening
1部にテスト選別用外部端子パッド4及び、電源供給及びGNDライン6及び7を設けて、内部LSIチップ3 External terminal pads 4 and test screened one part, provided with a power supply and the GND line 6 and 7, within the LSI chip 3
の組み立て用外部端子パッド5の電源及びGNDパッドのすべてに、電源及びGND接続を行うとともに、テスト選別時に(テスト)プローブは、テスト選別用外部端子パッド4のみに接続して、組み立て用外部端子パッド5の損傷を防ぐ。 In all power and GND pads of the assembly external terminal pads 5, performs power supply and GND connections (test) probe during the test screening, only connected to the test selection external terminal pads 4, the external terminals for assembly prevent damage to the pad 5.

【0014】例えば、ASIC(特殊用途向けIC)等の多品種少量生産品の場合、品種毎にテスト用治具を準備することは難しいので、治具の共用化を図るのが通例である。 [0014] For example, in the case of limited production of diversified products products such as ASIC (Application Specific IC), so it is difficult to prepare a test jig to each type, that promote sharing of jig is customary. 共用治具の場合、すべての外部端子パッドにプローブが接触できるように設計することは難しい。 In shared jig, it is difficult to design such probes can contact all the external terminal pads. 特に、電源及びGNDパッドはそれぞれ多数あるので、それらのすべてにプローブを接触させることには無理がある。 In particular, the power supply and GND pads are numerous, respectively, to be contacted by probe to all of them is unreasonable.

【0015】従って、テスト選別用外部端子パッド部1 [0015] Thus, test sorting external terminal pad portion 1
1上で電源供給及びGNDライン6及び7を使って、すべての内部LSIチップ3の電源及びGND組み立て用外部端子パッド5に接続することにより、テスト選別時における出力同時動作数制限(同時に動作する出力回路数が多くなると、出力回路が必要な電流のほとんどを消費するので、電源やGNDラインに流れる電流が大きくなる。従って、出力回路の同時に動作する数が制限を受ける)の緩和、及び動作の安定化に役立つ。 Using the power supply and the GND line 6 and 7 on 1, by connecting to the power supply and GND assembled external terminal pads 5 of all internal LSI chip 3 operates simultaneous output operation speed limit during the test selection (at the same time When the output circuit number increases, since consumes most of the output circuit is required current, the current flowing through the power supply and the GND line is increased. Therefore, the number of simultaneously operating the output circuit restricted) relaxation, and operation help in the stabilization of.

【0016】すなわち、組立て用外部端子パッド5のG [0016] That is, G of assembling the external terminal pads 5
ND,電源の各パッドの数よりも、テスト用のそれを多く設けておくことにより、テスト選別時における出力同時動作数の緩和や動作安定性が図れる。 ND, than the number of the pads of the power supply, by providing much it for testing, thereby the output simultaneous operation speed of relaxation and operation stability during testing sorting.

【0017】内部LSIチップ(LSIチップ本体)3 [0017] The internal LSI chip (LSI chip body) 3
を、半導体ウェーハ1からダイシングにより切り離すとき、同時にテスト選別用外部端子パッド部11をも切り離す。 And when disconnecting by dicing the semiconductor wafer 1, disconnected even test sorting external terminal pad portion 11 at the same time.

【0018】 [0018]

【発明の効果】以上説明したように本発明は、内部LS As described above, according to the present invention, the internal LS
Iチップ(LSIチップ本体)の周囲部にテスト選別用外部端子パッド部を設け、その上にテスト選別用外部端子パッドと電源供給及びGNDラインを設けることにより、内部LSIチップの組み立て用外部端子パッドを、 I chip provided an external terminal pad portions for testing sorted perimeter of (LSI chip body), by providing the external terminal pads for testing sorting and power supply and GND lines thereon, the external terminal pads for assembly inside the LSI chip the,
プローブを接触させることによる障害から避けるとともに、テスト選別時に出力同時動作数制限の緩和と動作の安定がはかれる効果があり、さらにLSIチップ本体をダイシングによって半導体ウェーハから分離する際に、 Together avoid the failure by contacting the probe, there are stable can be achieved the effect of alleviating the operation of the output simultaneous operation speed limit at the time of testing sorting, when separated from the semiconductor wafer further by dicing the LSI chip body,
同時にテスト選別用外部端子パッド部からも切り離すことにより、電気特性の劣化を防ぐ効果もある。 By separating from the test sorting external terminal pad portions at the same time, there is also an effect to prevent deterioration of electrical characteristics.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施例の上面図である。 1 is a top view of an embodiment of the present invention.

【図2】半導体ウェーハの上面図である。 2 is a top view of a semiconductor wafer.

【図3】LSIチップの組立方法を説明する図である。 3 is a diagram for explaining the assembly method of the LSI chip.

【符号の説明】 DESCRIPTION OF SYMBOLS

2 LSIチップ 3 内部LSIチップ 4 テスト選別用外部端子パッド 5 組み立て用外部端子パッド 6 電源供給ライン 7 GNDライン 11 テスト選別用外部端子パッド部 2 LSI chip 3 inside the LSI chip 4 Test sorting external terminal pads 5 assembled external terminal pads 6 power supply line 7 GND line 11 test sorting external terminal pad portion

Claims (4)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半導体ウェーハ上に形成された半導体集積回路チップと、このチップの周囲に配設されテスト選択用外部端子パッドが配列して設けられたテスト用端子パッド部とを含むことを特徴とする半導体集積回路装置。 1. A semiconductor integrated circuit chips formed on a semiconductor wafer, characterized in that the external terminal pads for test selection is arranged around the chip and a test terminal pad portion provided by arranging the semiconductor integrated circuit device according to.
  2. 【請求項2】 前記チップにはパッドが設けられており、前記テスト選択用外部端子パッドと前記チップの対応パッドとが互いに接続されていることを特徴とする請求項1記載の半導体集積回路装置。 Wherein said chip is pad is provided, the semiconductor integrated circuit device according to claim 1, characterized in that said test selection external terminal pads and the corresponding pads of the chip are connected to each other .
  3. 【請求項3】 前記テスト選択用外部端子パッドのグランドを含む電源パッドの総数は、前記チップのパッドの電源パッドの総数よりも大であることを特徴とする請求項2記載の半導体集積回路装置。 The total number of power supply pads including ground wherein the external terminal pads the test selection is a semiconductor integrated circuit device according to claim 2, wherein the is larger than the total number of power supply pads of the pad of the chip .
  4. 【請求項4】 複数のチップとこれ等チップの各外周にテスト選択用外部端子パッドが夫々配列して設けられたテスト用端子パッド部とを有する半導体ウェーハを準備し、前記チップの各々のテストを前記テスト選択用外部端子パッドを使用してテストを行ない、しかる後に前記チップを前記半導体ウェーハから分離する際に前記テスト用端子パッド部をも切り離すようにしたことを特徴とするチップ化方法。 4. A plurality of chips and which like the external terminal pads for testing selected for each periphery of the chip is preparing a semiconductor wafer having a test terminal pad portions provided respectively arranged, each of the test of the chip the test using the selected external terminal pads subjected to testing, chip method being characterized in that the disconnect also the test terminal pad portion in separating the chip from the semiconductor wafer and thereafter a.
JP15202696A 1996-06-13 1996-06-13 Semiconductor integrated circuit device and method for forming it in chip Withdrawn JPH09330963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15202696A JPH09330963A (en) 1996-06-13 1996-06-13 Semiconductor integrated circuit device and method for forming it in chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15202696A JPH09330963A (en) 1996-06-13 1996-06-13 Semiconductor integrated circuit device and method for forming it in chip

Publications (1)

Publication Number Publication Date
JPH09330963A true JPH09330963A (en) 1997-12-22

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JP15202696A Withdrawn JPH09330963A (en) 1996-06-13 1996-06-13 Semiconductor integrated circuit device and method for forming it in chip

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7482675B2 (en) 2005-06-24 2009-01-27 International Business Machines Corporation Probing pads in kerf area for wafer testing
US7825446B2 (en) 2006-01-18 2010-11-02 Fujitsu Semiconductor Limited Semiconductor device, semiconductor wafer structure and method for manufacturing the semiconductor wafer structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7482675B2 (en) 2005-06-24 2009-01-27 International Business Machines Corporation Probing pads in kerf area for wafer testing
US7825446B2 (en) 2006-01-18 2010-11-02 Fujitsu Semiconductor Limited Semiconductor device, semiconductor wafer structure and method for manufacturing the semiconductor wafer structure

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