JP2001168157A - Semiconductor device, testing method thereof and semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a testing method thereof and a semiconductor chip which is capable of independently inspecting the semiconductor chip. SOLUTION: A bare chip IC 1 has inspecting terminals 4b, 5b electrically connected to a logic circuit block 2 formed on the bare chip IC, for inspecting the logic circuit block 2 and bonding terminals 4a, 5a electrically connected to the inspecting terminals 4b, 5b through transmission gates. After electrically cutting off the inspecting terminals 4b, 5b and the bonding terminals 4a, 5a, using the transmission gates, the inspecting terminals 4b, 5b are probed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device mounted on a product mounted on a bare chip, such as a hybrid ECU, and an inspection thereof.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor mounted products has rapidly progressed, and there is a demand for mounting semiconductor chips in a bare state. FIG. 3 is a schematic diagram relating to a conventional inspection of a semiconductor chip such as a bare chip.

As shown in FIG. 3, a semiconductor chip J2 is mounted on a substrate J1, and a terminal J3 of one semiconductor chip J2 and a terminal J3 of another semiconductor chip J2 are connected to a wiring formed on the substrate J1. It is electrically connected to J4 by a wire J5 formed by wire bonding or the like.
In the illustrated example, an inspection terminal J6 is provided from a wiring J4 which is the same node as the two semiconductor chips J2. Then, the semiconductor chip J2 is inspected by probing to the inspection terminal J6.

[0004]

However, from the limited test terminals provided on the mounting board, it is possible to judge whether the product is functional or not. Further, there is a problem that it becomes difficult to perform a failure analysis on what characteristic of the chip has failed.

[0005] The above problem arises from the fact that a plurality of semiconductor chips share one node after the semiconductor chip is mounted on the substrate. That is, even if a defect of the semiconductor chip is detected by the inspection terminal, it is not possible to specify which semiconductor chip is defective among a plurality of semiconductor chips sharing the same node, which causes this problem.

In view of the above problems, an object of the present invention is to provide a semiconductor device capable of independently inspecting a semiconductor chip, a method of inspecting the semiconductor device, and a semiconductor chip.

[0007]

According to the first aspect of the present invention, a semiconductor chip (1) is provided.
Are test terminals (4) electrically connected to the internal circuit (2).
b, 5b) and bonding terminals (4a, 5a) for electrically connecting to peripheral circuits, and the bonding terminals (4a, 5a) are connected to the inspection terminals (4b, 5b) by the switch means (60). ) Is electrically connected.

In the present invention, the bonding terminal (4a, 5a) and the inspection terminal (4
b, 5b), the semiconductor chip (1) is electrically disconnected from the peripheral circuit, and the semiconductor chip (1) is electrically disconnected from the peripheral circuit using the inspection terminals (4b, 5b).
Can be independently tested.

In this case, the bonding terminals (4a, 5a,
If a) is located on the outer peripheral side of the test terminals (4b, 5b), the test terminals (4a, 5a) can be easily connected to peripheral circuits using the bonding terminals (4a, 5a).
b, 5b).

According to the third aspect of the present invention, the semiconductor chip (1) has an inspection terminal (4b, 5b) electrically connected to the internal circuit (2), and an inspection terminal (4b, 5b) for electrically connecting to the peripheral circuit. Bonding terminals (4a, 5a), and the bonding terminals (4a, 5a) are connected to the inspection terminals (4b, 5a).
b) is electrically connected to the bonding terminal (4a, 5a) and the inspection terminal (4b, 5b) by using the switch means (60). Thereafter, the semiconductor chip (1) is inspected using the inspection terminals (4b, 5b).

According to the present invention, the bonding terminals (4
a, 5a) and the test terminals (4b, 5b) can be electrically disconnected, so that the semiconductor chip (1) can be electrically disconnected from the peripheral circuit. it can.

According to the invention described in claim 4, the inspection terminals (4b, 5b) electrically connected to the internal circuit (2).
And bonding terminals (4a, 5a) for electrically connecting to peripheral circuits.
a, 5a) is electrically connected to the inspection terminals (4b, 5b) via switch means (60).

Thus, the bonding terminal (4a, 5a) and the inspection terminal (4
The semiconductor chip (1) can be independently tested using the test terminals (4b, 5b) in a state where the semiconductor chips (b, 5b) are electrically disconnected.

In this case, it is preferable that the bonding terminals (4a, 5a) are located on the outer peripheral side of the upper surface of the chip with respect to the inspection terminals (4b, 5b).

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0016]

FIG. 1 is an electric circuit diagram of a bare chip IC according to a semiconductor device of the present embodiment. As shown in FIG. 1, a bare chip IC 1 as a semiconductor chip which is a monolithic IC has a logic circuit block (internal circuit in the claims) 2 formed thereon, and a Vss (ground) terminal 3 from the logic circuit block 2. Vdd (power supply) terminals 4a and 4b are provided. Further, terminals 5a and 5b electrically connected to the input / output terminals of the logic circuit block 2 are provided.

The terminal 5 connected to the input / output terminal
a, 5b and Vdd terminals 4a, 4b, each of which is a set of two terminals, one of which is a bonding terminal 4a for establishing electrical continuity with peripheral circuits (including electronic components, power supply lines, and ground lines). 5a, the other being a bare chip IC
Inspection terminals 4b and 5b for performing the first inspection.

The test terminals 4b and 5b are electrically connected directly to the logic circuit block 2, and the bonding terminals 4a and 5a are connected to each other via a switch circuit block 60 as a switch. Are electrically connected to the inspection terminals 4b and 5b.

In FIG. 1, in addition to the Vdd terminals 4a and 4b, a pair of bonding terminals 5a and inspection terminals 5a are provided.
b, only one set of terminals 5a, 5a, 5
Similarly to b, a plurality of pairs of bonding terminals and inspection terminals connected to the input / output terminals of the logic circuit block 2 are formed.

Here, the switch circuit block 60 is Pc
The transmission gate includes an hMOS transistor 61 and an NchMOS transistor 62. The gate of the PchMOS transistor 61 and the CS (chip select) terminal 7 are connected, and Nc
The gate of the hMOS transistor 62 is connected to the CS terminal 7 via the inverter 63.

When the CS terminal 7 is open, a pull-down resistor 8 is built in so that the CS signal is at a low level. A diode 9 for circuit protection is provided between the wiring from the CS terminal 7 and the power supply and the ground. Is provided.
The substrate potential of the PchMOS transistor 61 and the power supply of the inverter 63 are obtained from the bonding terminal 4a among the Vdd terminals 4a and 4b.

FIG. 2 shows these bonding terminals 4.
FIG. 3 is a schematic view of the arrangement of the test terminals 4b and 5b and the bare chip IC1 as viewed from above. As shown in FIG. 2, in the present embodiment, pads are formed on the upper surface of the chip, and the pads 10 arranged on the edge (outer peripheral side) of the bare chip IC 1 correspond to the bonding terminals 4a, 5a.
The pads 11 arranged on the inner peripheral side of the bare chip IC1 with respect to the pads 10 at these edges are the inspection terminals 4b, 5b
Is equivalent to

The bare chip IC1 is mounted on a substrate, and the pads 10 (bonding terminals) arranged on the edge of the bare chip IC1 are electrically connected to peripheral circuits by wire bonding or the like.

In the bare chip IC 1 having the above configuration, the CS signal is applied in a state where a bias is applied between the bonding terminal 4 a of the Vdd terminals 4 a and 4 b and the Vss (ground) terminal 3 from outside the bare chip IC 1. When low, the PchMOS transistor 61 and the NchMO
Since both S transistors 62 are turned on, the transmission gate is turned on, and this bare chip IC1 is electrically connected to peripheral circuits. On the other hand, when the CS signal is at the high level, the two types of transistors 61 and 62 are both turned off, so that the transmission gate is turned off, and the paired bonding terminals 4a and 5a and the inspection terminals 4b and 5b are turned off. Electrical disconnection disconnects the bare chip IC1 from peripheral circuits.

Then, the bare chip IC1 is disconnected from the peripheral circuits, and the logic circuit block 2 is energized with the power supply, and is probed to the pads 11 corresponding to the inspection terminals 4b, 5b, thereby inspecting the bare chip IC1. Do.

According to the present embodiment, since the inspection terminals 4b and 5b and the bonding terminals 4a and 5a are provided, and the transmission gate is provided therebetween, the bare chip IC1 is removed from the peripheral circuit as described above. The bare chip IC1 can be electrically cut, and after the bare chip IC1 is mounted on the substrate, the bare chip IC1 can be independently tested.

In addition, since the bare chip IC 1 is electrically disconnected from the peripheral circuit for inspection, the bare chip IC 1 alone can be inspected for a leak current, a standby current, etc., and a highly reliable semiconductor can be obtained by improving testability. A device can be obtained.

Further, since the bonding terminals 4a, 5a are provided on the outer peripheral side of the bare chip IC1 with respect to the inspection terminals 4b, 5b, after the bare chip IC1 is mounted on the substrate by wire bonding or the like, the wires are connected to the inspection terminals. 4
b, 5b so that the inspection terminals 4
b, 5b.

Further, since the defective chip can be easily specified, the repair of the component can be performed more appropriately. In addition, failure analysis of what characteristic of the chip has failed becomes easy. In addition, by providing the test terminals 4b and 5b on the bare chip IC 1 side where high integration is possible, the area of the test terminals on the mounting substrate side can be significantly reduced. As a result, the substrate can be reduced in size,
In particular, the cost can be reduced in a ceramic multilayer substrate where the substrate is expensive.

In this embodiment, the transmission gate is turned off when the CS signal is at a high level, and the bare chip IC1 is electrically disconnected. However, when the CS signal is at a low level, the bare chip IC1 is disconnected. You may make it.

When the number of terminals of the bare chip IC 1 is small, the pads 10 and 11 are not provided at the edge of the bare chip IC 1 as in the present embodiment, but a pair is formed at the edge of the bare chip IC 1. Pads corresponding to the bonding terminals 4a and 5a and the inspection terminals 4b and 5b may be alternately arranged.

In this embodiment, hatching is applied to a non-cross-sectional view, but it is for convenience only and does not show a cross-section.

[Brief description of the drawings]

FIG. 1 is a bare chip IC according to a semiconductor device of an embodiment.
FIG.

FIG. 2 is a bare chip IC according to the semiconductor device of the embodiment;
FIG. 3 is a schematic top view of FIG.

FIG. 3 is a schematic diagram relating to inspection of a conventional semiconductor mounted product.

[Explanation of symbols]

1: semiconductor chip, 4a, 5a: bonding terminal,
4b, 5b: inspection terminals, 60: switch means.

Claims (5)

[Claims] 1. A semiconductor device comprising a semiconductor chip (1) mounted on a substrate and the semiconductor chip (1) electrically connected to a peripheral circuit, wherein the semiconductor chip (1) includes an internal circuit (2). ), And bonding terminals (4a, 4b, 5b) for electrically connecting to the peripheral circuits.
5a), wherein the bonding terminals (4a, 5a) are electrically connected to the inspection terminals (4b, 5b) via switch means (60). 2. The bonding terminal (4a, 5a).
And the inspection terminals (4b, 5b) are arranged on the upper surface of the chip, and the bonding terminals (4a, 5a) are located on the outer peripheral side of the inspection terminals (4b, 5b). 2. The semiconductor device according to claim 1, wherein: 3. A method for inspecting a semiconductor device, comprising: mounting a semiconductor chip (1) on a substrate; and electrically connecting the semiconductor chip (1) to a peripheral circuit. Inspection terminals (4b, 5b) electrically connected to the circuit (2), and bonding terminals (4a,
5a), wherein the bonding terminals (4a, 5a) are electrically connected to the inspection terminals (4b, 5b) via switch means (60). After electrically disconnecting the bonding terminals (4a, 5a) and the inspection terminals (4b, 5b) using the inspection terminals (4b, 5b), the semiconductor chip (1) is inspected. A method for inspecting a semiconductor device, comprising: 4. A semiconductor device comprising: inspection terminals (4b, 5b) electrically connected to the internal circuit (2); and bonding terminals (4a, 5a) for electrically connecting to peripheral circuits. A semiconductor chip characterized in that bonding terminals (4a, 5a) are electrically connected to said inspection terminals (4b, 5b) via switch means (60). 5. The bonding terminal (4a, 5a)
And the inspection terminals (4b, 5b) are arranged on the upper surface of the chip, and the bonding terminals (4a, 5a) are located on the outer peripheral side of the inspection terminals (4b, 5b). The semiconductor chip according to claim 4, wherein