JPH0576776B2 - - Google Patents
Info
- Publication number
- JPH0576776B2 JPH0576776B2 JP59027619A JP2761984A JPH0576776B2 JP H0576776 B2 JPH0576776 B2 JP H0576776B2 JP 59027619 A JP59027619 A JP 59027619A JP 2761984 A JP2761984 A JP 2761984A JP H0576776 B2 JPH0576776 B2 JP H0576776B2
- Authority
- JP
- Japan
- Prior art keywords
- inverters
- integrated circuit
- manufacturing process
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 238000012360 testing method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 5
- 230000005856 abnormality Effects 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 3
- 238000011179 visual inspection Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 238000012369 In process control Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010965 in-process control Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 238000012993 chemical processing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Description
【発明の詳細な説明】
＜技術分野＞
本発明はMOS集積回路半導体装置の製造工程
をチエツクするための製造工程管理用半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a semiconductor device for manufacturing process control for checking the manufacturing process of MOS integrated circuit semiconductor devices.
＜従来技術＞
半導体装置の製造工程、特に半導体基板に拡
散、エツチング等の処理を施こし、更に配線を形
成してMOS集積回路からなる半導体ウエハーを
製造する前半工程を管理することは、歩留りに大
きく影響し、コストと品質に最も大きな影響を及
ぼす。そのため半導体装置の製造にあたつては、
工程を適切に管理して歩留りを向上させるため
に、不良が生じた半導体チツプに対して不良原因
を解析する作業が行われている。この解析作業チ
ツプ全体に渡つて全域に顕微鏡を用いて目視検査
する方法によつて行われており、多くの時間を費
しているのが実状である。しかし目視検査を行つ
たとしても判別できない欠陥もあり、また電気的
動作不良箇所と目視検査異常箇所との対応が取れ
ない場合がしばしばある。<Prior art> Managing the manufacturing process of semiconductor devices, especially the first half of the process of applying processes such as diffusion and etching to the semiconductor substrate and then forming wiring to manufacture semiconductor wafers consisting of MOS integrated circuits, has a significant impact on yield. have the greatest impact on cost and quality. Therefore, when manufacturing semiconductor devices,
In order to properly manage processes and improve yields, work is being done to analyze the causes of defects in semiconductor chips that have defects. This analysis process is performed by visually inspecting the entire area of the chip using a microscope, which takes a lot of time. However, even if a visual inspection is performed, there are some defects that cannot be identified, and it is often impossible to correlate electrical malfunction locations with visual inspection abnormalities.
＜発明の目的＞
本発明はMOS集積回路半導体装置製造時の工
程管理における問題点に鑑みなされたもので、工
程管理に供するために特有の半導体チツプを作製
し、不良原因を解析し易く、短時間のうちに電気
的動作不良箇所を確実に検出して製造工程の管理
に反映させ得る製造工程管理用半導体装置を提供
する。<Purpose of the Invention> The present invention was made in view of the problems in process control during the manufacture of MOS integrated circuit semiconductor devices.The present invention is made in view of the problems in process control during the manufacture of MOS integrated circuit semiconductor devices. Provided is a semiconductor device for manufacturing process management that can reliably detect electrical malfunction locations in time and reflect them in manufacturing process management.
＜実施例＞
CMOS集積回路を製造する工程に適用する場
合の実施例を挙げて説明する。半導体基板１に形
成された入力端子２に互いに直列接続された複数
のインバータI1，I2…I2nを接続して形成する。尚
初段のインバータI1と入力端子２間には保護抵抗
３が挿入され、またインバータI1の入力端と電源
電圧間に保護ダイオード４，５が挿入されてい
る。<Example> An example in which the present invention is applied to a process of manufacturing a CMOS integrated circuit will be described. It is formed by connecting a plurality of inverters I 1 , I 2 . . . I 2n connected in series to an input terminal 2 formed on a semiconductor substrate 1. A protection resistor 3 is inserted between the first-stage inverter I 1 and the input terminal 2, and protection diodes 4 and 5 are inserted between the input terminal of the inverter I 1 and the power supply voltage.
上記インバータI1，I2…I2nは２個のインバータ
を単位セル６1，６2，…６ｍとして、第ｋ個目
（例えばｋ＝10）の単位セル6kの出力端と（ｋ＋
１）個目のセル入力端間に入力と並列に出力バツ
フア７1を介して出力端子８1を形成する。ｋ個の
単位セル毎に同様に出力端子８2，８3…を設け、
最終セル6mの出力端に出力端子８ｉを形成する。 The above-mentioned inverters I 1 , I 2 ...I 2n have two inverters as unit cells 6 1 , 6 2 , ... 6m, and the output terminal of the k-th (for example, k=10) unit cell 6 k and (k+
1) An output terminal 8 1 is formed between the input terminals of the second cell in parallel with the input via an output buffer 7 1 . Similarly, output terminals 8 2 , 8 3 . . . are provided for every k unit cells,
An output terminal 8i is formed at the output end of the final cell 6m.
上記各段のインバータI1〜I2nはいずれも第２
図に示す如くCMOSトランジスタで構成されて
いる。ＰチヤネルMOSトランジスタ９とＮチヤ
ネルMOSトランジスタ１０が電源ライン間に接
続されている。同図において太実線で示す入出力
ライン１１、両トランジスタ接続部１２及び各ト
ランジスタと電源ラインとの接続部１３はAl配
線によつて形成されるが、該Al配線１１〜１３
は回路をチエツクする過程で夫々の箇所の切断が
周辺回路に影響することなく実行可能なように、
例えば該当部分の下地酸化膜を平坦化が図られ、
しかも他の配線との間隔も充分にとられている。
隣接するインバータ間にはプロービングのための
ミニパツト１４が同様にAlによつて形成されて
いる。上記工程管理チツプは、セル数百個又は数
千個を１チツプとし、ツエツクされるべき集積回
路と同程度の集積度に構成することが望ましい。 The inverters I 1 to I 2n in each stage above are all connected to the second
As shown in the figure, it is composed of CMOS transistors. A P channel MOS transistor 9 and an N channel MOS transistor 10 are connected between the power supply lines. In the same figure, the input/output line 11, both transistor connection portions 12, and the connection portion 13 between each transistor and the power supply line, which are indicated by thick solid lines, are formed by Al wiring.
In the process of checking the circuit, each part can be disconnected without affecting the surrounding circuits.
For example, the underlying oxide film in the corresponding area is planarized,
Moreover, the distance between the wires and other wires is sufficient.
Mini-pats 14 for probing are similarly formed of Al between adjacent inverters. It is preferable that the process control chip has several hundred or several thousand cells in one chip, and has a degree of integration comparable to that of the integrated circuit to be checked.
ここで上記インバータ回路からなる集積回路を
製造する工程は、CPU、各種メモリ等のチエツ
クされるべきMOS集積回路を製造すウエハ前半
工程と同じ条件で製造される。即ち拡散、エツチ
ング、絶縁膜の形成、配線の形成等の条件を、チ
エツクされるべき工程と同じ条件によつて形成さ
れる。従つて上記工程を経て製造された半導体チ
ツプを解析することにより製造工程の不良原因を
解析することができる。 Here, the process of manufacturing the integrated circuit comprising the inverter circuit is performed under the same conditions as the wafer first half process of manufacturing MOS integrated circuits to be checked, such as CPUs and various memories. In other words, the conditions for diffusion, etching, formation of an insulating film, formation of wiring, etc. are the same as those of the process to be checked. Therefore, by analyzing the semiconductor chips manufactured through the above steps, it is possible to analyze the causes of defects in the manufacturing process.
上記構成のチツプに対して、ウエハテストは入
力端子２に矩形波信号を入力し、この入力信号の
反転信号が最終出力端子８ｉから出力されるか否
かを検出し、この出力信号が検出されれば良品チ
ツプと判別し得る。一方不良チツプについては以
下のようにして原因を解析が実行される。 For the chip with the above configuration, the wafer test inputs a rectangular wave signal to the input terminal 2, detects whether an inverted signal of this input signal is output from the final output terminal 8i, and detects whether or not this output signal is detected. If so, it can be determined that the chip is of good quality. On the other hand, for defective chips, the cause is analyzed as follows.
即ち与えられた矩形波入力信号ち対して、途中
段に設けた出力端子８1〜８ｉを用いて、どこの
段階で誤動作しているかをテストする。次に各イ
ンバータ毎に設けたミニパツド１４の用いてどの
セルで誤動作しているか、更にはセル内の２つの
インバータのどちらで誤動作が生じていかをテス
トする。上記電気的なテストのみならず目視検査
し、特に誤動作しているインバータを観察するこ
とが望ますい。上記テスト結果から不良原因を解
析するが、不良原因が判明しない場合には、Al
配線１１，１２，１３の切断等の処理により素子
を分離し、電気的特性の異常を調査する。更には
化学処理、SEM等を用いた詳細な解析を行つて
不良原因を究明する。上記工程管理用チツプの解
析結果に基づいで製造工程が管理され、MOS集
積回路半導体装置が製造される。 That is, for a given rectangular wave input signal, the output terminals 8 1 to 8i provided in the middle are used to test at what stage the malfunction occurs. Next, a mini pad 14 provided for each inverter is used to test which cell is malfunctioning, and furthermore, which of the two inverters in the cell is malfunctioning. In addition to the electrical tests mentioned above, it is recommended to perform a visual inspection, especially to observe malfunctioning inverters. Analyze the cause of the failure from the above test results, but if the cause of the failure cannot be determined,
The elements are separated by processing such as cutting the wirings 11, 12, and 13, and abnormalities in electrical characteristics are investigated. Furthermore, we conduct detailed analysis using chemical processing, SEM, etc. to determine the cause of the defect. The manufacturing process is controlled based on the analysis result of the process control chip, and a MOS integrated circuit semiconductor device is manufactured.
＜効果＞
以上本発明によれば、電気的特性のテストが容
易な回路構成をもつ集積回路を用いて製造工程を
管理するため、異常箇所の検出操作が簡単になり
また回路配線の切断を容易にしていため異常箇所
までの追跡が容易になり、不良原因の解析時間を
短縮化すると共に、制度を高めMOS集積回路の
製造工程の管理をし易くすることができる。<Effects> According to the present invention, since the manufacturing process is managed using an integrated circuit having a circuit configuration that allows easy testing of electrical characteristics, it is easy to detect abnormalities and to cut circuit wiring. This makes it easier to trace the location of the abnormality, shortening the time required to analyze the cause of the failure, and improving accuracy and making it easier to manage the manufacturing process of MOS integrated circuits.
第１図は本発明による一実施例の電気回路ブロ
ツク図、第２図は同実施例の要部回路図である。
１：半導体基板、２：入力端子、６1〜６ｍ：
インバータセル、８1〜８ｉ：出力端子、I1〜
I2n：インバータ、１１，１２，１３：Al配線、
１４：ミニパツド。
FIG. 1 is a block diagram of an electric circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a main part of the embodiment. 1: Semiconductor board, 2: Input terminal, 6 1 ~ 6m:
Inverter cell, 8 1 ~ 8i: Output terminal, I 1 ~
I 2n : Inverter, 11, 12, 13: Al wiring,
14: Mini pad.
Claims (1)
回路の上記プロセスチエツク専用集積回路であつ
て、半導体基板上の入出力端子間に複数のインバ
ータを直列に接続すると共に、途中段のインバー
タからテスト用パツドを導出し、上記インバータ
を相互に接続する配線を切断し得るに充分なスペ
ースをもつて形成してなり、上記プロセスと同一
のプロセスを経て製造されることを特徴とする製
造工程管理用半導体装置。1 This is an integrated circuit exclusively for process checking of integrated circuits manufactured through a predetermined wafer process, in which a plurality of inverters are connected in series between the input and output terminals on the semiconductor substrate, and test pads are connected from the inverters in the middle stage. A semiconductor device for manufacturing process control, characterized in that the semiconductor device is formed with sufficient space to derive the above-mentioned inverters and cut the wiring interconnecting the inverters, and is manufactured through the same process as the above-mentioned process. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2761984A JPS60170955A (en) | 1984-02-15 | 1984-02-15 | Semiconductor device for control of manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2761984A JPS60170955A (en) | 1984-02-15 | 1984-02-15 | Semiconductor device for control of manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60170955A JPS60170955A (en) | 1985-09-04 |
| JPH0576776B2 true JPH0576776B2 (en) | 1993-10-25 |
Family
ID=12225958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2761984A Granted JPS60170955A (en) | 1984-02-15 | 1984-02-15 | Semiconductor device for control of manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60170955A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110298484A1 (en) | 2009-03-11 | 2011-12-08 | Sharp Kabushiki Kaisha | Electronic circuit and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4832490A (en) * | 1971-09-01 | 1973-04-28 | ||
| JPS57133644A (en) * | 1981-02-12 | 1982-08-18 | Fujitsu Ltd | Semiconductor integrated circuit device |
-
1984
- 1984-02-15 JP JP2761984A patent/JPS60170955A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4832490A (en) * | 1971-09-01 | 1973-04-28 | ||
| JPS57133644A (en) * | 1981-02-12 | 1982-08-18 | Fujitsu Ltd | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60170955A (en) | 1985-09-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |