JPH113940A - Semiconductor device, evaluation of device and configuration of fundamental element circuit for characteristics evaluation - Google Patents

Semiconductor device, evaluation of device and configuration of fundamental element circuit for characteristics evaluation

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Publication number
JPH113940A
JPH113940A JP15407497A JP15407497A JPH113940A JP H113940 A JPH113940 A JP H113940A JP 15407497 A JP15407497 A JP 15407497A JP 15407497 A JP15407497 A JP 15407497A JP H113940 A JPH113940 A JP H113940A
Authority
JP
Japan
Prior art keywords
circuit
evaluation
teg
unused
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15407497A
Other languages
Japanese (ja)
Inventor
Masamichi Uehara
正道 上原
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP15407497A priority Critical patent/JPH113940A/en
Publication of JPH113940A publication Critical patent/JPH113940A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To make it possible to grasp the situation of the fundamental element characteristics of chips in the state of the delivery of the chips or subsequent to the delivery of the chips, by a method wherein a fundamental element for characteristics evaluation is created on an I/O cell region which is connected with an unused I/O terminal. SOLUTION: A fundamental element (TEG circuit) 104 for characteristics evaluation formed on a scribing line is created on an I/O cell region 103 which is connected with an unused I/O terminal part 10. As the TEG circuit 104, a circuit such as a transistor, a wiring, the connection of a wiring or a capacitor which is hitherto created on the scribing line, is created in the forms of the transistor, the wiring, the connection of the wiring and the capacitor, on the condition of different combination and the like and the evaluation of the circuit is possible. Moreover, also besides this circuit, it is also possible to create a circuit (a circuit which was necessary but taken off from the surface of the scribing line due to some reasons on the region) taken off from the surface of the scribing line. Here, if the transistor is created as the circuit 104, the calculation of the coefficient of an irregularity in the process for forming the circuit can be calculated with better accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O terminal connected to an unused input / output terminal (hereinafter referred to as a PAD) of a chip, particularly for a gate array of a semiconductor device.
Basic element for characteristic evaluation (TEG circuit) in O (input / output) area
The present invention relates to a semiconductor device for performing device evaluation by creating a device and a method for evaluating the semiconductor device.

[0002]

2. Description of the Related Art As shown in a partial view of a wafer in FIG.
TEG (Test Element Gro) which is a basic element for evaluating characteristics of transistors, resistors, and quality control
up, hereinafter referred to as TEG), and the in-plane variation relating to the characteristics of the basic elements in the wafer, the characteristics of the transistors, and the like were investigated.

However, the TEG must be formed within a limited width, and the number of transistors to be formed is also limited.
Also, since the wafer is scribed, the characteristics cannot be measured again if the wafer is diced.

As for the transistor characteristics, as a dedicated evaluation of this area, generally determined several points have been measured to infer the characteristics of the internal cell transistors of the IC chip.

[0005]

However, in the prior art, the TEG, which is a basic element for characteristic evaluation, is 100 μm.
It has to be created on a scribe line having a width of about m, and there is a problem that the size and the like are limited.

In addition, since the scribe line is cut by a dicing process when the chip is shipped, there is a problem that it is difficult to ascertain the shipping state or the basic element characteristic state of the chip after the shipment. .

Furthermore, the TEG on the scribe line has to be measured separately from the chip characteristics, so that there is a problem that a measurement time for evaluating the characteristics is required separately from the chip characteristics.

In addition, since it does not take much time for the measurement of the characteristic evaluation, only a few points can be measured for one wafer, and the data population is small. For this reason, there is a problem that the data for investigating the in-plane variation of the characteristics is not sufficient.

[0009]

A semiconductor device according to a first aspect of the present invention is characterized in that a TEG circuit is formed in an input / output cell region connected to an unused PAD.

According to the present invention, since the TEG is created in the input / output cell area larger than the width of the scribe line, the effect of being less restricted by the size of the area than on the scribe line is obtained.

A semiconductor device according to a second aspect of the present invention is characterized in that a quality control device evaluation circuit is created as the TEG according to the first aspect.

According to the present invention, since the circuit is not disconnected at the time of shipment, it is possible to ascertain the shipment state or the basic element characteristic state of the chip after shipment, thereby shortening the time required for failure analysis. This has the effect. Furthermore, since the transistor characteristics of each chip can be measured and more evaluation data can be obtained in one wafer than before, the effect of increasing the accuracy of the data of the in-plane variation on the wafer is achieved.

According to a third aspect of the present invention, there is provided a method for evaluating a semiconductor device, wherein measurement of a TEG circuit is performed simultaneously with evaluation of a normal functional circuit.

According to the present invention, it is not necessary to provide an environment setting and time separately from the functional circuit for the TEG circuit evaluation. This has the effect of reducing the time required for environment setting and the like required for evaluation.

A semiconductor device evaluation method according to a fourth aspect of the present invention is characterized in that unused PADs are continuously connected via a TEG circuit.

Usually, two PAs are used for measuring one TEG circuit.
Since D is required, only n / 2 TEG circuits can be measured with respect to the number n of unused PADs. However, according to the present invention, there is an effect that the number of n-1 TEG circuits can be measured with respect to the number n of unused PADs. Furthermore, by using the PAD that uses only the termination, the number n of unused PADs is
This has the effect that the number of n + 1 TEG circuits can be measured.

[0017]

According to the first and second aspects of the present invention, the TEG circuit is not cut even when dicing the wafer.

According to the third aspect of the present invention, it is possible to measure the TEG circuit at the time of evaluating the normal function circuit.

According to the fourth aspect of the present invention, the unused PA
By continuously using the number n of D, the TEG circuit evaluation number becomes n / 2
To n-1 or n + 1.

[0020]

FIG. 1 shows an embodiment of the present invention.
Reference numeral 101 denotes a used PAD (used input / output terminal). 102
Indicates an unused PAD (unused input / output terminal). 103
Indicates an I / O (input / output) cell. 104 indicates a TEG cell. Reference numeral 105 denotes an internal cell area.

In the gate array, several types of bulks having different sizes (wafers in which only basic elements have been formed before circuit wiring) are prepared, and chips manufactured under the same process conditions are combined in one series. To the user. Therefore, the user selects the most optimal bulk from among the prepared bulks in consideration of the circuit scale, cost, and the like. As a result, the number of PADs (input / output terminals) that the selected bulk has
There is a situation where the number of PADs required in a circuit required by the user is smaller. In such a case, there is an unused PAD when an actual circuit is created. Until now, the unused I / O (input / output) cell area of the unused PAD portion has also been unused.
Therefore, instead of the I / O cell, a TEG circuit formed on the scribe line or other necessary circuits is created in this unused I / O cell area to evaluate the characteristics of the basic element. And confirm the quality status.

For example, as shown in FIG.
It is assumed that there is an unused PAD adjacent to 2b. Conventionally, an I / O cell like 103 exists. However, instead of 103, a TEG circuit like 104 is created. 102a is one electrode for measuring the characteristics of the AL wiring 104 which is a TEG circuit, and 102b is
It becomes the other electrode for measuring the characteristics of the wiring 104.
As described above, the TEG circuit formed on the scribe using two adjacent unused PADs is replaced with the conventional I / O.
It can be created in the cell area and its characteristics can be examined with an unused PAD. Further, as a TEG circuit, it is possible to create a circuit conventionally formed on a scribe line, such as a transistor, wiring, wiring connection, a shape of a capacitor and the like, different combination conditions, and evaluate the circuit. Further, in addition to this, it is also possible to create a circuit that has been removed from the scribe line (a circuit that was necessary but has been removed for the sake of area). Here, if a transistor is formed as a TEG circuit, it is possible to calculate the coefficient of the process variation with higher accuracy. This is because conventionally, when evaluating a transistor circuit created on a scribe line, a predetermined number of points are measured and a process variation coefficient is calculated from the measured points. However, in this case, if necessary, the TEG circuit characteristics of all the chips can be measured by measuring them together at the time of chip characteristic evaluation. This is because the parameter of the data to be analyzed increases.

Further, as miniaturization progresses, there is a possibility that transistors having the same size on a mask but different sizes on a device may be produced due to the close-packed relationship of the transistors. The coarse and dense relationship is different between the scribe line and the internal cell area. By creating data equivalent to the internal cell area in the I / O cell area,
Characteristics close to the original transistor characteristics can be obtained.

Regarding the positional relationship of the unused PADs, even if they are far apart, they can be connected using the internal wiring area, so that they need not be particularly adjacent.

Further, by continuously connecting unused PADs, it is possible to reduce the number of PADs relative to the number of TEG measurement circuits as compared with the case where the PADs are not continuously connected.

For example, in 2PAD, only one type of TEG circuit can be measured, but by continuously connecting 3PADs, two types of TEG circuits can be measured.

FIG. 3 shows an embodiment in which 3PADs are continuously connected. Reference numeral 301 denotes a TEG circuit. 302
Is a wiring connecting between the TEG circuits. 303 is
Unused PAD used when evaluating each TEG circuit.
First, when measuring the characteristics of the TEG circuit 301a,
The measurement is performed using the PADs 303a and 303b. When measuring the characteristics of the TEG circuit 301b, the measurement is performed by using the PADs 303b and 303c. When the connection was not made continuously, only n / 2 TEG circuits could be measured with respect to the number n of PADs. This enables measurement of TEG circuits. Furthermore,
By using a PAD that uses only the end, n + 1 TEG circuits can be measured for the number of PADs n.

Also, by creating a TEG circuit using an unused PAD of a chip in this way, a prober for measuring the TEG on the scribe has been required, and an environment setting has also been required. This is a prober for evaluating the characteristics of the chip, which can be measured simultaneously with the evaluation of the characteristics of the chip.

[0029]

As described above, according to the method of manufacturing a semiconductor device of the present invention, there is an effect that the TEG circuit formation region is not restricted as much as the scribe line.

Further, it is possible to grasp the shipment state or the basic element characteristic state of the chip after shipment, and it is possible to shorten the failure analysis time.

Further, there is an effect that the accuracy of data of in-plane variation of transistors and other elements on the wafer is improved.

In addition, there is an effect that time required for setting an environment and the like, which is specially required for TEG circuit measurement, can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a plan view of a conventional semiconductor device.

FIG. 3 is a plan view of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 101 PAD used 102 Unused PAD 103 I / O cell area 104 Evaluation TEG 105 Internal cell area 201 · Scribe area 202 · · · · Chip area 301 · · · Evaluation TEG area 302 · · · · Connection wiring between TEGs 303 · · · Unused PAD

Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 21/822

Claims (4)

    [Claims]
  1. In a gate array having an internal cell region forming a logic circuit and an input / output cell region forming an input / output circuit, the input / output cell region connected to an unused input / output terminal includes a basic element for characteristic evaluation. A semiconductor device characterized by forming an element circuit.
  2. 2. A semiconductor device, wherein a quality control device evaluation circuit is created as the characteristic evaluation basic element circuit according to claim 1.
  3. 3. A device evaluation method in which measurement of a basic element circuit for characteristic evaluation is performed simultaneously with evaluation of a normal functional circuit.
  4. 4. An unused input / output terminal is continuously connected through the basic element circuit for characteristic evaluation according to claim 1,
    A characteristic evaluation basic element circuit configuration method that enables measurement of n-1 basic element circuits for characteristic evaluation with respect to the number n of unused input / output terminals. Further, by using the input / output terminals used only at the termination, n + 1 TEs can be provided for the number n of the unused input / output terminals.
    A method for configuring a basic element circuit for characteristic evaluation that enables G circuit measurement.
JP15407497A 1997-06-11 1997-06-11 Semiconductor device, evaluation of device and configuration of fundamental element circuit for characteristics evaluation Withdrawn JPH113940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15407497A JPH113940A (en) 1997-06-11 1997-06-11 Semiconductor device, evaluation of device and configuration of fundamental element circuit for characteristics evaluation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15407497A JPH113940A (en) 1997-06-11 1997-06-11 Semiconductor device, evaluation of device and configuration of fundamental element circuit for characteristics evaluation

Publications (1)

Publication Number Publication Date
JPH113940A true JPH113940A (en) 1999-01-06

Family

ID=15576329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15407497A Withdrawn JPH113940A (en) 1997-06-11 1997-06-11 Semiconductor device, evaluation of device and configuration of fundamental element circuit for characteristics evaluation

Country Status (1)

Country Link
JP (1) JPH113940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004006857A (en) * 2002-05-15 2004-01-08 Samsung Electronics Co Ltd Integrated circuit chip and its fabricating method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004006857A (en) * 2002-05-15 2004-01-08 Samsung Electronics Co Ltd Integrated circuit chip and its fabricating method

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Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20040907