JPH0555313A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To contrive to cut down checking time by a method wherein, when a non-repairable IC element is present on a semiconductor wafer in the pretest stage, the semiconductor wafer is judged as a defective article in the stage of contact check of the wafer test, and an operational margin check is abbreviated. CONSTITUTION:Pertaining to each IC element formed on a semiconductor substrate 2, a defective contact generating fuse 8 is connected at least to an electrode pad 4 which is provided on each IC element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer capable of shortening the time required for the electrical characteristic test of each IC element formed on a semiconductor substrate.

[0002]

2. Description of the Related Art Generally, in the process of manufacturing a semiconductor IC, a plurality of semiconductor chips are simultaneously formed on a semiconductor substrate due to crystal defects of Si semiconductor substrates forming a semiconductor wafer, stains in the manufacturing process, and the like. Since each IC element may cause a defect, before separating the semiconductor wafer into IC chips by separating each IC element, it is necessary to determine whether or not each IC element satisfies the required electrical characteristics in advance. It is necessary to check the state of the wafer.

By the way, each I formed on the semiconductor substrate
In the case where the C element is, for example, a RAM, the above-mentioned electrical characteristic test is conventionally performed as follows.

As shown in FIG. 2, first, a pre-test for checking whether or not the circuit normally operates for each memory cell is performed using a wafer prober or the like. In this pre-test, for example, when a memory cell forming one bit does not operate, the redundant circuit formed in advance for repair is laser-cut in the next laser trimming process, so that the redundant circuit is passed through. So that electricity can flow. However, since the number of redundant circuits to be formed is limited, if a large number of memory cells are defective at the same time in the pretest stage, it cannot be repaired.

In this pretest and laser trimming,
Since it is in the state of one semiconductor wafer before the dicing process for separating it as an IC chip, even if one IC element on the semiconductor substrate is found to be unrepairable at the pretest stage, only the defective IC element is separated and removed. Since this is not possible, the wafer is moved to the next wafer test in this state.

In this wafer test, a wafer prober is used to first perform a contact check for checking whether or not the electrode pad is connected to each internal memory cell. In this contact check, if there is a connection failure, the IC element is determined to be defective, and a defective mark is attached to the IC element so that the IC element can be distinguished from a non-defective IC element. For IC elements that have passed the contact check, an operation margin check is subsequently performed to check whether or not each internal memory cell normally operates. Then, in this operation margin check, when a certain memory cell has an abnormal operation, a defective mark is attached to the corresponding IC element so that the IC element can be discriminated from a non-defective IC element.

When this wafer test is completed, the semiconductor wafer is separated into individual IC elements by dicing.
After removing the IC chip with the defective mark as the C chip, only the good IC chip is transferred to the next assembly process.

[0008]

As described above, since the pretest to the wafer test are performed in the state of the semiconductor wafer, even if it is found that there is an unrecoverable IC element at the pretest stage, this is excluded. However, it is difficult to perform a wafer test. Moreover, the contact check in the wafer test merely confirms the connection state between the electrode pad and its internal circuit, and does not individually confirm the normality or abnormality of each memory cell. Even if the IC element is defective,
This contact check does not necessarily result in a defect,
Only when the final operation margin check for each memory cell is completed, the defective IC element is marked with the defective mark. Moreover, since the final operation margin check is to confirm the operation for each memory cell, it takes a long time to check.

As described above, even if it is known that there is an unrecoverable IC element in the semiconductor wafer at the pre-test stage, the final operation margin check is completed for all IC elements including the defective IC element. If it is not done, the mark cannot be marked as a defect, so that it takes extra time for checking in the wafer test, and there is a problem that the manufacturing efficiency of the IC chip is poor.

[0010]

The present invention has been made to solve the above-mentioned problems, and when it is found that there is an unrecoverable IC element at the pretest stage,
It is treated as a defect at the contact check stage of the wafer test, and the operation margin check can be omitted so that the check time can be shortened.

Therefore, in the semiconductor wafer of the present invention, each IC element formed on the semiconductor substrate is
For at least one electrode pad of the C element,
It is characterized by connecting a fuse for contact failure occurrence.

[0012]

In the above structure, if it is found in the pre-test stage that there is an IC element that cannot be repaired even if a redundant circuit is used, the electrode of the corresponding defective IC element is processed in the next laser trimming step. Laser cut the fuse connected to the pad. As a result, the electrode pad and its internal circuit are disconnected, so it is determined that there is a contact failure at the next contact check stage, so there is no need to perform the next operation margin check, and the check time is correspondingly shortened. it can.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram schematically showing a semiconductor wafer in which an IC element having an electrode pad and a fuse is formed on a semiconductor substrate.

In the figure, reference numeral 1 denotes the entire semiconductor wafer, 2 denotes a Si semiconductor substrate, and 4 denotes one of a large number of electrode pads provided in each IC element formed on the semiconductor substrate 2. Indicated at 6 is one internal circuit (N-channel MOS transistor in this example) connected to the electrode pad 4.

A feature of this embodiment is that a fuse 8 for contact failure generation is connected between the electrode pad 4 on the semiconductor substrate 2 and the MOS transistor 6.

In the above structure, as shown in the flow chart of FIG. 2, when it is found that there is an IC element which cannot be repaired even if a redundant circuit is used in the pre-test stage, in the next laser trimming step, The fuse 8 connected to one electrode pad 4 of the corresponding defective IC element is laser-cut. As a result, the electrode pad 8 and the MOS transistor 6 inside thereof are disconnected. Therefore, even if the wafer probe is brought into contact with the electrode pad 4 and a negative voltage is applied in the next contact check, this M
Since no current flows through the OS transistor 6, the IC element including the MOS transistor 6 is determined to have a defective contact at this stage.

Therefore, unlike the conventional case, it is not necessary to perform the next operation margin check, and the check time is shortened accordingly.

Although the fuse 8 is provided between the electrode pad 4 and the internal circuit 6 in the above embodiment, the present invention is not limited to this. For example, the fuse 8 may be provided between the internal circuit 6 and the ground terminal. Of course, the fuse 8 may be provided in the.

[0019]

According to the present invention, when it is found that there is an unrecoverable IC element at the pretest stage,
Since it can be treated as a defect at the contact check stage of the wafer test and the operation margin check can be omitted, the check time can be shortened and the manufacturing efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram schematically showing a semiconductor wafer in which an IC element having an electrode pad and a fuse is formed on a semiconductor substrate.

FIG. 2 is a flowchart showing a semiconductor wafer manufacturing process, in particular, an electrical characteristic test process.

[Explanation of symbols]

1 ... Semiconductor wafer, 2 ... Semiconductor substrate, 4 ... Electrode pad,
6 ... MOS transistor (internal circuit), 8 ... Fuse.

Claims (1)

[Claims] 1. A semiconductor wafer, characterized in that, for each IC element formed on a semiconductor substrate, a fuse for contact failure generation is connected to at least one electrode pad provided in each IC element.