JPH0554694A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the selection time including a defect relief process in a semiconductor storage device. CONSTITUTION:A fuse 502 in a program circuit 5 is disconnected to set a nose P to the high level. The level of this node P sets a circuit 3 to the conductive state to form a leak line between an input terminal 1 and the ground, thereby generating a defect of input/output leak. The generated defect is first checked to select a defective article without performing the other checks. Thus, the check time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art A semiconductor memory device has one of all memory cells.
If a defective memory cell exists even in a bit, it becomes a defective product, and it is becoming difficult to improve the yield as the capacity increases.

Therefore, for a defect occurring in a normal memory cell, a redundant memory cell is provided in advance in the chip, and when a defect is found in the normal memory cell by a test, a redundant circuit is used to use the normal memory cell. A defective memory cell in the inside is cut off in a circuit manner, and a remedy for connecting a redundant memory cell is performed. However, if the number of defective memory cells in the normal memory cells exceeds the number of redundant memory cells, it cannot be relieved, resulting in a defective product.

FIG. 4 is a flowchart showing the process from the end of the manufacturing process to the shipment of the product. Primary inspection in Figure 4,
The secondary inspection is an electrical characteristic inspection, and the primary inspection in FIG. 4 is an inspection process for finding a repairable item. The semiconductor chip formed on the wafer is judged by the primary inspection as to whether it is a non-defective product, a defective product that can be repaired, or a defective product that cannot be repaired. Is applied. After that, by the secondary inspection in FIG.
Good wafers are selected from wafers in which semiconductor chips of non-defective products, repair treatment-implemented products, and defective products are mixed, and only defective products are marked.

[0005]

The primary inspection and the secondary inspection are each divided into a plurality of stages.
Various tests such as current consumption, speed, and operating voltage have been conducted.

In the conventional semiconductor memory device, there is no method for identifying whether each chip is a non-defective product, a repair-processed product, or a non-repairable defective product in the primary inspection by the secondary inspection, and therefore, In the next inspection as well, it is necessary to inspect all chips step by step like the first inspection. Therefore, a chip determined to be unrepairable in the primary inspection is tested as a defective chip by performing the test in the secondary inspection to the same stage as the primary inspection.

A defective chip having a defect cause that is not detected in the initial inspection stage of the secondary inspection requires an inspection time as the inspection stage for detecting the defect cause is in the latter stage of the secondary inspection. As a result, the inspection time for one wafer becomes long. Particularly, in recent years, the number of memory cells has become enormous with the increase in capacity of semiconductor memory devices, so that the inspection requires a longer time. Therefore, the present invention has the above-described inspection time. In order to prevent a long time,
An object of the present invention is to provide a semiconductor memory device that can reduce the inspection time by adding a simple circuit.

[0008]

A semiconductor memory device of the present invention stores a circuit means for replacing a defective memory cell in a normal memory cell with a redundant memory cell for repair, and a memory for indicating that repair is impossible. And a circuit means for expanding at least a defect depending on the state of the program means.

[0009]

According to the present invention, by programming the chip that cannot be repaired in the primary inspection, the circuit is set so that it can be identified as a defective chip in the test in the initial stage of the secondary inspection. Therefore, the defective chip in the secondary inspection can be selected at an earlier stage than the stage of the test determined to be unrepairable in the primary inspection.

[0010]

1 is a circuit diagram showing an example of an embodiment according to the present invention. Reference numeral 5 in FIG. 1 denotes a program circuit, and the circuit 3 in FIG. 1 is a circuit for setting a defect depending on the state of the program circuit 5. In the circuit 3 in FIG. 1, the input terminal 1 is grounded. Fuse 5 of program circuit 5
When 02 is conductive, the node Q is at the power supply potential and is "H".
"High" level. The "High" level of the node Q is inverted by the inverter 501, and "L" is applied to the node P.
The ow "level appears. Since this level is applied to the gate of the circuit 3, the circuit 3 is turned off and the signal input from the input terminal 1 is input to the NOR gate 2.
When the fuse 502 is cut, the node Q becomes "Low" level, and when this level is input to the inverter 501, the "High" level appears at the node P. When the "High" level of the node P is applied to the gate of the circuit 3, the circuit 3 is turned on and the input terminal 1 is forcibly grounded. By this, input terminal 1
In addition to the leakage current flowing when the "High" level is input, the internal signal 4 is always "High", and the external control becomes impossible.

FIG. 2 is a circuit diagram showing an example of another embodiment according to the present patent. The circuit 5 in FIG. 2 is the same as the circuit 5 in FIG. 1 described above. When the fuse 502 is cut, the node P becomes the “High” level as described above.
The level of the node P is input to the NOR gate 2. Therefore, no matter what signal is input from the input terminal 1, the output of the NOR gate 2, that is, the internal signal 4 is always output at "Low" level. Therefore, if the input terminal 1 is used as a chip control signal terminal, the operation of the chip is completely stopped by cutting the fuse 502.
It is determined to be defective at the time of electrical characteristic inspection.

FIG. 3 is a circuit diagram showing an example of another embodiment according to the present patent. The circuit 5 surrounded by the broken line in FIG. 3 is the same circuit as that in FIGS. 1 and 2. Therefore, fuse 5
By disconnecting 02, the node P becomes "High" level, and a path for short-circuiting the power supply wiring 6 and the ground wiring 7 is created to turn on the circuit. As a result, at the time of the electrical characteristic inspection, it is determined that the power supply current is abnormal and the product is defective.

In the above-described embodiments, a new defect can be generated by cutting the fuse 502 in the program circuit 5 for the chip that cannot be repaired by the primary inspection. ..

The program circuit surrounded by a broken line in the above embodiment is given as a simple circuit example for the purpose of explanation. However, instead of cutting the fuse as described above, the resistance is changed by laser irradiation. Method of changing resistance, M
Similar results can be obtained by a method using a non-volatile memory element such as NOS or FAMOS. Also, the program circuit should be able to give opposite levels to the node P in FIG. 1, FIG. 2 and FIG. 3 in the non-programmed state and the programmed state. It is possible to cause each characteristic abnormality regardless of the means.

[0015]

According to the present invention described above, the chip 1
Products that cannot be repaired in the secondary inspection can be sorted out in the initial stage of the secondary inspection by expanding defects in the program circuit.

Therefore, there is an effect that the inspection time for the products can be reduced as well as the time required for the selection can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram of still another embodiment of the present invention.

FIG. 4 is a flowchart from an electrical characteristic inspection process of a manufactured semiconductor memory device to product shipment.

[Explanation of symbols]

 1 ... Input terminal 2 ... NOR gate 3 ... Fault setting circuit 4 ... Internal signal 5 ... Program circuit 501 ... Inverter 502 ... Fuse 503 ... Resistor 6 ... Power supply Wiring 7 ... Ground wiring P, Q ... Nodes in each figure

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/82 27/04 T 8427-4M

Claims (1)

[Claims] 1. A circuit means for replacing a defective memory cell in a normal memory cell with a redundant memory cell to relieve, a program means for storing that relieving is impossible, and a state of the program means. A semiconductor memory device comprising at least circuit means for magnifying a defect.