JPH05282892A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an inspection cost by shortening an inspection sorting time including the step of relieving a defective product in a semiconductor memory having a redundancy circuit. CONSTITUTION:If a fuse 302 of a programming circuit 3 is not melted, a 'high' level is present at a node P, a 'low' level of an inverted level of the node P by an inverter is present at a node Q, and one of the inputs of the NAND gate is always set to the 'low' level, and hence an output of a test output terminal 4 becomes a 'high' level irrespective of the input from a test input terminal 1. If the fuse 302 is melted, the node P is the 'low' level and the node Q becomes the 'high' level. Since one of inputs of the NAND gate is the 'high' level, if the terminal 1 is the 'high' level, a 'low' level is output to a test output terminal 4. Accordingly, propriety can be identified according to a state of the programming circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art A semiconductor memory device has one of all memory cells.
If a defective memory cell exists even in a bit, it becomes a defective product, and it is becoming difficult to improve the yield as the capacity increases.

Therefore, for a defect occurring in a normal memory cell, a redundant memory cell is provided in advance in the chip, and when a defect is found in the normal memory cell by a test, a redundancy circuit is used for the normal memory cell. A defective memory cell in the inside is cut off in a circuit manner, and a remedy for connecting a redundant memory cell is performed. However, if the number of defective memory cells in the normal memory cells exceeds the number of redundant memory cells, it cannot be relieved, resulting in a defective product.

FIG. 5 is a flow chart showing the process from the end of the manufacturing process to the shipment of the product. Primary inspection in Figure 5,
The secondary inspection is an electrical characteristic inspection, and the primary inspection in FIG. 5 is an inspection process for finding a repairable item. The semiconductor chip formed on the wafer is determined by the primary inspection as to whether it is a non-defective product, a defective product that can be repaired, or a defective product that cannot be repaired. Is applied. After that, by the secondary inspection in FIG.
Good wafers are selected from wafers in which semiconductor chips of non-defective products, repair treatment-implemented products, and defective products are mixed, and only defective products are marked.

[0005]

The primary inspection and the secondary inspection are each divided into a plurality of stages.
Various tests such as current consumption, speed, and operating voltage have been conducted.

In the conventional semiconductor memory device, whether each chip is a non-defective product in the primary inspection, is a repair treatment-implemented product, or is a defective product that cannot be repaired.
Since there is no way to identify it in the secondary inspection, it is necessary to inspect all chips in the secondary inspection in the same steps as in the primary inspection. Therefore, even if a chip is determined to be a non-defective product in the primary inspection, it is not determined to be a non-defective chip unless the same test as the primary inspection is performed again in the secondary inspection.

Since the same inspections as the primary inspection and the secondary inspection are performed on the non-defective chips, the inspection time for one wafer is long as a result. Particularly, in recent years, the number of memory cells has become enormous with the increase in capacity of semiconductor memory devices, so that the inspection requires a longer time.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of shortening the inspection time by adding a simple circuit in order to prevent the above inspection time from being lengthened.

[0009]

A semiconductor memory device of the present invention includes a circuit means for replacing a defective memory cell in a normal memory cell with a redundant memory cell for repair, and a program for storing a good product. Means and circuit means for outputting a signal capable of identifying a non-defective product according to the state of the program means.

[0010]

According to the present invention, by programming a chip which is determined to be non-defective in the primary inspection, a circuit is set so that it can be identified as a non-defective chip in the test in the initial stage of the secondary inspection. Therefore, the chips that are determined to be non-defective in the primary inspection are not subjected to the secondary inspection, or unnecessary inspection during the secondary inspection can be omitted.

[0011]

FIG. 1 is a circuit diagram showing an example of an embodiment of the present invention. The circuit 3 in FIG. 1 is a program circuit. When the fuse 302 of the program circuit 3 is not blown, the node P is at "High" level, and this level is inverted by the inverter 301 to bring the node Q to "Low" level. Therefore, one of the input levels of the NAND gate 2 is always "Low" whether the voltage applied to the test input terminal 1 is "High" level or "Low" level.
Since it is the level, the voltage level of the test output terminal 4 is always the “High” level. When the fuse 302 of the program circuit 3 is blown, the node P becomes “Lo”.
It becomes the w "level, and this level is inverted by the inverter to bring the node Q to the" High "level.
Since one of the inputs of the ND gate is always at the "High" level, when the "High" level is applied to the test input terminal 1, the "Low" level is output to the test output terminal 4. From the above, the state of the program circuit can be determined.

FIG. 2 is a circuit diagram showing another example of the embodiment of the present invention. A current is applied to the test input terminal 1, and if the fuse 5 is not cut off, it is conductive, and if it is cut off, it is not conductive, so that the program state can be determined.

FIG. 3 is a circuit diagram showing another example of the embodiment of the present invention. The circuit 7 in FIG. 3 is a control circuit, and the circuit 3
Is the same as the program circuit of FIG. Control circuit 7
The threshold voltage of the N-channel transistor is set so as to correspond to a test voltage higher than the normal use voltage of the semiconductor memory device, and the normal operation of the semiconductor memory device is not affected. When the normal use voltage is applied to the input terminal 6, the N-channel transistor of the control circuit 7 is in the OFF state, so that the test output terminal 4 is at the ground voltage regardless of the state of the program circuit 3. When the test voltage is applied to the input terminal 6, the N-channel transistor of the control circuit 7 is turned on. In this case, the fuse 302 of the program circuit 3
Is not disconnected, node P is "High"
Since this level is inverted by the inverter 301 and the node Q becomes "Low" level, the "Low" level is output to the test output terminal 4. When the fuse 302 is cut off, the node P is "Lo".
Since the level becomes w "and this level is inverted by the inverter 301 and the node Q becomes" High "level, the" High "level is output to the test output terminal 4. Therefore, the state of the program circuit 3 is changed. The voltage is output to the test output terminal only when the test voltage is applied, and the normal use voltage does not affect the input signal from the input terminal 6.

FIG. 4 is a circuit diagram showing another example of the embodiment of the present invention. The circuit 3 is the same program circuit as that shown in FIGS. 1 and 3, the circuit 8 is a switch circuit, and the circuit 9 is a control circuit. The threshold voltage of the N-channel transistor of the switch circuit 8 is set so as to correspond to the test voltage. When the normal use voltage is applied to the input terminal 6, the switch circuit 8 is in the OFF state and the node P is at the “Low” level. Therefore, from the operation of the above-mentioned program circuit, the node Q becomes "High" level and the P-channel transistor of the control circuit 9 becomes O.
In the FF state, there is no effect on the signal at the output terminal 10. When the test voltage is applied to the input terminal 6, the switch circuit 8 is turned on, and if the fuse 302 of the program circuit 3 is not blown, the node P becomes “High”.
Since the node Q becomes "h" level and the node Q becomes "Low" level, the control circuit 9 is turned on and the power supply voltage is output to the output terminal 10. The state in which the test voltage is applied to the input terminal 6 When the fuse 302 is blown at, the node P is at "Low" level and the node Q is at "Hig".
The power supply voltage is not output to the output terminal 10 because the control circuit 9 is turned off at the "h" level. Therefore, the input signal from the input terminal 6 and the output terminal 1 are not used during normal use.
The state of the program circuit appears at the output terminal 10 only when the test voltage is applied to the input terminal 6 without affecting the output signal output to 0.

In the above-described embodiments, the fuse 502 in the program circuit 5 is cut off from the chip which has become a non-defective product in the primary inspection. It can be identified as a non-defective product by various tests.

The program circuit surrounded by the broken line in the above embodiment is given as a simple circuit example for the purpose of explanation. However, instead of cutting the fuse as described above, the resistance is changed by laser irradiation. Method of changing resistance, M
Similar results can be obtained by a method using a non-volatile memory element such as NOS or FAMOS. This also applies to the fuse 5 shown in FIG.
Further, any circuit or means may be used for the program circuit as long as it can create a state opposite to that before programming and after programming.

The switch circuit 8 shown in FIG. 4 is composed of a plurality of N-channel transistors when the threshold voltage of the transistors does not correspond to the test voltage due to manufacturing variations. This is because the function of the switch circuit 8 is satisfied if there is even one device having a threshold voltage corresponding to the test voltage.
Therefore, the number of N-channel transistors forming the switch circuit 8 may be any number from one to any number depending on the accuracy of the manufacturing process.

[0018]

According to the present invention described above, the chip 1
The products judged to be non-defective products in the next inspection can be stored in the program circuit and selected in the initial stage of the secondary inspection.

Therefore, there is an effect that the inspection time for the products can be reduced as well as the time required for the selection can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a circuit for outputting a program circuit and its state as a signal when there is a test input terminal and a test output terminal according to the present invention.

FIG. 2 is a circuit diagram of a program circuit having a test terminal of the present invention.

FIG. 3 is a circuit diagram of a program circuit having a ready-made input terminal and a test output terminal according to the present invention and a circuit for outputting its state as a signal.

FIG. 4 is a circuit diagram of a circuit for outputting a program state of a program circuit as a signal when using a ready-made input terminal circuit and a ready-made output terminal of the present invention.

FIG. 5 is a flowchart from the end of the manufacturing process to product shipment in the conventional technology.

[Explanation of symbols]

 1 ... Test input terminal 2 ... NAND gate 3 ... Program circuit 301 ... Inverter 302 ... Fuse 303 ... Resistor 4 ... Test output terminal 6 ... Ready-made input Terminal 7 ... Control circuit 8 ... Switch circuit 9 ... Control circuit 10 ... Ready-made output terminals P, Q ... Nodes in each figure

Claims (1)

[Claims] 1. A circuit means for replacing a defective memory cell in a normal memory cell with a redundant memory cell for remedy, a program means for storing that a chip is a non-defective product, and a non-defective product depending on the state of the program means. A semiconductor memory device including circuit means for outputting a signal capable of identifying that