KR100191775B1 - Repair information storage and detection circuit of a semiconductor memory device - Google Patents

Abstract

The present invention relates to a repair information storage and detection circuit of a semiconductor memory device capable of storing information repaired at a wafer stage and determining whether or not to perform repair using the same at a package stage. In such a circuit, when a defect occurs in a memory cell at the wafer stage and repaired, repair information may be stored by fuse cutting of the repair information storage unit. Therefore, when a defect occurs in the package step, the number of repairs used in the wafer step may be known from the stored information, thereby increasing the repair efficiency of the semiconductor memory device.

Description

A circuit of restoring and detecting repair information of semiconductor memory device

Higher integration and increased memory capacity of the semiconductor memory device may cause problems in yield reduction and reliability of the semiconductor memory device due to particle and pattern defects at each step in the manufacturing process of the semiconductor memory device. It also brought about an increase. Therefore, in the semiconductor memory device, various repair structures are used to improve the yield, in order to repair the memory cells, that is, the bits caused by the above defects. In a semiconductor memory device using an electric repair scheme, the repair can be performed not only on the wafer stage but also on the memory cell in which the defect occurs in the package stage. In the wafer step, a memory cell in which defects are generated due to problems such as particles and pattern defects in each step of the manufacturing process can be repaired using the above-described repair structures.

In the package step, repair is also possible for power supply margin marginal defects occurring after the package and progressive defects due to burn in. In the wafer step, a defective memory cell can be repaired by using a repair structure within a repair structure that can be used sequentially. In the package step, only the remaining parts except for the repair structure used in the wafer step should be used. That is, in the semiconductor memory device using the 8-bit repair structure, when 5 bits are defective in the wafer step and the repair is performed using the repair structure, only 3 bits of defects can be repaired in the package step. In addition, in the package step, it is necessary to know how many repair bits are left in the repair structure used in the wafer step to determine whether to repair the defective package.

However, in the semiconductor memory device as described above, it is necessary to know how many repair bits are left in the repair structure used in the wafer stage to determine whether to repair a defective package. Not. Therefore, it is difficult to determine whether or not to perform repairing at the package stage, thereby reducing the repair efficiency of the semiconductor memory device.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and stores and detects repair information of a semiconductor memory device capable of determining whether or not to perform repair by using the information repaired at the wafer stage in the package stage. To provide a circuit.

1 is a block diagram showing a configuration of a repair information storage and detection circuit of a semiconductor memory device according to a preferred embodiment of the present invention;

2A to 2C are circuit diagrams showing circuits of the respective blocks of FIG. 1;

* Explanation of symbols on the main parts of the drawings

10: input unit 20: control unit

30: decoder 40: repair information storage

According to one aspect of the present invention for achieving the object as described above, when repairing a defect in a memory cell, after cutting certain fuses in the wafer step to store repair information, the repair step in the package step A repair information storage and detection circuit of a semiconductor memory device capable of determining whether or not a memory cell can be repaired by detecting information, wherein the repair information storage and detection circuit of the semiconductor memory device has a predetermined level higher than that of the first control signal and the first control signal from the outside. Receiving a second control signal and outputting a low level signal in response to the first control signal and a high level signal in response to the second control signal through a first output terminal; An input consisting of a plurality of high trip point buffers for outputting the two output signals and the signal inverted phase through the Unit; A control unit including a high trip point buffer configured to output a high level clock control signal when storing repair information in the wafer step or detecting the stored repair information in the package step; Receiving a plurality of output signals outputted from the high trip point buffers of the input unit and a clock control signal outputted from the controller, and selecting one of the output terminals in response to the high level signal; A decoder unit for outputting a low level signal to the plurality of unselected output terminals; Receives output signals output from the decoder, a clock signal applied from the outside, and a control signal input through a conductive path connected to a test terminal, and in response thereto stores repair information by cutting a predetermined fuse in the wafer stage. And a repair information storage unit which detects the stored repair information in the package step.

In a preferred embodiment of the circuit, the clock signal of the repair information storage unit is characterized in that a low level signal is applied in the normal operation of the semiconductor memory device and a high level signal is applied in the standby state.

In a preferred embodiment of this circuit, the repair information storage unit; A test terminal to which a control signal is applied from the outside; A conductive path electrically connected to the test terminal; An input terminal to which a clock signal is applied from the outside; A plurality of MOS transistors, each gate of which is connected to the input terminal, and a source-drain channel connected between each output terminal of the decoder unit and the conductive path; A plurality of fuses having one end connected to the conductive path; Each gate is connected to each output terminal of the decoder unit, and a plurality of MOS transistors are connected to each source-drain channel between the other terminal of the plurality of fuses and the second power supply terminal.

By such a circuit, it is possible to store the information repaired at the wafer stage and use it at the package stage to determine whether to perform the repair. Therefore, the repair efficiency of the semiconductor memory device can be improved.

Referring to FIG. 1, a repair information storage and detection circuit of a novel semiconductor memory device according to the present invention includes an input unit 10, a control unit 20, a decoder unit 30, and a repair information storage unit 40. . In order to store repair information in the repair information storage unit 40 at the wafer stage, both methods may be used by cutting and storing a fuse or storing information of an uncut state. If the repair information is stored by cutting the fuse, the clock control signal HI_CLK of the control unit 20 is a high level signal, and each of the high trip point buffers 12 of the input unit 10 is stored. Output low level signals HTB1, HTB1B-HTBn, HTBnB. Any one of the plurality of output terminals R1-Rn is selected by the signals HI_CLK, HTB1, HTB1B-HTBn, and HTB1B through the decoder unit 30 to output a high level signal. The fifth to seventh MOS transistors Q5-of the repair information storage unit 40 by the output signals R1-Rn of the decoder unit 30 and a low level clock signal CLK applied from the outside. The channel of Q7) is not conducting. In addition, a channel of a predetermined MOS transistor having a gate connected to the selected output terminal of each of the output terminals R1-Rn of the decoder unit 30 is turned on, and at this time, a fuse is applied by applying a predetermined level of voltage through the test terminal 7 Is cut. The repair information stored in the repair information storage unit 40 can be detected when the semiconductor memory device is in a standby state.

The current in the standby state flows at several tens of microamps or less, and the repair information can be detected by the amount of the standby current. In order to detect repair information stored in the repair information storage unit 40 by the fuse cutting in the package step, the decoder 10 through the input unit 10, the control unit 20, and the decoder unit 30 may be used as described above. One of the output terminals R0 to Rn of the unit 30 is selected. In this case, the clock signal CLK of the repair information storage unit 40 is applied at a high level so that a plurality of MOS transistors Q5 through Q7 having gates connected to the input terminal 6 to which the clock signal CLK is applied. ) Is turned on. Accordingly, a channel of a predetermined MOS transistor having a gate connected to the selected output terminal of the output terminals R1-Rn of the decoder unit 30 is turned on so that a standby current of several tens of microamps flows. If the fuse connected to the selected MOS transistor is not cut, a current of several hundred microamps or more flows. Based on the above result, the repair information may be detected in the package step.

According to such a circuit, when a defect occurs in a memory cell at the wafer stage and repaired, the repair information may be stored by cutting the fuse of the repair information storage unit 40. When the defect occurs in the package step, the number of repairs used in the wafer step can be known from the stored information. Therefore, the repair efficiency of the semiconductor memory device can be improved.

1 is a block diagram illustrating a configuration of a repair information storage and detection circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a repair information storage and detection circuit of a semiconductor memory device may store repair information by cutting predetermined fuses at a wafer stage when repairing a defect in a memory cell, and then storing the repair information at a package stage. Information can be detected to determine how many memory cells can be repaired. The input unit 10 receives a first control signal Vcc and a second control signal Vcc + a having a predetermined level higher than that of the first control signal Vcc from the outside, and receives the first output terminal 2. Outputs a low level signal in response to the first control signal Vcc and a high level signal in response to the second control signal Vcc + a It consists of a plurality of high trip point buffer 12 for outputting the two output signal and the signal inverted phase. In addition, the control unit 20 may output the high level clock control signal HI_CLK when the repair information is stored in the wafer step or when the stored repair information 40 is detected in the package step. Consists of

The decoder 30 may include a plurality of output signals HTB1, HTB1B-HTBn, and HTBnB output from each of the high trip point buffers 12 of the input unit 10, and a clock control signal output from the controller 20. HI_CLK) is input, and in response, one of the plurality of output terminals R0-Rn is selected to output a high level signal and a low level signal to the plurality of non-selected output terminals. The repair information storage unit 40 outputs the output signals R0-Rn output from the decoder unit 30, a clock signal CLK applied from the outside, and a conductive path L1 connected to the test terminal 7. In response to the control signal TS input through the controller, repair information is stored in the wafer stage by a predetermined fuse cutting, and then the stored repair information is detected in the package stage. In this case, the clock signal CLK of the repair information storage unit 40 is applied with a low level signal in a normal operation of the semiconductor memory device and a high level signal in a standby state.

2 is a circuit diagram of a repair information storage and detection circuit of a semiconductor memory device according to a preferred embodiment of the present invention.

Referring to FIG. 2, a repair information storage and detection circuit of a semiconductor memory device according to an embodiment of the present invention may include an input unit 10 including a plurality of high trip point buffers 12, a control unit 20, and a decoder unit. 30 and a repair information storage unit 40. Each of the high trip point buffers 12 of the input unit 10 is applied with the first and second power supply voltages Vcc and Vss through the first and second power supply terminals 4 and 5, respectively. One of the control signal Vcc and the second control signal Vcc + a is applied through the input terminal IN1. A predetermined signal is output through the first output terminal 2 and a signal inverted in phase of the predetermined signal is output through the second output terminal 3 across the input unit 10. In the first MOS transistor Q1 having a gate connected to the input terminal 1, a source-drain channel is connected between the input terminal 1 and the first connection point N1 and connected to the first power terminal 4. In the second MOS transistor Q2 having a gate connected thereto, a source-drain channel is connected between the first power supply terminal 4 and the first connection point N1.

In the third MOS transistor Q3 having a gate connected to the first power terminal 4, a source-drain channel is connected between the first connection point N1 and the second connection point N2, and the third MOS transistor is connected to the third MOS transistor Q3. The bulk of Q3 is connected to said first connection point N1. In addition, a source-drain channel is connected between the second connection point N2 and the second power supply terminal 5 in the fourth MOS transistor Q4 having a gate connected to the second power supply terminal 5. First and second inverters I1 and I2 are connected in series between the second connection point N2 and the first output terminal 2, and the second terminal is connected to an output terminal of the first inverter I1. The output terminal 3 is connected. The controller 20 includes a high trip point buffer 14 that outputs a high level clock control signal HI_CLK when storing repair information or reading the stored information in the repair information storage unit 40. It is. The decoder unit 30 also includes a plurality of NAND gates G1-G2 for coding the signals HTB1, HTB1B-HTBn, and HTBnB outputted from the high trip point buffer 12 of the input unit 10. And clock control signals HI_CLK of the controller 20 are input as control signals of the plurality of NAND gates G1-G2, respectively.

Inverters I3 and I4 are connected to output terminals of the respective NAND gates G1-G2, respectively, and have n n output terminals R1-R7 of 2 for n inputs of the input unit 10. have. The repair information storage unit 40 cuts the fuse in response to a signal applied from each output terminal R1-R7 of the decoder unit 30 and a clock signal CLK applied from the test terminal 7 and the outside. The repair information is stored by. The repair information storage unit 40 is connected to a conductive path L1 to which a control signal TS is applied from the test terminal 7. In addition, the plurality of MOS transistors Q5 to Q7 having their gates connected to the input terminal 6 to which the clock signal CLK is applied from the outside are connected to the respective output terminals R1 to R7 of the decoder unit 30. Source and drain channels are respectively connected between the conductive paths L1. The plurality of fuses F1 to F3 have one end connected to the conductive path L1 and a plurality of MOS transistors having a gate connected to each output terminal R0 to R7 of the decoder unit 30 ( Q5-Q7 are source-drain channels connected between the other terminal of the plurality of fuses F1-F3 and the second power supply terminal 5, respectively.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 and 2A to 2C.

As shown in FIG. 1, the repair information storage and detection circuit of the semiconductor memory device according to the present invention outputs an input unit 10 including a plurality of high trip point buffers 12 and a clock control signal HI_CLK. A decoder 20 for outputting a selection signal using the control unit 20, the output signals HTB1, HTB1B-HTBn, and HTBnB of the input unit 10 and the output signal HI_CLK of the control unit 20 as an input signal ( 30, the repair information is stored at the wafer stage in response to the control signals TS applied through the output signals R1-R7, the clock signal CLK, and the test terminal 7 of the decoder unit 30. Or a repair information storage unit 40 for detecting the stored information in a package step. Here, each of the high creep point buffers 12 and 14 of the input unit 10 and the control unit 20 is predetermined compared to a power supply voltage Vcc (hereinafter, referred to as a first control signal) at each of the input terminals IN1 to INn and IN. It is operated when the high level second control signal Vcc + a is input to output a high level signal. On the other hand, when the first control signal Vcc is applied to each of the input terminals, the first MOS transistor Q1 drops by a voltage level corresponding to a threshold voltage, so that the depletion type third MOS transistor Q3 of the P channel is provided. The channel of N is negatively connected so that the output signals HTB1, HTB1B-HTBn, and HTBnB always maintain a low level. In addition, the input terminals IN1 to INn and IN of the high trip point buffers 12 and 14 may use an address / data output / clock pin in a package step. In addition, the clock signal CLK applied to the gates of the fifth to seventh MOS transistors Q5 to Q7 of the repair information storage unit 40 stores the repair information at the wafer stage and when the semiconductor memory device normally operates. In normal operation, the signal is applied to the low level and to the high level in the standby state.

First, when the semiconductor memory device operates normally, the first control signal Vcc is applied through the respective input terminals IN1 to INn of the high trip point buffer 12 of the input unit 10 so that the second MOS transistor is applied. The channel of Q2 is not conducting and is maintained at a low level at each first output terminal 2 during this period. As described above, the clock signal CLK applied to the repair information storage unit 40 is also applied at a low level during this period. Therefore, the decoder 30 also outputs a low level signal because the output signals HTB1 to HTBn of the input unit 10 and the clock control signal HI_CLK of the control unit 20 are maintained at a low level. . The repair information storage unit 40 which receives the clock signal CLK and the output signals R0 to R7 of the decoder unit 30 does not operate. When the semiconductor memory device is in the standby state, the clock signal CLK applied to the repair information storage unit 40 is applied at a high level. Therefore, the channel of the fifth to seventh MOS transistors Q5 to Q7 connected to the input terminal 6 to which the clock signal CLK is applied is conductive. Even during this period, the respective output signals HTB1-HTBn and the clock control signal HI_CLK of the input unit 10 are kept at a low level. Since the output signals of the NAND gates G1-G2 of the decoder unit 30 controlled by the clock control signal HI_CLK are output at a high level, the respective output signals R1-R7 of the decoder unit 30 are output. In this state, the channel of the eighth to tenth MOS transistors Q8 to Q10 of the repair information storage unit 40 is not conducting. Therefore, even in the standby state, since there is no current path in the repair information storage unit 40, the normal operation of the semiconductor memory device is not affected.

A method of storing repair information in a repair information storage and detection circuit according to the present invention for a memory cell in which a defect occurs at the wafer stage is as follows. The capacity for storing the repair information varies depending on the design, but an 8-bit repair structure will be described here. The repaired information storing method in the repair information storage unit 40 may be used both when the fuse of the repair information storage unit 40 is cut and when the fuse is not cut. That is, the repair information is determined according to whether the fuse is cut. In the 8-bit structure, three high trip point buffers 10 of the input unit 10 are required. In addition, the clock control signal HI_CLK is applied at a high level when detecting the repair information at the time of fuse cutting (repairing the repair information) and at the package stage, and at a low level when the standby information is detected.

In order to cut the first fuse F1 of the repair information storage unit 40, a first control signal (1) is input to each input terminal IN1-INn of each high trip point buffer 12 of the input unit 10. When Vcc) is applied, each output signal HTB1-HTBn is kept at a low level, and as described above, the clock control signal HI_CLK is at a high level. The first NAND gate G1 is selected among the NAND gates G1 to G2 of the decoder unit 30 receiving the two signals, and a high level signal is output through the output terminal R1. Accordingly, the channel of the eighth MOS transistor Q8 having a gate connected to the selected output terminal R1 is turned on, and the first fuse F1 is cut when a predetermined voltage is applied through the test terminal 7. At this time, a low level signal is applied to the gates of the remaining MOS transistors except for the eighth MOS transistor Q8, so that the channels of the respective MOS transistors are not conducting. Therefore, fuses connected to one end of each of the MOS transistors are not cut. In the same manner as described above, when the second control signal Vcc + a is applied to each input terminal of each high trip point buffer 10 of the input unit 10, each output signal HTB0 to HTBn has a high level. do. The seventh output terminal R7 is selected by the output signals HTB0-HTBn and the high level clock control signal HI_CLK of the input unit 10, and the repair information is obtained by cutting the third fuse F3 using the output signal R7. Can be stored.

In the method of detecting the repair information stored in the repair information storage unit 40 by the above-described method in the package step, the case where the fuse is cut in the wafer step and stored in the first step is as follows. In order to detect repair information stored at the wafer stage in the package stage, it is possible when the semiconductor memory device is in a standby state, and requires input of each high trip point buffer 12 of the input unit 10. When the semiconductor memory device operates normally, the standby current flows for several tens of microamps or less, and the repair information may be determined as the amount of the standby current. In the standby state, the clock signal CLK applied to the repair information storage unit 40 shown in FIG. 2 is in a high level state, and the repair information stored in the repair information storage unit 40 is determined whether the fuse is cut or not. Is determined accordingly. That is, when the first fuse F1 is not cut, when the input signals of the high trip point buffer 12 are all at the low level and the clock control signal HI_CLK is at the high level in the standby state, the first output is performed. Terminal R1 is selected to output a high level signal. The output signal conducts the channels of the fifth and eighth MOS transistors Q5 and Q8 of the repair information storage unit 40 so that a current path exists so that a current of several hundred microamps or more flows even in the standby state.

Therefore, when the first fuse F1 is cut off, a standby current of several tens of microamps or less flows as in the normal operation. This amount of standby current indicates how much of the repair structure was used at the wafer stage. If five repair structures are used in the wafer stage among the 8-bit repair structures, five fuses corresponding thereto are cut. When the output terminals R1 to R7 are selected using the respective input signals of the high trip point buffers 12 in the package step, the fuse is cut even when the output terminals R1 to R4 are selected so that the current path is reduced. Since it is not present, normal standby current flows. Therefore, when the output terminals R5-R7 are selected, the standby current flows over several hundred microamps because the fuse is not cut. The results show that the repair structure has three bits that can be used at the package level. If the fuse is not cut at the wafer stage and stored as repair information, define that the fuse is not cut as the number of repair structures used at the wafer stage. If the repair information is stored, the standby current flows for several hundred microamps or more, and since the fuse is cut in the repair information storage unit 40, the standby current flows for several tens of microamps or less. Thus, information on the remaining number of repair structures available in the package step can be obtained. The repair information in the package step is determined by the amount of current in the standby state, which varies depending on whether the repair information storage unit 40 cuts the fuse in the wafer step.

As described above, in the case where a defect occurs in the memory cell during the wafer step, repair information may be stored by fuse cutting of the repair information storage unit. When the defect occurs in the package step, the stored information may be detected to determine the number of repairs used in the wafer step. Therefore, the repair efficiency of the semiconductor memory device can be improved.

Claims (3)

When a defect occurs in a memory cell, when repairing it, a predetermined fuse is cut at the wafer stage to store repair information, and then, in the package stage, the repair information is detected to determine how many memory cells can be repaired. In a repair information storage and detection circuit of a semiconductor memory device, A first control signal Vcc and a second control signal Vcc + a having a predetermined level higher than that of the first control signal Vcc are received from the outside, and the first control signal is received through a first output terminal 2. Outputs a low level signal in response to (Vcc) and a high level signal in response to the second control signal (Vcc + a), the second output signal being in phase with the two output terminals (3) An input unit 10 including a plurality of high trip point buffers 12 for outputting an inverted signal; A control unit (20) comprising a high trip point buffer (14) for outputting a high level clock control signal (HI_CLK) when storing repair information in the wafer step or detecting the stored repair information in the package step; The plurality of output signals HTB1, HTB1B-HTBn, and HTBnB output from the high trip point buffer 12 of the input unit 10 are received, and the clock control signal HI_CLK output from the control unit 20 is received. A decoder 30 which selects any one of the plurality of output terminals R1-R7 in response to output a high level signal, and outputs a low level signal to the plurality of unselected output terminals; Output signals R1 to R7 output from the decoder unit 30, a clock signal CLK applied from the outside, and a control signal TS input through the conductive path L1 connected to the test terminal 7. And a repair information storage unit 40 which receives the input and stores the repair information by predetermined fuse cutting in the wafer step, and then detects the stored repair information in the package step. Repair information storage and detection circuit. The semiconductor device of claim 1, wherein the clock signal CLK of the repair information storage unit 40 is supplied with a low level signal in a normal operation of the semiconductor memory device and a high level signal in a standby state. Repair information storage and detection circuit of the memory device. The method of claim 1, wherein the repair information storage unit 40; A test terminal 7 to which a control signal TS is applied from the outside; A conductive path (L1) electrically connected to the test terminal (7); An input terminal 6 to which a clock signal CLK is applied from the outside; A plurality of MOS transistors, each gate of which is connected to the input terminal 6, and a source-drain channel connected between each output terminal R0-R7 of the decoder unit 30 and the conductive path L1 ( Q5-Q7); A plurality of fuses F1 to F3 having one end connected to the conductive path L1; Each gate is connected to each output terminal R1-R7 of the decoder unit 30, and each source-drain channel is connected between the other terminal of the plurality of fuses F1-F3 and the second power supply terminal 5. And a plurality of connected MOS transistors (Q8-Q10).