KR100205545B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device capable of improving redundancy efficiency and selectively repairing redundant sub bit lines corresponding to the number of sub bit lines connected to a defective memory cell. By such a device, when a defect occurs in a memory cell and the defective memory cell is repaired as a redundant memory cell, as in the prior art, the entire sub bit line connected to the defective memory cell and the entire sub bit line to which the normal memory cell is connected are not simply repaired. Only redundant sub bit lines corresponding to the generated memory cells can be repaired selectively. Therefore, not only the entire memory cell block can be repaired as a redundant cell block but also the redundancy efficiency can be improved.

Description

Semiconductor memory device

FIG. 1 is a block diagram illustrating a schematic configuration of a semiconductor memory device having a conventional redundant free decoder.

Referring to FIG. 1, in a conventional semiconductor memory device, a plurality of sub bit line pairs SBLi0 to SBLi3, SBLBi0 to SBLBi3 to which memory cells MC are connected, and an external selection signal YAi0 to YAi3 and YABi0 to YABi3 are provided. A plurality of transfer transistors T1, T2, T3, T4, and TB1 having gates connected to the plurality of selection signal lines SLi0 to SLi3, SLBi0 to SLBi3 and to the lines SLi0 to SLi3 and SLBi0 to SLBi3, respectively. And a plurality of memory cell blocks 10 including a main bit line MBL0 connected to the plurality of sub bit line pairs SBLi0 to SBLi3 and SBLBi0 to SBLBi3 through TB2, TB3, and TB4; Main column decoder having a plurality of column decoders for outputting a plurality of selection signals YB0-YBn for selectively connecting any one of the main bit lines MBL0 of the block 10 to the bit lines B / L. Block 30 and the plurality of selection signals YB0 to YBn. A plurality of NMOS transistors IS0 to ISn connected to each other and a memory cell MC connected to the plurality of sub bit lines SBLi0 to SBLi3 when a defect occurs, to replace the plurality of memory cell blocks 10. Redundant memory cell blocks 20 having the same configuration as the N-th memory cell 20 and a redundant memory cell block corresponding to a memory cell block of a sub bit line to which the defective memory cell MC is connected. It consists of a redundant predecoder block 40 having a plurality of redundant predecoder corresponding to the blocks 20.

In the conventional semiconductor memory device illustrated in FIG. 1, when a defect occurs in the memory cell MC of the memory cell block 10, a redundancy for decoding a defective address signal corresponding to the defective memory cell and replacing it with a redundant memory cell is shown. A circuit is provided. Therefore, the defective memory cells MC of the memory cell block 10 are repaired by the redundant memory cells RMC of the redundant memory cell block 20 corresponding thereto. In this case, the defective address signal specifying the defective memory cell is used to designate a corresponding block among the plurality of redundant memory cell blocks for repairing the defective memory cell through the redundant predecoder 40. In order to perform this function, a defective address input unit 44 such as a fuse circuit capable of detecting a defective address signal and a redundant bit line RMBL of the redundant memory cell block 20 are selected from the detected defective address signal. The redundant column free decoder 40 is required.

2 is a block diagram showing the configuration of a conventional redundant free decoder.

Referring to FIG. 2, when a defect occurs in the memory cell MC of the memory cell block 10, the precharge unit 42 determines the conductive path L1 in response to a control signal CSB applied from the outside. Charge to the voltage level of. The defect address input unit 44 connects the conductive path L1 to the second power supply terminal 2 when there is no defect in the memory cell MC of the memory cell block 10, and connects the memory cell MC to the memory cell MC. If a fault occurs, corresponding fault addresses CAi0 to CAi3 and CABi0 to CABi3 are inputted to block the second power supply terminal 2 connected to the conductive path L1. The controller 48 receives signals charged in the plurality of conductive paths L1 corresponding to the plurality of redundant free decoders 40, and outputs the plurality of selection signals output from the main column decoder 30 ( Output a control signal RRDT to block YB0-YBn). The output unit 46 receives a signal charged in the conductive path L1, and outputs a selection signal RYBn for selecting a redundant memory cell block 20 corresponding to the defective memory cell MC.

3 is a circuit diagram illustrating a circuit of the redundant free decoder of FIG. 2.

Referring to FIG. 3, the redundant free decoder includes a first power supply terminal 1 to which a power supply voltage Vcc is applied and a second power supply terminal 2 to which a ground voltage Vss is applied. The precharge unit 42 includes a first fuse F1 connected between the first power supply terminal 1 and the first connection point N1, the first connection point N1, and the second power supply terminal 2. A first MOS transistor having a gate connected to the resistor R1 connected to the first connection point N1 and a source-drain channel connected between the first power supply terminal 1 and the second connection point N2. Q1), an inverter I1 for inverting and outputting a phase of the signal charged at the first connection point N1, and a gate is connected to an output terminal of the inverter I1, and the first connection point N1 and the first connection point are connected to each other. A source-drain channel is connected in series between the second MOS transistor Q2 having a source-drain channel connected between the two power supply terminals 2, and the second connection point N2 and the second power supply terminal 2. Gates are connected to control terminals 7 to which control signals CSB are applied from the outside; The third and fourth MOS transistors Q3 and Q4 have a conductive path L1 connected between the source and drain channels. Here, the first and third MOS transistors Q1 and Q3 are P-type conductive channels, and the second and fourth MOS transistors Q2 and Q4 are N-type conductive channels.

The defective address input unit 44 is connected to the plurality of first fuse groups F2, F4, F6, and F8 having one end connected to the conductive path L1, and to the memory cell MC of the memory cell block 10. When a fault occurs, each gate is connected to each of the input terminals 3, 4, 5, and 6 to which the corresponding fault addresses CAi0 to CAi3 and CABi0 to CABi3 are applied, and the first fuse group F2 and F4 are connected. And a plurality of MOS transistors Q5, Q7, Q9 and Q11 having a source-drain channel connected between the other terminal of F6 and F8 and the second power supply terminal 2, and the conductive path L1. A plurality of second fuse groups F3, F5, F7, and F9 having one end connected to the plurality of inverters, and a plurality of inverters I2, I3, and I4 that invert and output phases of the defective addresses CAi0 to CAi3 and CABi0 to CABi3. , I5 and a gate connected to each output terminal of the plurality of inverters I2, I3, I4, and I5, and the other terminal of the second fuse group F3, F5, F7, and F9 and the second electric terminal. A plurality of MOS transistors Q6, Q8, Q10, and Q12 are connected to the source-drain channel between the original terminals 2, respectively.

In addition, the output unit 46 for outputting a signal for selecting any one of the redundant memory cell blocks 20 shown in FIG. 1 receives a signal charged in the conductive path L1 and receives a plurality of inverters ( A signal output through I6, I7, and I8 and a NOR gate G1 connected to input terminals are respectively connected to the third connection point N3. The controller 48 receives signals in which the phases of the signals charged in the plurality of conductive paths L1 corresponding to the plurality of redundant predecoder 40 are inverted and are output from the main column decoder 30 in response thereto. The NAND gate G2 outputs a control signal RRDT for blocking the plurality of selection signals YB0 to YBn.

Hereinafter, an operation of a semiconductor memory device having a conventional redundant free decoder will be described in detail with reference to FIGS. 1 to 3.

The conductive path L1 of the redundant predecoder 40 illustrated in FIG. 3 has the first and second fuse groups F2, F4, F6, F8, F3, F5, F7, and F9 when no defect occurs in the memory cell. ) To maintain a low level through a predetermined fuse. For convenience of description, when a defect occurs in the memory cell MC of the memory cell block 10 of the semiconductor memory device shown in FIG. 1, the defect is replaced with the redundant memory cell RMC of the redundant memory cell block 20. Let's do it. As described above, when the defective memory cell MC is repaired to the redundant sub bit line RSBL corresponding to the connected sub bit line SBL, the first fuse F1 of the precharge unit 42 shown in FIG. ) Is cut by applying a predetermined signal from the outside.

When the first fuse F1 is cut, a high level is applied to the gate of the second MOS transistor Q2 through the first inverter I1 to conduct a channel. In addition, a second power supply terminal 2 having a low level is connected to the gate of the first MOS transistor Q1 through the second MOS transistor Q2 to conduct a channel. At this time, when the control signal CSB applied from the outside is applied at a low level, the channel of the third MOS transistor Q3 is turned on and the power supply voltage Vcc transferred through the channel of the first MOS transistor Q1 is It is charged to the conductive path L1. The plurality of MOS transistors Q5, Q7, Q9 and Q11 and the plurality of MOS transistors Q6, which receive the defect address signals CAi0 to CAi3 and CABi0 to CABi3 corresponding to the defective memory cell MC, respectively. The fuse corresponding to the address of the defective memory cell MC is cut out of the first and second fuse groups F2, F4, F6, F8, F3, F5, F7, and F9 connected to Q8, Q10, and Q12, respectively. . Thereafter, when the defective address signals CAi0 to CAi3 and CABi0 to CABi3 are input, the conductive path L1 charged by the precharge unit 42 to the power supply voltage Vcc is maintained at the power supply voltage Vcc. .

In addition, the signal RYBn for selecting the redundant memory cell block 20 corresponding to the defective memory cell MC through the output unit 46 receiving the signal charged in the conductive path L1 is at a high level. Is output. In addition, the controller 48, which receives a plurality of signals in which the phase of the signal charged in the conductive path L1 is inverted, also outputs a high level signal together with the output unit 46. The operation of the decoder 30 is blocked. As a result, the memory cell block is not selected while the plurality of selection signals YB0 to YBn for selecting the memory cell block 10 are blocked and redundancy of the defective memory cell is performed. The selection signal RYB0 corresponding to the sub bit line to which the defective memory cell is connected is selected among the plurality of selection signals RYB0 to RYBn output from the redundant predecoder 40 of FIG. The memory cell MC is repaired into the redundant memory cell RMC.

However, according to the semiconductor memory device as described above, even if a defect occurs in the memory cell (MC) connected to any one or more of the plurality of sub-bit line (SBLi1-SBLi4), in order to repair it, The entire memory cell block is repaired simultaneously to the plurality of redundant sub bit lines RSBLi1 to RSBLi4 of the redundant memory cell block. As such, when repaired simultaneously to the redundant sub-bit lines RSBLi0,, and RSBLi3, there is a high probability that another defect occurs among the redundant memory cells RMC of the redundant memory cell block replacing the memory cell block of the defective memory cell. high. In addition, since the memory cell block 10 is repaired to the entire redundant memory cell block 20, the redundancy efficiency is lowered.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to improve redundancy efficiency and selectively repair the redundant sub bit lines corresponding thereto according to the number of sub bit lines connected to the defective memory cell. The present invention provides a semiconductor memory device.

1 is a block diagram showing a schematic configuration of a semiconductor memory device having a conventional redundant free decoder;

2 is a block diagram showing the configuration of a conventional redundant free decoder;

3 is a circuit diagram showing a circuit of the redundant free decoder of FIG. 2;

4 is a block diagram showing a configuration of a redundant free decoder according to a preferred embodiment of the present invention;

5 is a circuit diagram showing a circuit of the redundant free decoder of FIG. 4;

FIG. 6 is a diagram illustrating fuse coding of an address information input unit of the redundant free decoder of FIG. 4; FIG.

* Explanation of symbols on the main parts of the drawings

40: redundant free decoder block 42: precharge part

44: Defective address input 46: Output

48: control unit 50: address information input unit

According to one aspect of the present invention for achieving the above object, through a plurality of sub-bit line pairs connected to the memory cells and a plurality of transfer transistors each gate is connected to the selection signal lines to which the selection signal is applied from outside Outputting a plurality of memory cell blocks including main bit lines connected to the plurality of sub bit line pairs, and a plurality of selection signals for selectively connecting one of the main bit lines of each of the memory cell blocks to a bit line; A main column decoder block having a plurality of column decoders and a plurality of memory cell blocks for repairing a defect in one or more of the plurality of memory cells respectively connected to the plurality of sub bit lines. Multiple with the same configuration Redundant free consisting of redundant memory cell blocks and a plurality of redundant free decoders corresponding to the plurality of redundant memory cell blocks to select a redundant memory cell block corresponding to the memory cell block containing the defective memory cell 10. A semiconductor memory device having a decoder block, wherein each redundant predecoder comprises: a conductive path charged with a power supply voltage or a ground voltage; A precharge unit for charging the conductive path to a predetermined voltage level in response to a control signal applied from the outside when a memory cell of the memory cell block is defective; When the memory cell of the memory cell block does not have a defect, the conductive path is connected to a second power terminal. When a defect occurs in the memory cell, a corresponding defective address is input to the second power terminal connected to the conductive path. A defective address input unit for blocking the; A control unit which receives a signal charged in a plurality of conductive paths corresponding to the plurality of redundant free decoders, and outputs a control signal for blocking a plurality of selection signals output from the main column decoder; An output unit for receiving a signal charged in the conductive path and outputting a selection signal for selecting a redundant memory cell block corresponding to the defective memory cell; An address for selecting a redundant sub bit line corresponding to one or more sub bit lines connected to a defective memory cell among the plurality of memory cell blocks by predetermined fuse decoding, and replacing the defective memory cell with a redundant memory cell It includes an address information input unit for receiving information.

In a preferred embodiment of the device, the address information input section has one end connected to the conductive path to individually select a redundant sub bit line corresponding to a sub bit line connected to the defective memory cell and connected to the address input means. A plurality of fuses connected to other terminals and selectively cut according to a predetermined fuse coding method; And an address input means for receiving control signals corresponding to minimum bits for selecting a plurality of redundant sub bit lines connected to redundant main bit lines of the redundant memory cell block.

In a preferred embodiment of the device, the address input means has a gate connected to a control terminal to which a control signal is applied from the outside and source-drain between the other terminal of the fuse Fi and the second power supply terminal among the plurality of fuses. An NMOS transistor connected with a channel; An inverter for receiving the control signal and outputting a signal having a reversed phase; A NMOS transistor having a gate connected to an output terminal of the inverter and a source-drain channel connected between the other terminal of the fuse FiB and the second power supply terminal; A NMOS transistor having a gate connected to a control terminal to which a control signal is applied from the outside and a source-drain channel connected between the other terminal of the fuse Fj and the second power supply terminal; An inverter for receiving the control signal and outputting a signal having a reversed phase; A gate is connected to an output terminal of the inverter and an NMOS transistor having a source-drain channel connected between the other terminal of the fuse FjB and the second power supply terminal.

By such a device, it is possible to implement a semiconductor memory device capable of improving redundancy efficiency and selectively repairing only memory cells of one sub-bit line having a defect.

Hereinafter, the semiconductor memory device according to the present invention will be described in detail with reference to FIGS. 4 to 6. Each redundant predecoder 40 of the novel semiconductor memory device of the present invention, with reference to FIG. 5, includes a conductive path L1 charged with a power supply voltage Vcc and a ground voltage Vss, and the memory cell block ( When a defect occurs in the memory cell MC of 10), the precharge unit 42 for charging the conductive path L1 to a predetermined voltage level in response to a control signal CSB applied from the outside, and When the memory cell MC of the memory cell block 10 is not defective, the conductive path L1 is connected to the second power supply terminal 2, and when the memory cell MC is defective, a corresponding defect is generated. A defective address input unit 44 which receives the addresses CAi0 to CAi3 and CABi0 to CABi3, and blocks the second power supply terminal 2 connected to the conductive path L1, and the plurality of redundant predecoder 40. Receives a signal charged in a plurality of conductive paths L1 corresponding to The controller 48 outputs a control signal RRDT for blocking the plurality of selection signals YB0 to YBn output from the in-column decoder 30, and a signal charged to the conductive path L1 is received. And an output unit 46 for outputting a selection signal RYBn for selecting a redundant memory cell block 20 corresponding to the defective memory cell MC, and a defect among the plurality of memory cell blocks 10. The redundant sub bit line RSBL corresponding to one or more sub bit lines SBL connected to the memory cell MC is selected by predetermined fuse decoding, and the defective memory cell MC is selected from the redundant memory cell RMC. ) Is composed of an address information input unit 50 for receiving address information RDi and RDBi for replacing with "

According to such an apparatus, when a defect occurs in the memory cell MC, when the defective memory cell MC is repaired as a redundant memory cell RMC, the sub bit line SBL connected to the defective memory cell MC is conventionally used. The redundant sub bit line RSBL corresponding to the defective memory cell may be selectively repaired instead of the entire sub bit line to which the and normal memory cells are connected. Therefore, not only the entire memory cell block 10 can be repaired to the redundant memory cell block 20 but also the redundancy efficiency can be improved.

In Figs. 4 to 6, the same reference numerals are given together for the components having the same functions as the components shown in Figs.

4 is a block diagram showing a configuration of a redundant free decoder according to a preferred embodiment of the present invention.

Referring to FIG. 4, when a defect occurs in the memory cell MC of the memory cell block 10, the precharge unit 42 determines the conductive path L1 in response to a control signal CSB applied from the outside. Charge to the voltage level of. The defect address input unit 44 connects the conductive path L1 to the second power supply terminal 2 when there is no defect in the memory cell MC of the memory cell block 10, and connects the memory cell MC to the memory cell MC. If a fault occurs, corresponding fault addresses CAi0 to CAi3 and CABi0 to CABi3 are inputted to block the second power supply terminal 2 connected to the conductive path L1. The controller 48 receives signals charged in the plurality of conductive paths L1 corresponding to the plurality of redundant free decoders 40, and outputs the plurality of selection signals output from the main column decoder 30 ( Output a control signal RRDT to block YB0-YBn). The output unit 46 receives a signal charged in the conductive path L1, and outputs a selection signal RYBn for selecting a redundant memory cell block 20 corresponding to the defective memory cell MC. The address information input unit 50 selects a redundant sub bit line RSBL corresponding to one or more sub bit lines SBL connected to the defective memory cell MC among the plurality of memory cell blocks 10. Selected by fuse decoding, and receives address information RDi and RDBi for replacing the defective memory cell MC with a redundant memory cell RMC.

5 is a circuit diagram showing a circuit of a redundant free decoder according to a preferred embodiment of the present invention.

In the defective address storage circuit of the redundant predecoder shown in FIG. 5, the redundant predecoder includes a first power supply terminal 1 to which a power supply voltage Vcc is applied and a second power supply terminal 2 to which a ground voltage Vss is applied. ). The precharge unit 42 includes a first fuse F1 connected between the first power supply terminal 1 and the first connection point N1, the first connection point N1, and the second power supply terminal 2. A first MOS transistor having a gate connected to the resistor R1 connected to the first connection point N1 and a source-drain channel connected between the first power supply terminal 1 and the second connection point N2. Q1), an inverter I1 for inverting and outputting a phase of the signal charged at the first connection point N1, and a gate is connected to an output terminal of the inverter I1, and the first connection point N1 and the first connection point are connected to each other. A source-drain channel is connected in series between the second MOS transistor Q2 having a source-drain channel connected between the two power supply terminals 2, and the second connection point N2 and the second power supply terminal 2. Gates are respectively connected to control signals CSB applied from the outside; The third and fourth MOS transistors Q3 and Q4 have a conductive path L1 connected between the source and drain channels.

The defective address input unit 44 is connected to the plurality of first fuse groups F2, F4, F6, and F8 having one end connected to the conductive path L1, and to the memory cell MC of the memory cell block 10. If a fault occurs, a gate is connected to each terminal to which the corresponding fault addresses CAi0 to CAi3 and CABi0 to CABi3 are applied, and the other terminals of the first fuse groups F2, F4, F6, and F8 and the A plurality of MOS transistors Q5, Q7, Q9, and Q11 each having a source-drain channel connected between the second power supply terminal 2, and a plurality of second fuse groups having one end connected to the conductive path L1. (F3, F5, F7, F9), a plurality of inverters I2, I3, I4, and I5 inverting and outputting phases of the defect addresses CAi0 to CAi3 and CABi0 to CABi3, and the plurality of inverters A gate is connected to each output terminal of (I2, I3, I4, and I5), the other terminal of the second fuse group F3, F5, F7, and F9 and the second power supply terminal 2 The source-drain channel made up of a plurality of MOS transistors each connected to (Q6, Q8, Q10, Q12).

The output unit 46 for outputting a signal for selecting any one of the redundant memory cell blocks shown in FIG. 1 receives a signal charged in the conductive path L1 and receives a plurality of inverters I6 and I7. And a NOR gate G1 having an input terminal connected to the signal output through I8) and the third connection point N3, respectively. The controller 48 receives signals in which the phases of the signals charged in the plurality of conductive paths L1 corresponding to the plurality of redundant predecoder 40 are inverted and are output from the main column decoder 30 in response thereto. The NAND gate G2 outputs a control signal RRDT for blocking the plurality of selection signals YB0 to YBn. In addition, one end of the address information input unit 50 may be connected to the conductive path L1 and the other terminal may be connected to the address input unit 50b to selectively cut the fuses according to a predetermined fuse coding method. , FiB, Fj, FjB) and address input means 50b.

The address input unit 50b has a gate connected to the control terminal 8 to which the control signal RDi is applied from the outside, and the other of the fuse Fi among the plurality of fuses Fi, FiB, Fj, and FjB. An NMOS transistor Q11 having a source-drain channel connected between the terminal and the second power supply terminal 2; An inverter I9 which receives the control signal RDi and outputs a signal having a reversed phase; A NMOS transistor Q12 having a gate connected to an output terminal of the inverter I9 and a source-drain channel connected between the other terminal of the fuse FiB and the second power supply terminal 2; A NMOS transistor Q13 having a gate connected to a control terminal 9 to which a control signal RDBi is applied from the outside and a source-drain channel connected between the other terminal of the fuse Fj and the second power supply terminal 2; An inverter (I10) for receiving the control signal (RDBi) and outputting a signal having a reversed phase; A gate is connected to an output terminal of the inverter I10, and an NMOS transistor Q14 is connected to a source-drain channel between the other terminal of the fuse FjB and the second power supply terminal 2.

In addition, coding for cutting a plurality of fuses Fi, FiB, FBi, and FBiB for selecting a sub bit line connected to a defective memory cell is shown in FIG. According to the coding diagram illustrated in FIG. 6, the sub bit lines connected to the defective memory cell may be individually selected and repaired.

A semiconductor memory device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

The conductive path L1 of the redundant predecoder 40 illustrated in FIG. 5 has the first and second fuse groups F2, F4, F6, F8, F3, F5, F7, and F9 when no defect occurs in the memory cell. To maintain the low level. For convenience of description, when a defect occurs in the memory cell MC of the memory cell block 10 of the semiconductor memory device shown in FIG. 1, the defect is replaced with the redundant memory cell RMC of the redundant memory cell block 20. Let's do it. As described above, when the defective memory cell MC is repaired to the redundant sub bit line RSBL corresponding to the connected sub bit line SBL, the first fuse F1 of the precharge unit 42 shown in FIG. ) Is cut by applying a predetermined signal from the outside. When the first fuse F1 is cut, a high level is applied to the gate of the second MOS transistor Q2 through the first inverter I1 to conduct a channel.

In addition, a second power supply terminal 2 having a low level is connected to the gate of the first MOS transistor Q1 through the second MOS transistor Q2 to conduct a channel. At this time, when the control signal CSB applied from the outside is applied at a low level, the channel of the third MOS transistor Q3 is turned on and the power supply voltage Vcc transferred through the channel of the first MOS transistor Q1 is It is charged to the conductive path L1. The plurality of MOS transistors Q5, Q7, Q9 and Q11 and the plurality of MOS transistors Q6, which receive the defect address signals CAi0 to CAi3 and CABi0 to CABi3 corresponding to the defective memory cell MC, respectively. The fuse corresponding to the address of the defective memory cell MC is cut out of the first and second fuse groups F2, F4, F6, F8, F3, F5, F7, and F9 connected to Q8, Q10, and Q12, respectively. .

Thereafter, when the defective address signals CAi0 to CAi3 and CABi0 to CABi3 are input, the conductive path L1 charged by the precharge unit 42 to the power supply voltage Vcc is maintained at the power supply voltage Vcc. . By the above-described series of operations, RYB0 is selected among the selection signals RYB0 to RYBn output from the redundant free decoder of FIG. 1 to replace the defective memory cell with a redundant memory cell block. However, the above-described series of operations are the same as the conventional redundant free decoder, but may selectively repair the memory cell through the address information input unit 50. A plurality of fuses Fi, FiB, FBi, and FBiB of the address information input unit 50 shown in FIG. 5 are cut according to the coding diagram shown in FIG. For example, assume that a defect occurs in the memory cell MC connected to the sub bit line SBLi1 of the memory cell block 10 shown in FIG. 1.

In this case, FiB and FBiB of the plurality of fuses Fi, FiB, FBi, and FBiB of the address information input unit 50 are cut according to the diagram shown in FIG. 6. In addition, low-level control signals RDi and RDBi are applied to gates of the NMOS transistors Q11 and Q13 of the address input unit 50b to maintain the power supply voltage Vcc charged in the conductive path L1. It is applied from the outside. Accordingly, the channel of the NMOS transistors Q11 and Q13 is not conducting, so that the power supply voltage Vcc charged to the conductive path L1 is maintained. The signal RYBn for selecting the redundant memory cell block 20 corresponding to the defective memory cell is output at a high level through the output unit 46 receiving the signal charged in the conductive path L1. .

In addition, the controller 48, which receives a plurality of signals in which the phase of the signal charged in the conductive path L1 is inverted, also outputs a high level signal together with the output unit 46. The operation of the decoder 30 is blocked. As a result, the memory cell block is not selected while the plurality of selection signals YB0 to YBn for selecting the memory cell block 10 are blocked and redundancy of the defective memory cell is performed. A plurality of selections connected to respective gates of the plurality of transfer transistors shown in FIG. 1 through external coding using control signals RDi and RDBi applied to the address input means 50b of the address information input unit 50. Only defective memory cells applied to the signal lines may be repaired.

As described above, when a defect occurs in a memory cell, when the defective memory cell is repaired as a redundant memory cell, as in the prior art, the entire sub bit line connected to the defective memory cell and the sub bit line to which the normal memory cell are connected are not repaired. Only redundant sub bit lines corresponding to the generated memory cells can be repaired selectively. Therefore, not only the entire memory cell block can be repaired as a redundant cell block but also the redundancy efficiency can be improved.

Claims (3)

A plurality of sub-bit line pairs SBLi0 to SBLi3 and SBLBi0 to SBLBi3 to which memory cells MC are connected, and a plurality of gates connected to gates to select signal lines SLi0 to SLi3 and SLBi0 to SLBi3 to which a selection signal is applied from the outside. A plurality of main bit lines MBL0 connected to the plurality of sub bit line pairs SBLi0 to SBLi3, SBLBi0 to SBLBi3 through transfer transistors T1, T2, T3, T4, TB1, TB2, TB3 and TB4. Plurality of selection signals YB0 − for selectively connecting one of the plurality of memory cell blocks 10 and one of the main bit lines MBL0 of each of the memory cell blocks 14 to the bit lines B / L. One or more memory cells of a main column decoder block 30 having a plurality of column decoders outputting YBn) and a plurality of memory cells MC connected to the plurality of sub bit lines SBLi0 to SBLi3, respectively. If (MC) is defective, repair it To correspond to the plurality of redundant memory cell blocks 20 having the same configuration as the plurality of memory cell blocks 10 and the memory cell block 10 including the defective memory cell MC In the semiconductor memory device having a redundant pre-decoder block 40 composed of a plurality of redundant pre-decoder 40 corresponding to the plurality of redundant memory cell blocks 20 to select a redundant memory cell block 20. , Each redundant free decoder 40, A conductive path L1 charged with a power supply voltage Vcc or a ground voltage Vss; A second power supply terminal 2 to which a ground power supply Vss is applied; When a defect occurs in the memory cell MC of the memory cell block 10, a precharge unit for charging the conductive path L1 to a predetermined voltage level in response to a control signal CSB applied from the outside ( 42); When the memory cell MC of the memory cell block 10 is not defective, the conductive path L1 is connected to the second power terminal 2, and when the memory cell MC is defective, the corresponding conductive path L1 is connected thereto. A defect address input unit 44 which receives the defect addresses CAi0 to CAi3 and CABi0 to CABi3 and blocks the second power supply terminal 2 connected to the conductive path L1; Blocking the plurality of selection signals YB0-YBn output from the main column decoder 30 by receiving signals charged in the plurality of conductive paths L1 corresponding to the plurality of redundant free decoders 40. A control unit 48 for outputting a control signal RRDT for the control unit; An output unit 46 which receives a signal charged in the conductive path L1 and outputs a selection signal RYBn for selecting a redundant memory cell block 20 corresponding to the defective memory cell MC; The redundant sub bit line RSBL corresponding to one or more sub bit lines SBL connected to the defective memory cell MC among the plurality of memory cell blocks 10 is selected by predetermined fuse decoding, And an address information input unit (50) for receiving address information (RDi, RDBi) for replacing the defective memory cell (MC) with a redundant memory cell (RMC). The conductive path (100) of claim 1, wherein the address information input unit (50) is configured to individually select a redundant sub bit line (RSBL) corresponding to a sub bit line (SBL) connected to the defective memory cell (MC). A plurality of fuses (Fi, FiB, Fj, FjB) having one end connected to L1) and another terminal connected to the address input means (50b) and selectively cut according to a predetermined fuse coding method; Address for receiving control signals RDi and RDBi corresponding to minimum bits for selecting a plurality of redundant sub bit lines RSBLi0 to RSBLi3 connected to the redundant main bit line RMBL0 of the redundant memory cell block 20 A semiconductor memory device characterized by comprising an input means (50b). 3. The address input unit 50b of claim 2, wherein a gate is connected to a control terminal 8 to which a control signal RDi is applied from the outside, and among the plurality of fuses Fi, FiB, Fj, and FjB. An NMOS transistor Q11 having a source-drain channel connected between the other terminal of the fuse Fi and the second power supply terminal 2; An inverter I9 which receives the control signal RDi and outputs a signal having a reversed phase; A NMOS transistor Q12 having a gate connected to an output terminal of the inverter I9 and having a source-drain channel connected between the other terminal of the fuse FiB and the second power supply terminal 2; A NMOS transistor Q13 having a gate connected to a control terminal 9 to which a control signal RDBi is applied from the outside and a source-drain channel connected between the other terminal of the fuse Fj and the second power supply terminal 2; An inverter (I10) for receiving the control signal (RDBi) and outputting a signal having a reversed phase; And a NMOS transistor Q14 having a gate connected to an output terminal of the inverter I10 and a source-drain channel connected between the other terminal of the fuse FjB and the second power supply terminal 2. .