KR100761400B1 - Row redundancy circuit of semiconductor memory device - Google Patents

Abstract

According to an aspect of the invention, the first cell block and the second cell block; A plurality of first redundant word lines corresponding to the first cell block; A plurality of second redundant word lines corresponding to the second cell blocks; A block selection circuit unit for selecting the first redundant word line or the second redundant word line for repair of a word line of the first cell block in response to a block address signal and a control signal; And a fuse box for outputting a low redundancy signal and generating the control signal by programming an address of a cell failed by fuse cutting. The block selection circuit unit is configured to select a pair of block signals to receive the control signal and the block address. part; An adder configured to receive a low redundancy signal output from the fuse box and logically sum the low redundancy signal in response to a word line activation signal; A block designation unit for designating a cell block for receiving and repairing a block address signal; A repair word line activation unit configured to receive the word line activation signal and the output of the pair block selection unit and output a repair word line activation signal; And a normal word line activation unit configured to receive an output of the summation unit and an output of the block designation unit and output a normal word line activation signal. As such, the low redundancy circuit of the present invention uses the redundant word line of the neighboring cell block from the fuse box when the redundant word line corresponding to the cell block is used and the redundant word line is no longer available. Generates a control signal for determining a and selects the cell block and the redundant word line in the block selection circuit section in response to the control signal.

Redundant word line, self-pair signal, adder, block branch, fuse box.

Description

Low redundancy circuit of semiconductor memory device             

1 is a block diagram showing the concept of a low redundancy of the prior art;

2 is a circuit diagram showing a fuse box of the flexible low redundant scheme of the prior art;

3 is a circuit diagram showing a conventional block selection circuit;

4 is a circuit diagram showing a block selection scheme of a low redundancy circuit of the present invention;

5 is a circuit diagram showing a fuse box circuit of the present invention.

Explanation of symbols on the main parts of the drawings

400: fair block selector 410: adder

420: block branch 430: repair line activation unit

440: normal word line activation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a low redundancy circuit having improved repair efficiency by enabling the use of redundant word lines of neighboring cell blocks.

In general, since the cost of a semiconductor memory device is greatly influenced by its yield, a redundant memory cell is basically added to the normal memory cell in order to improve this yield. Thus, if a few defective memory cells are generated, a method (repair) of replacing them with redundant memory cells has been used. In high-density and large-capacity memory devices larger than 256Mb, as the size of the chip grows, the bridge phenomenon generated during the manufacturing process creates an undesired current path in the standby state of the memory device, leading to power consumption and narrowing the line width. Due to the lack of flat margin (Margin) caused by the defect is very frequent. Thus, various attempts have been made to increase the efficiency of the repair.

1 is a block diagram illustrating the concept of low redundancy in the prior art.

Referring to FIG. 1, a conventional low redundancy scheme includes a plurality of cell blocks 100 including M rows and N columns and having a plurality of redundant word lines up and down, and A block selection / word line enable block 110 for selecting the cell block and activating a word line, and a plurality of fuse boxes 120 for driving the redundancy word line by programming an address of a failed cell. It is provided.

When a fail occurs in a word line to drive the redundant word line, the fuse corresponding to the address of the failed word line in the fuse box 120 is cut and replaced with the redundant word line.

However, since redundant word lines must be able to replace failed word lines, the number of redundant word lines has a fuse box 120 so as to find the address of the failed word lines. A fuse box has as many fuses as each cell. Therefore, if the number of redundant word lines is large, the number of fuse boxes increases.

The repair scheme that compensates for these drawbacks is the flexible row redundant scheme.

Figure 2 is a circuit diagram showing a fuse box of the flexible low redundant scheme of the prior art.

Referring to FIG. 2, a low redundant fuse box according to the related art includes a precharge unit 200 precharging a node 1, a plurality of first fuses 210 connected in parallel to the node 1, and a plurality of first fuses 210 connected to the node 1 in parallel. A plurality of first NMOS transistors 220 having an address signal XA input to a gate terminal and a source-drain path formed between the first fuse 210 and a ground terminal, and the node 1 and the strobe signal stb. ) Is input to the gate terminal, and a plurality of second NMOS transistors 230 connected in series between the ground terminal and the second fuse 240 and between the source terminal and the output node of the second NMOS transistor 230. And a second fuse 240 formed in the second fuse 240.

Referring to the operation, first, the precharge circuit precharges the node 1 in a state where the word line is not enabled. If the first fuse is not broken while the word line is enabled, the logic high value of the node 1 precharged through the first NMOS transistor 220 is changed to a logic low value. If the first fuse is disconnected while the word line is enabled, the path flowing to the ground terminal through the first NMOS transistor 220 is blocked, so that the logic high value precharging the node 1 is maintained. Then, when the strobe signal stb is logic high, the second NMOS transistor 230 is turned on. When the output of the desired fuse is selected by cutting off the second fuse, a logic low value is output through the second NMOS transistor 230 and the selected fuse.

3 is a circuit diagram showing a conventional block selection circuit.

Referring to FIG. 3, a word is received by receiving a noah gate unit 300 that receives a low redundancy signal xredt <0: 5>, which is the final output signal of the fuse box, and an output signal of the noah gate unit 300. The NAND gate 310 in response to the line activation signal wlstd, the first inverter 320 that receives the output of the NAND gate 310, and the NAND gate 330 that receives the block addresses blkA and blkB. And a second inverter 340 that receives the NAND gate 330 and a NAND gate that receives the outputs of the first and second inverters 320 and 340 and outputs a normal word line activation signal blknb. 350 and a delay / inversion unit 360 for delaying and inverting the word line activation signal wlstd to output a repair word line activation signal blkrb.

Referring to the operation, when the word line activation signal wlstd is activated at a logic high and the low redundancy signals xredt <0: 5> are all at a logic low, the output of the NOR gate 300 goes to a logic high. To make the output of the NAND gate 310 logic low. Then, when the block addresses blkA and blkB are selected and enabled to be logic high, the output of the NAND gate 330 is made to be logic low, and is inverted through the second inverter 340 so that the two gates of the NAND gate 350 are inverted. Since the inputs are all logic high, the normal word line activation signal blknb is activated to logic low. In addition, the repair word line activation signal blkrb is activated to a logic low in response to the word line activation signal wlstd.

The normal word line activation signal blknb and the repair word line activation signal blkrb are signals indicating which cell block is activated among a plurality of cell blocks. When the normal word line is enabled, the normal word line activation signal blknb is enabled in a logic row to enable one of the plurality of word lines in combination with the input row address. In the case of a repair, one of the low redundancy signals xredt <0: 5> is enabled by logic high to disable the normal word line enable signal blknb, and instead, the repair word line enable signal blkrb Enabled to logic low. This enables the repair word line selected by the redundancy signal xredt <0: 5> in the cell block.                         

The flexible row redundant scheme operating as described above may repair up to 2K word lines per cell block. However, if a word line fails in more than 2K in one cell block, the number of repair word lines is limited to 2K, which causes a problem that repair is no longer possible. This has the problem that repair is impossible even if there are more than 2K fuse boxes or other repair word lines remaining.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a low redundancy circuit that improves repair efficiency by sharing repair word lines of adjacent cell blocks.

According to an aspect of the present invention for achieving the above object, a first cell block and a second cell block; A plurality of first redundant word lines corresponding to the first cell block; A plurality of second redundant word lines corresponding to the second cell blocks; A block selection circuit unit for selecting the first redundant word line or the second redundant word line for repair of a word line of the first cell block in response to a block address signal and a control signal; And a fuse box for outputting a low redundancy signal and generating the control signal by programming an address of a cell failed by fuse cutting. The block selection circuit unit is configured to select a pair of block signals to receive the control signal and the block address. part; An adder configured to receive a low redundancy signal output from the fuse box and logically sum the low redundancy signal in response to a word line activation signal; A block designation unit for designating a cell block for receiving and repairing a block address signal; A repair word line activation unit configured to receive the word line activation signal and the output of the pair block selection unit and output a repair word line activation signal; And a normal word line activation unit configured to receive an output of the summation unit and an output of the block designation unit and output a normal word line activation signal.

As such, the low redundancy circuit of the present invention uses the redundant word line of the neighboring cell block from the fuse box when the redundant word line corresponding to the cell block is used and the redundant word line is no longer available. A control signal for determining is determined, and the block selection circuit section selects the cell block and the redundant word line in response to the control signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a circuit diagram showing a block selection scheme of a low redundancy circuit of the present invention.

Referring to FIG. 4, the block selection scheme according to the present invention includes a pair block selection unit 400 that receives a self_pairb signal and a block address for determining whether to select a neighboring cell block, and a low redundancy signal. xredt <0: 5>), the summation unit 410 for ORing the low redundancy signal in response to the word line activation signal wlstd, and the first and second block addresses blkA and blkB are received and repaired. A repair block for designating a cell block for receiving a block block 420, a word line activation signal wlstd, and an output of the pair block selector 400, and a repair word for outputting a repair word line activation signal blkrb. The word line activation unit 430 and the normal word line activation unit 440 receiving the output of the summing unit 410 and the output of the block designation unit 420 and outputting a normal word line activation signal blknb are provided. Equipped.

In detail, the fair block selector 400 is controlled by the NMOS transistor by the first block selection address bxab_i, the PMOS transistor is controlled by the second block selection address bxab_j, and receives the self-pair signal self_pairb. The first transmission gate 401 and the PMOS transistor are controlled by the first block selection address bxab_i, the NMOS transistor is controlled by the second block selection address bxab_j, and receives the self-pair signal self_pairb. A second transmission gate 402 inverted and transmitted, and a noah gate 403 for receiving the output of the first and second transmission gates and a block address blkB for selecting its own block.

When repairing a fail of a word line occurring in a cell, the pair block selector 400 is required to use redundant word lines of neighboring cell blocks as well as its own cell block. In this case, a group of common address bits among the block addresses of a cell block and a neighboring cell block is called a second block address blkB, and a group of different address bits is called a first block address blkA. Once the normal word line is enabled, the normal word line activation signal blknb is enabled to a logic low by receiving a corresponding block address in the same way as a conventional circuit.

However, if the address of the redundant word line is input, it is determined whether the fuse is cut to use the redundant word line of its cell block or the redundant word line to cut the fuse to use the redundant word line of the neighboring cell block. Should know. The signal indicating this is the self-pair signal self_pairb. This is a logic high when the redundant word line of the cell block corresponding to the currently input block address is used and a logic low when the redundant word line of the neighboring cell block is used. The repair word line enable signal blkrb of a desired cell block (its cell block or a neighboring cell block) is enabled to a logic low by using the self-pair signal self_pairb. In order to enable the repair word line enable signal blkrb, as shown in FIG. 4, the output of the pair block selector 400 must be enabled as logic high. However, the pair block select which is the output of the pair block selector 400 is selected. The signal flex_red operates as follows.

When the row address is input, the first and second transmission gates 401 and 402 which pass from the self-pair signal self_pairb to the pair block selection signal flex_red operate to select their cell blocks. When the second transmission gate 402 is opened and the neighboring cell block is selected, the first transmission gate 401 is opened. The second transmission gate 402 inverts the self-pair signal self_pairb and sends the signal to the noah gate 403, and the first transmission gate 401 transmits the same. That is, when the self-pair signal self_pairb is logic, the outputs of the first and second transmission gates 401 and 402 which are the inputs of the NOA gate 403 become logic lows in their cell blocks and are adjacent to each other. Logic high in the cell block. In addition, if the self-pair signal self_pairb is logic low, the outputs of the first and second transmission gates 401 and 402 become logic high in their cell blocks and logic low in neighboring cell blocks. Accordingly, the repair word line activation signal blkrb is enabled in its cell block when the self-pair signal self_pairb is logical high and in the neighboring cell block when the self-pair signal self_pairb is logical low. Is enabled. After that, one of the redundant word lines is enabled by replacing the word lines by the low redundancy signals xredt <0: 5>, which is the same as the conventional circuit.

When the address of the redundant word line is input, the normal word line activation signal blknb is disabled in any cell block because one of the low redundancy signals xredt <0: 5> is enabled.

5 is a circuit diagram illustrating a fuse box circuit of the present invention.

Referring to FIG. 5, the fuse box of the present invention further includes a fuse (Fuse_SP) for making the self-pair signal (self_pairb) in the conventional fuse box shown in FIG.

Specifically, the fuse box is a precharge unit for precharging the node 1, a plurality of first fuses (Fuse_1) connected in parallel to the node 1, and the address signal (XA) is input to the gate terminal and the source- A plurality of first MOS transistors 520 having a drain path formed between the first fuse and the ground terminal, and a second fuse Fuse_2 connected to each output terminal of a low redundancy signal fuse and a self-pair flag signal self_pair_flag. Fuse_SP) and a plurality of second MOS transistors 530 which are inputted with the node 1 signal and the strobe signal stb as a gate terminal and connected in series between a ground terminal and the second fuse.                     

By cutting the fuse Fuse_SP or not, it is determined whether to use the redundant word line of the cell block or the redundant word line of the neighboring cell block. If the cut of the fuse (Fuse_SP) is to select a neighboring cell block, the self-pair flag (self_pair_flag), which is an output of the fuse (SP), has a logic low state in its cell block and a neighboring cell block. It will have a logic high state. Since the self-pair signal self_pairb of FIG. 4 has the opposite polarity, the self-pair flag self_pair_flag is inverted to generate the self-pair signal self_pairb. On the contrary, if the cut of the fuse (Fuse_SP) is to use the redundant word line of its cell block, the self-pair signal (self_pairb) is generated through buffering the self_pair_flag signal of FIG. 5 as it is.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can share the redundant word lines of neighboring cell blocks, thereby increasing the repair efficiency twice as much as the conventional low repair scheme in one cell block.

Claims (4)

delete A first cell block and a second cell block; A plurality of first redundant word lines corresponding to the first cell block; A plurality of second redundant word lines corresponding to the second cell blocks; A block selection circuit unit for selecting the first redundant word line or the second redundant word line for repair of a word line of the first cell block in response to a block address signal and a control signal; And And a fuse box for programming an address of a cell failed by fuse cutting to output a low redundancy signal and to generate the control signal. The block selection circuit unit, A pair block selecting unit receiving the control signal and the block address; An adder configured to receive a low redundancy signal output from the fuse box and logically sum the low redundancy signal in response to a word line activation signal; A block designation unit for designating a cell block for receiving and repairing the block address signal; A repair word line activation unit configured to receive the word line activation signal and the output of the pair block selection unit and output a repair word line activation signal; And And a normal word line activation unit configured to receive an output of the summation unit and an output of the block designation unit and output a normal word line activation signal. delete delete

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