KR970003214A - Semiconductor memory device with low redundancy - Google Patents

Semiconductor memory device with low redundancy Download PDF

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Publication number
KR970003214A
KR970003214A KR1019950015388A KR19950015388A KR970003214A KR 970003214 A KR970003214 A KR 970003214A KR 1019950015388 A KR1019950015388 A KR 1019950015388A KR 19950015388 A KR19950015388 A KR 19950015388A KR 970003214 A KR970003214 A KR 970003214A
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KR
South Korea
Prior art keywords
redundancy
signal
word line
memory block
group
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KR1019950015388A
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Korean (ko)
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KR0149589B1 (en
Inventor
최명찬
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김광호
삼성전자 주식회사
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Priority to KR1019950015388A priority Critical patent/KR0149589B1/en
Publication of KR970003214A publication Critical patent/KR970003214A/en
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Publication of KR0149589B1 publication Critical patent/KR0149589B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

1.청구범위에 기재된 발명이 속하는 기술 분야1. Technical field to which the invention described in the claims belongs

본 발명은 반도체 메모리장치의 로우리던던시에 관한 것이다.The present invention relates to a low redundancy of a semiconductor memory device.

2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve

종래에는 블럭단위로 리던던시가 이루어져 리던던시효율이 저하되거나 혹은 많은 수의 휴즈박스를 필요로 하여 칩면적이커지는 단점이 있었다.In the related art, redundancy is performed on a block basis, and redundancy efficiency is reduced, or a large number of fuse boxes are required, resulting in a large chip area.

3.발명의 해결방법의 요지3. Summary of the solution of the invention

본 발명에 따른 로우리던던시에 있어서 스페어 메모리블럭을 가지는 다수개의 메모리블럭들과, 리던던시 선택신호와 상기스페어 메모리블럭내의 스페어 워드라인들을 구동시키는 스페어 워드라인 제어신호를 발생하는 다수개의 휴즈박스들과,상기 메모리블럭내의 노멀워드라인들을 제어하는 워드라인 구동신호를 발생하는 다수개의 워드라인 구동회로들을 가지는반도체 메모리장치에 있어서 상기 메모리블럭의 선택에 관련된 신호와 적어도 둘이상의 상리 리던던시 선택신호를 입력하여 상기 워드라인 구동신호의 상태를 제어하는 복수개의 리던던시 활성화신호를 발생하는 수단을 구비한다.In the low redundancy according to the present invention, a plurality of memory blocks having a spare memory block, a plurality of fuse boxes for generating a redundancy selection signal and a spare word line control signal for driving spare word lines in the spare memory block; In a semiconductor memory device having a plurality of word line driving circuits for generating a word line driving signal for controlling normal word lines in the memory block, the semiconductor memory device is configured to input a signal related to the selection of the memory block and at least two different redundancy selection signals. Means for generating a plurality of redundancy enable signals for controlling the state of the word line drive signal.

4.발명의 중요한 용도4. Important uses of the invention

이에 따라 리던던시 효율이 향상되고 칩면적이 줄어든 반도체 메모리 장치가 구현된다.As a result, a semiconductor memory device having improved redundancy efficiency and reduced chip area is realized.

Description

로우리던던시기능을 가지는 반도체 메모리장치Semiconductor memory device with low redundancy

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 리던던시방식을 사용하는 반도체 메모리장치의 개략적인 구성을 보여주는 도면.5 is a diagram showing a schematic configuration of a semiconductor memory device using the redundancy method according to the present invention.

Claims (2)

스페어 메모리블럭을 가지는 다수개의 메모리블럭들과, 로우 어드레스 디코딩신호에 응답하여 리던던시 선택신호와 상기 스페어 메모리블럭내의 스페어 워드라인들을 구동시키는 스페어 워드라인 제어신호를 발생하는 다수개의휴즈박사들과, 상기 메모리블럭내의 노멀 워드라인들을 제어하는 워드라인 구동신호를 발생하는 다수개의 워드라인 구동회로들을 가지는 반도체 메모리장치에 있어서, 상기 메모리블럭의 선택에 관련된 신호와 적어도 둘이상의 상기 리던던시선택신호를 입력하여 상기 워드라인 구동신호의 상태를 제어하는 복수개의 리던던시 활성화신호를 발생하는 수단을 구비함을 특징으로 하는 반도체 메모리장치.A plurality of memory blocks having a spare memory block, a plurality of fuse doctors generating a redundancy selection signal in response to a row address decoding signal and a spare word line control signal for driving spare word lines in the spare memory block; A semiconductor memory device having a plurality of word line driving circuits for generating a word line driving signal for controlling normal word lines in a memory block, the semiconductor memory device comprising: receiving a signal related to selection of the memory block and at least two or more redundancy selection signals; And means for generating a plurality of redundancy enable signals for controlling the state of the word line drive signal. 제1항에 있어서 상기 수단이 상기 메모리 블럭의 선택에 관련된 상기 신호에 제1논리 상태를 공통으로 입력하는 제1군의 논리게이트들과, 상기 신호의 제2논리상태를 입력하는 제2군의 논리게이트들과, 상기 제1군의 논리게이트들의 출력을 입력하여 제1리던던시 활성화 신호를 발생하는 논리게이트와, 상기 제2군의 논리게이트들의 출력을 입력하여제2리던던시 활성화신호를 발생하는 논리게이트들을 구비하며 상기 제1군 및 제2군의 논리게이트들의 각각이 서로 다른상기 휴즈박스들로부터 발생된 상기 리던던시 선택신호를 각각 입력함을 특징으로 하는 반도체 메모리장치.2. The first group of logic gates according to claim 1, wherein the means inputs a first group of logic gates for commonly inputting a first logical state to the signal related to the selection of the memory block, and a second group for inputting a second logical state of the signal. Logic gates, a logic gate for inputting an output of the first group of logic gates to generate a first redundancy activation signal, and a logic for inputting an output of the second group of logic gates to generate a second redundancy enable signal And a redundancy select signal generated from the fuse boxes, the gates having logic gates in the first group and the second group, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950015388A 1995-06-12 1995-06-12 Semiconductor memory device having low redundancy KR0149589B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950015388A KR0149589B1 (en) 1995-06-12 1995-06-12 Semiconductor memory device having low redundancy

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Application Number Priority Date Filing Date Title
KR1019950015388A KR0149589B1 (en) 1995-06-12 1995-06-12 Semiconductor memory device having low redundancy

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KR970003214A true KR970003214A (en) 1997-01-28
KR0149589B1 KR0149589B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100761400B1 (en) * 2000-07-31 2007-09-27 주식회사 하이닉스반도체 Row redundancy circuit of semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100761400B1 (en) * 2000-07-31 2007-09-27 주식회사 하이닉스반도체 Row redundancy circuit of semiconductor memory device

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Publication number Publication date
KR0149589B1 (en) 1998-12-01

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