KR0172352B1 - Column redundancy control circuit of semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to column redundancy of a semiconductor memory device.

2. The technical problem the invention is trying to solve:

The present invention provides a column redundancy control circuit in a multi-bank structure that reduces the chip size increase due to density by implementing a new column redundancy constituting a plurality of banks consisting of groups of a plurality of memory arrays. .

3. Summary of the Solution of the Invention:

The present invention relates to a plurality of unit cell arrays, a plurality of sense amplifier blocks arranged between the unit cell arrays arranged in a column direction, and a plurality of partitions arranged between the unit cell arrays arranged in a row direction. Wordline drivers, a plurality of divided groups including a plurality of unit cell arrays, a plurality of banks arranged in a column direction, and one for selecting the bank and selecting a word line of a unit cell array belonging to the selected bank A semiconductor memory device having a low decoder and a column decoder for selecting a column corresponding to a memory 연결된 connected to the word line, the semiconductor memory device comprising: a column redundancy circuit for controlling column repair of the plurality of banks.

4 Important uses of the invention:

The present invention is suitably used for a semiconductor memory device.

Description

Column Redundancy Control Circuit of Semiconductor Memory Device

1 is an overall configuration diagram of a column redundancy apparatus according to the present invention.

2 is a block diagram showing the configuration of column redundancy according to the present invention.

3 is a block diagram of an embodiment according to the present invention having independent repair means for each column decoder.

4 is a specific circuit diagram of a fuse box means according to the present invention.

5 is a detailed circuit diagram of a circuit for driving a redundant global column selection line according to the present invention.

6 is a detailed circuit diagram of a redundant global column select line driver according to the present invention.

7 is a detailed circuit diagram of a circuit for implementing and disabling a normal global column selection line according to the present invention.

The present invention relates to a semiconductor memory device, and more particularly, to a column redundancy control circuit.

In general, in a semiconductor memory device, when a defect occurs in a normal memory cell, the normal cell is decoded by decoding an address signal corresponding thereto and a redundancy cell. There is a redundancy device that compensates for the deficiency of the redundancy device, and the redundancy cell array in which the redundancy cells are arranged is disposed around the normal cell array, and it is common knowledge that decoders necessary for address signal decoding and redundancy cell selection are separately embedded. . In the prior art, a plurality of normal arrays having a plurality of memory cells are arranged in a row direction and a plurality of redundant arrays having a plurality of redundant cells for replacing defects of the normal cell array are provided in a plurality of rows and at least one column direction. An array of memory cells arranged, a plurality of row decoders provided for each of the normal row blocks so that the normal arrays and the redundant cell arrays arranged in the same row are driven in a unit row block, and the normal cells arranged in the same column A plurality of normal column decoders corresponding to each normal column block so that arrays can be driven by a unit normal column block, and corresponding redundant column blocks so that the redundant cell arrays arranged in the same column can be driven by a unit redundant column block To obtain at least one column decoder A semiconductor memory device comprising: a block selection circuit for outputting a block selection signal for selecting one of the row blocks in response to an address signal specifying selection of the row block, and an address of a normal block in which a defect has occurred; A fuse circuit having a fuse for storing and detecting a column address in response to the block selection signal and outputting a redundant detection signal when it matches the address signal stored therein; and a redundant column decoder in response to the redundant detection signal Redundant selection circuit for outputting a redundant selection signal for driving a; and a normal control circuit for disabling the normal column decoder in response to the redundant detection signal, the redundant cell array corresponding to a normal array in which both rows and columns are selected Repair is done by substituting for A column redundancy that allows. However, there is a problem that it is very difficult to overcome the disadvantage of increasing the chip size in the conventional technology in the large memory due to the ever increasing high integration.

Accordingly, an object of the present invention is to implement a new column redundancy in a configuration of a plurality of banks consisting of groups of a plurality of memory arrays, thereby controlling column redundancy in a multi-bank structure that reduces chip size due to an increase in density. In providing a circuit.

According to the technical spirit of the present invention for achieving the above objects, a plurality of unit cell arrays, a plurality of sense amplifier blocks disposed between the unit cell arrays arranged in a column direction, and arranged in a row direction A plurality of divided word line drivers disposed between the unit cell arrays, a plurality of divided groups including a plurality of unit cell arrays, a plurality of banks arranged in a column direction, and the selected bank A column redundancy control circuit of a semiconductor memory device having a row decoder for selecting a word line of a unit cell array belonging to and a column decoder for selecting a column corresponding to a memory cell connected to the word line. Has a single column redundancy circuit that controls column repairs And a gong.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

First, a multibank configuration will be described. In order to realize high speed and high integration of a memory device, a plurality of memory seal arrays may be configured as a plurality of blocks, and a plurality of blocks may be arranged in a column and row direction to form a bank. It is common knowledge in this field that constructs are a trend of recent high density memories. 1 is an overall configuration diagram of a column redundancy apparatus according to the present invention. Referring to FIG. 1, different banks 0 and 1 have row decoders 0 and 220, which are independent row decoders, and each bank has a plurality of data outputs DQ1 to DQn. An array of the plurality of data output lines is shared between bank 0 and bank 1 through global I / O line 15, which is an input / output line (I / O line) for transmitting the data outputs DQ1 to DQn. Each column has independent column decoders 0 to n (301, 302, 303), and local I / O lines 11, 30, 17, which are lines that sense memory cell data and transmit them to global I / O line 15 21 for each array block constituting each bank, each of the array blocks has a local column selection line (LCSL) 35, 37, 39, 41 for switching the memory cell and local I / O, and selects the local column. Gating lines 35, 37, 39, 41 The memory device has a configuration in which bank addresses of banks 0 and 1 are input as means, and the output of the column decoder controls the global column selection line 33.

2 is a block diagram showing the column redundancy and configuration according to the present invention. Referring to FIG. 2, as in the description of FIG. 1, a bank address is used as a means for gating the local column selection line LCSL to control access of each bank regardless of the global column selection line. Can be. Therefore, only the column address is used as the input of the normal column decoder to drive the global column selection line. At this time, the redundant global column selection line is in a disabled state. When repair occurs, repair is realized by replacing redundant global column selection lines SGCSL0 to SGCSLN of redundant memory by cutting the fuse that stores the column address and bank address of the defective cell. do. At this time, the global column selection line SGCSL is used for both bank 0 and bank 1, but enables the local column selection line of the bank selected by the bank address controlling the local column selection line. The normal global column selection line GCSLN is disabled by the signal RENi generated by the fuse cut during the repair to prevent multi selection of the global column selection line.

3 is a configuration diagram having repair means independent of each of the column decoders according to an embodiment of the present invention. Referring to FIG. 3, reference numerals 21, 23, 25, 27, 29, 31, 33, and 35 are row selection circuits, and reference numerals 45, 46, 47, 48, 49, 50, 51, and 52 are master purses. It's a Woods circuit. FIG. 3 shows that the repair means are configured independently for each column decoder.

4 is a specific circuit diagram of the fuse box means according to the present invention. Referring to FIG. 4, the master fuse means 500 for disabling the output of the fuse box when the repair is not performed, and the decoded column address is the full external supply voltage Vcc. A level shift 600 for converting the voltage to a voltage boosted to be delivered to a level, a means 700 for controlling a fuse of a bank address, and a global column selection line under conditions where both the column address and the bank address are satisfied. It consists of a sensing means 800 for driving. 5 is a detailed circuit diagram of a circuit for driving a redundant global column selection line according to the present invention. Referring to FIG. 5, the output signal RENi and the master signal Master in FIG. 4 are input, and are inversely ANDed through two NAND gates 30 through two inputs through inverter chains 10 and 20, respectively. This output signal also outputs the drive signal RENiD through the inverter 40.

6 is a detailed circuit diagram of a redundant global column select line driver according to the present invention. Referring to FIG. 6, the driving signal RENiD is input to output a redundant global column selection line selection signal RGCSL through the inverter chain 50 rate.

7 is a detailed circuit diagram of a circuit for implementing and disabling a normal global column selection line according to the present invention. Referring to FIG. 4 and FIG. 7, the description of the configuration is conventional, and therefore, the description will be omitted, and the operation outputs the decoded column address by inputting the master signal Master. The fuse cutting method cuts the fuse connected to the rest of the decoding, leaving only the selected column address for the decoded column address. For example, when the decoded column address DCA01 is selected, fuse cuts are performed on the column addresses DCA0B1, DCA01B, and DCA0B1B. The remaining DCAij is also cut like DCA01. In addition, the repair operation may be performed on the bank address by cutting the fuse of the selected bank address in a manner opposite to that of the column address.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (5)

A plurality of split word line drivers disposed between a plurality of unit cell arrays, a plurality of sense amplifier blocks disposed between the unit cell arrays arranged in a column direction, and a plurality of divided word line drivers disposed between the unit cell arrays arranged in a row direction And a plurality of banks arranged in a column direction as a plurality of divided groups including a plurality of unit cell arrays, and one low decoder for selecting the bank and selecting a word line of a unit cell array belonging to the selected bank. And a column redundancy control circuit of a semiconductor memory device having a column decoder for selecting a column corresponding to a memory cell connected to the word line, the column redundancy circuit for controlling column repair of the plurality of banks. And a column redundancy control circuit of the semiconductor memory device. 2. The column redundancy control circuit of claim 1, wherein the repair is performed when the column redundancy circuit satisfies both the column address information and the bank address information. 2. The column redundancy control circuit of claim 1, wherein the column redundancy circuit comprises a column redundancy control means having a means dependent from a bank address and a repair means independent of the bank address. The low global value of claim 1, wherein the plurality of banks share a global column selection line, which is an output of a column decoder having an output unrelated to a bank address, and is low global only when the bank address and the column address are satisfied even during a repair operation. And means for replacing the column select line with a corresponding global column select line. 5. The method of claim 4, wherein the repair operation is configured to replace the memory cell array corresponding to the selected row global column selection line irrespective of a bank by a bank address that gates a local column selection line. A column redundancy control circuit of a semiconductor memory device.