KR970051446A

KR970051446A - Redundancy Roo Decoder Circuit

Info

Publication number: KR970051446A
Application number: KR1019950066143A
Authority: KR
Inventors: 이상우
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-12-29
Filing date: 1995-12-29
Publication date: 1997-07-29

Abstract

본 발명은 반도체 기억 장치의 리던던시 로오 디코더 회로에관한 것으로, 결함된 정상 워드 라인을 리페어함에 있어서 퓨즈 박스의 수를 늘리지 않고도 한 블럭에서 최대 4개까지 리페어어가 가능하도록, 결합된 정상 워드 라인이 있는 블럭 제1블럭인지 제2블럭인지를 선택하기 위한 신호를 출력하는 블럭선수단과, 상기 블럭선 택수단의 출력 신호와 리페어 인에이블 신호 및 로오 어데레스에 의해 상기 제1블럭 및 제1블럭의 스페어 워드라인을 선택하기 위한 출력하는 4개의 주 디코더 주단과 상기 주 디코더 수단의 출력 신호에 의해 선택된 스페어 워드 라인으로 고전위를 공급한 4개의 부 디코더 수단을 구비하여 리페어 효율을 증대시켰다.The present invention relates to a redundancy row decoder circuit of a semiconductor memory device, in which there is a combined normal word line for repairing up to four blocks in one block without increasing the number of fuse boxes in repairing a defective normal word line. A block selecting means for outputting a signal for selecting whether the block is a first block or a second block, and a spare of the first block and the first block by an output signal of the block selecting means, a repair enable signal and a row address; The repair efficiency was increased by including four main decoder main stages for outputting word lines and four sub decoder means for supplying high potentials to the spare word lines selected by the output signal of the main decoder means.

Description

Redundancy Roo Decoder Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 일실시예에 의한 리던던시 로오 디코더 회로도.2 is a redundancy row decoder circuit diagram according to an embodiment of the present invention.

Claims

A redundancy row decoder circuit of a semiconductor memory device, comprising: block selection means for outputting a signal for selecting whether a block having a defective word line is a first block or a second block, an output signal of the block selection means, and a repair in The signal for selecting the spare word lines of the first and second blocks by the enable signal and the low order is output to the four main decoder means called output and the spare word line selected by the output signal of the fraudulent main decoder means. A redundancy row decoder circuit comprising four sub decoder means for supplying the stomach.

2. The redundancy row circuit of claim 1, wherein the block selecting means selects the first block or the second block by one fuse option.

2. The redundant row decoder circuit according to claim 1, wherein said main decoder means comprises one NAND gate and an inverter.

2. The redundancy row decoder circuit according to claim 1, wherein the row address signal of the input signal of the main decoder means is the word address of the word line boosting signal_pre decoder.

※ Note: The disclosure is based on the initial application.