KR0172385B1 - Apparatus and method of block redundancy of semiconductor memory device having burn-in mode depending on over-active - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a block redundancy apparatus and method of a semiconductor memory device.

2. The technical problem to be solved by the invention

An object of the present invention is to control whether eight blocks are simultaneously repaired by the repair control signal REP during normal operation, and to determine whether to repair a normal word line, and when excessive active, four codes for the highest low address RAmax and RAmaxB are entered. Disclosed is a block redundancy apparatus and method for controlling blocks as independent repair control signals REP.

3. Summary of Solution to Invention

In the block redundancy device of a semiconductor memory device, an intermediate control circuit connected to the normal blocks to control a repair of a corresponding block by inputting a repair control signal during an overactive operation, a fuse box, and An over-active topmost low address fuse circuit for storing money-care processed low addresses to determine which low address the fuse box has been repaired upon over active and connected to a fuse box, and from the fuse box And a repair control signal generation circuit for outputting the repair control signal by logically combining the predecoded signals as inputs.

4. Important uses of the invention

It is suitably used for semiconductor memories.

Description

Block Redundancy Apparatus and Method of Semiconductor Memory Device Having Burn-in Mode According to Over Active

1 is a block diagram showing a block redundancy apparatus according to the prior art.

2 is a detailed circuit diagram of a fuse box according to the prior art.

3 is a block diagram of a repair control signal generation circuit of an intermediate control circuit according to the prior art.

4 is a block diagram showing a block redundancy apparatus according to the present invention.

5 is a detailed circuit diagram of a fuse box according to the present invention.

FIG. 6 is a detailed circuit diagram of the over-active most significant low address fuse circuit of FIG. 5. FIG.

7 is a block diagram of a repair control signal generation circuit of an intermediate control circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a block redundancy device in which an intermediate control circuit is added to each block of a predetermined unit during block redundancy, and a repair control signal is generated per block of a predetermined unit to perform efficient redundancy. There is one redundancy block per 8 blocks, and the spare word line of the redundant block will repair the normal word line of 8 blocks. In a row active operation, if one normal word line is enabled per eight blocks, and the normal word line is repaired, the normal word line is disabled and a spare of the redundant block is enabled. In a semiconductor memory device using a block redundancy method in which word lines are enabled, stress is activated by applying word lines in a high temperature state in order to increase the reliability of the semiconductor memory device. In case of over active, 4 blocks by don't care the highest low address bit RAmax separating 8 blocks. When enabled by one word line can be reduced to two times over the active time of applying a stress per chip (chip) is in the normal operation of the half. However, when the top-lower address is money-careed, the following problem occurs because the output REP of the fuse box controls all eight blocks. 1 is a block diagram showing a block redundancy apparatus according to the prior art. Referring to FIG. 1, when 8 lines are repaired, when word line 10 is repaired as a spare word line 30, when the low address corresponding to the normal word line 10 is received, the repaired normal word line 10 is disabled. State and spare wordline 30 of the redundant block is enabled. In this case, the output word REP of the fuse box 100 disables the normal word line 20, except for the highest low address, so that the normal word line 20 is not enabled and is not stressed so that correct redundancy cannot be executed. There is this.

2 is a detailed circuit diagram of a fuse box according to the prior art. Referring to FIG. 2, the PMOS transistor 3, which has a source connected to an external power supply voltage VDD terminal, a drain connected to a node 28, and a precharge signal input to a gate input, and an external power supply voltage VDD terminal and a source connected thereto, A predetermined number of fuses sequentially connected to a node PMOS transistor 5 having a drain connected to the node 28 and an output of the inverter 25 to a gate input, and a node 28 connected to the common drain of the PMOS transistors 3 and 5; And a drain connected to one side of the fuse, a source connected to a ground voltage VSS terminal, and a low address RAmaxB, RAmax, ..., RAmin respectively input to a gate input terminal. , Pre-decoded signals consisting of 13, 15, 17, ..., 21, 23 and inverters 27, 29 connected in series with an input terminal connected to the node 28 Outputs (i = 1 to n).

3 is a block diagram of a repair control signal generation circuit of an intermediate control circuit according to the prior art. Referring to FIG. 3, the configuration is one input of the lowest low address RAmin from the highest low address RAmax and one of the complementary address RAminB of the lowest low address RAmin from the complementary address RAmaxB of the highest low address RAmax as the other input. The first fuse box 101, the second fuse box 102, ..., the nth fuse box 300 which output precoded signals by using the precharge signal as another input, and the n fuse boxes The predecoded signal output through (n = 1 to n), respectively, as an input and an inverse logic, respectively, and as an input and an inverse logic, respectively, a NAND gate 301 for outputting the repair control signal REP.

Accordingly, an object of the present invention is to determine whether or not the normal word line is repaired by controlling eight blocks at the same time during the normal operation with the repair control signal REP, and coding of the uppermost low addresses RAmax and RAmaxB during excessive activation. The present invention provides a block redundancy apparatus and method for controlling each block as an independent repair control signal REP.

According to the technical idea of the present invention for achieving the above object, a plurality of memory array consisting of a plurality of memory arrays connected in a matrix form, and a plurality of normals composed of the memory arrays including a normal word line 10. A block redundancy device of a semiconductor memory device having blocks and a redundant block positioned at a side of the normal block and having a spare word line for repairing a defective block, comprising: a repair control signal connected to the normal blocks in an over active state Intermediate control circuits for controlling repair of the corresponding block by inputting and the intermediate control circuits connected to the intermediate control circuits are determined as pre-decoded by determining the corresponding low address of the block to be redundant among the low addresses. Supply a signal to the intermediate control circuits Is an over active top-level low address fuse circuit for storing money-care processed low addresses connected to the fuse box to determine which low address the fuse box has been repaired upon over-active. And a repair control signal generating circuit for outputting the repair control signal by logically combining the predecoded signals from the fuse box as inputs.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

4 is a block diagram showing a block redundancy apparatus according to the present invention. Referring to FIG. 4, eight blocks BLK1 to BLK8 and spare blocks, a first intermediate control circuit, and a second intermediate control circuit are configured. When block redundancy is used for eight blocks, one word line is enabled per eight blocks during normal operation, and one word line is enabled per four blocks during excessive active operation. Money-care. By giving the over active information from a row decoder (not shown) to make the uppermost low addresses RAmax, RAmaxB to a logical low so that the fuse box 100 does not receive the RAmax, RAmaxB, and the first and the first The RAmax and RAmaxB entering the dual control circuit are both enabled to activate twice the normal operation. In the fuse box 100, when the RAmax and RAmaxB are don-careed, it is not known whether the fuse is cut with the RAmax or RAmaxB, so that a dummy fuse box (to be described later) Add). The normal word to repair with the output of the fuse box 100 and the signal POA (signal enabled at burn-in over active) and the over active most significant low address RAmax fuse output so as to know whether it is repaired with the RAmax or RAmaxB. It can be seen whether a line belongs to four blocks under the control of RAmaxB or four blocks under the control of RAmax. Therefore, since it is possible to disable only the normal word lines of the repaired four blocks by controlling four blocks independently during over-active, double word lines are always enabled during the over-active. In order to control the four blocks of the RAmax and the four blocks of the RAmaxB separately during over-active, when repairing to the RAmax during fuse cutting, the uppermost low address RAmax fuse is cut, while the repair with the RAmaxB is the highest low. Do not cut the address RAmax fuse.

5 is a detailed circuit diagram of a fuse box according to the present invention. Referring to FIG. 5, the configuration is the NMOS transistor 7 in which the low addresses ranging from the highest low addresses RAmax and RAmaxB to the lowest low addresses RAmin and RAminB are gate inputs, and each drain is connected to each fuse. , 9, 11, 13, 15, 17, ..., 21, 23, precharge signal as gate input, external power supply voltage VDD terminal and source are connected, drain is node PMOS transistor 3 connected to N1, PMOS transistor 3 and source connected to drain and source connected to drain, PMOS transistor 5 whose input from the node N1 through the inverter 25 is the gate input, and the highest active over Inverter 4, the output of the low address fuse circuit 1000 and the output of the over-active top-most low address fuse circuit 1000 is passed through node 50 to the input stage 5, the NAND gate 41 having two inputs with the output active signal and the over-active enable signal POA connected to an input terminal, and the NAND gate passing through the node 52; NAND gate 47 for inverting and logically multiplying the output of 41 as an input and the output of the node N1 as another input, an inverter 49 having an input terminal connected to an output terminal of the NAND gate 47, and an input terminal connected to an output terminal of the inverter 45 And a NAND gate inverted and logically multiplied with the over-active enable signal POA as one input, and an NAND gated inverted and logical output using the output of the NAND gate 43 that passed through node 53 as one input and the output of the node N1 as another input. And an inverter 63 having an input terminal connected to the NAND gate 61 output terminal.

FIG. 6 is a detailed circuit diagram of the overactive most significant low address fuse circuit of FIG. The structure is a PMOS transistor 71 having a reset signal, RESET, as a gate input, a source connected to an external power supply voltage VDD terminal, and a drain connected to an over-active uppermost low address fuse 81, and the signal RESET being a gate input. A drain connected to the over-active highest-lower-level fuse 81 connected to the drain of the PMOS transistor 71, and a source connected to a ground voltage VSS terminal; and a drain and an EnMOS transistor of the PMOS transistor 71. A drain transistor is connected to a node 49 connected with a drain of 73 and a node 50 is connected to a gate input terminal. Referring to FIGS. 6 and 5, the operation of the over-active enable signal POA becomes logical high and if the over-active highest row address fuse is cut, node 50 becomes a logic high and a fuse box. When the repaired low address comes in, the node N1 becomes a logic high, and thus, the node 52 becomes a logic low, thereby making the predecoded signal PREDB-i outputted as a logic low so that the repair control signal REPB becomes a logic high. Node 53 is also logic high, making predecoded signal PRED-i logic high, so repair control signal REP is logic low. In the four blocks controlled by the RAmaxB, the repair control signal REPB becomes logic high and the normal word line is enabled. In the four blocks controlled by the RAmax, the repair control signal REP becomes a logic low and is the first intermediate. Disable the control circuitry or the second intermediate control circuitry and enable the spare word line of the redundant block. On the contrary, if the overactive most significant low address fuse is not cut, current flows through the PMOS transistor 71, the overactive most significant low address fuse 81, and the NMOS transistor 75, but the NMOS transistor 75 is longer than the normally used NMOS transistor. Is about 5 times larger and the PMOS transistor 71 is normally PMOS transistor, the node 49 is logical high and the inverter 50 is logic low by inverter 77 so that the NMOS transistor 75 is turned off. (Turn Off). Accordingly, in FIG. 5, when the over-active enable signal POA becomes logic high and the low address repaired in the fuse box comes in, the node N1 is logic high and the node 52 is logic high, so that the predecoded signal PREDB- Make i high to logic high so that repair control signal REPB goes to logic low. In addition, the node 53 becomes a logic low to make the predecoded signal PRED-i a logic low so that the repair control signal REP becomes a logic high. Therefore, in the four blocks controlled by the RAmaxB, the repair control signal REPB becomes a logic low to disable the first intermediate control circuit or the second intermediate control circuit, enable the spare word line of the redundant block, and the RAmax. In the four blocks under control of the repair control signal REP is logic high, and the normal word line is enabled. The middle of four blocks into which the coding of RAmax is entered among the eight blocks that apply block redundancy by generating the repair control signals REP and REPB based on the RAmax and RAmaxB information (ie, fuse cutting) of the over-active uppermost low address fuse. The repair control signal REP is used to control a control circuit, and the repair control signal REPB is used to control an intermediate control circuit of four blocks into which the coding of the RAmaxB is included. The over active most significant low address fuse is valid only when the over active enable signal POA becomes logic high for over active operation, and during normal operation, the signal POA becomes logic low and the repair control signals REP and REPB Since it is always the same, it operates in a normal block redundant manner.

7 is a block diagram of a repair control signal generation circuit of an intermediate control circuit according to the present invention. Referring to FIG. 7, the configuration is one input of the highest low address RAmax to the lowest low address RAmin as one input, and one of the complementary address RAminB of the lowest low address RAmin to the other input from the complementary address RAmaxB of the highest low address RAmax to the other input. And the first fuse box 31, the second fuse box 33, ..., the nth fuse box 200, and the n fuse boxes for outputting predecoded signals using the precharge signal as another input. NAND gates 201 and 202 output the repair control signals REP and REPB by inverting and multiplying the predecoded signals and the complementary signals corresponding thereto, respectively.

The effect of the present invention described above is that when using the block redundancy method, the word line can be activated more than the number of word lines that are activated during normal operation. In the case of eight blocks, a control control circuit is added in units of four blocks. In addition, by controlling the eight blocks in half as two repair control signals and a complementary repair control signal of the fuse box, the output of the fuse shows which address the fuse box is repaired to, and thus, an arbitrary normal word line. This redundancy is selectively applied to all of the stresses.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (7)

A memory array comprising a plurality of memory arrays connected in a matrix form, a plurality of normal blocks composed of the memory arrays and including a normal word line, and a spare word line disposed on a side of the normal block 10. A block redundancy device of a semiconductor memory device having a redundant block for repairing a defective block, wherein the intermediate control circuit is connected to the normal blocks to control a repair of a corresponding block by inputting a repair control signal when the active block is overactive. And a fuse box connected to the intermediate control circuits and configured to determine a corresponding low address of a block to be redundant among the low addresses by inputting a low address, and supply a pre-decoded signal to the intermediate control circuits. Connected to the fuse box and over active An over-active top-level low address fuse circuit for storing money-care processed low addresses to determine which low address the fuse box has been repaired to, and predecoded signals from the fuse box as inputs, respectively. And a repair control signal generation circuit for outputting the repair control signal by performing a logical combination to the block redundancy device of the semiconductor memory device. The block redundancy device of claim 1, wherein the intermediate control circuits control the plurality of normal blocks by dividing the plurality of normal blocks into half or even pairs. The block redundancy device of claim 1, wherein the repair control signal generating circuit generates two or more repair control signals. The block redundancy device of claim 1, wherein the repair control signal generation circuit comprises two or more NAND gates. A memory array comprising a plurality of memory arrays connected in a matrix form, a plurality of normal blocks composed of the memory arrays and including a normal word line, and a spare word line disposed on a side of the normal block A block redundancy method of a semiconductor memory device having a redundant block for repairing a defective block, the method comprising: money-care processing an arbitrary address that decodes to activate more word lines than the number of word lines activated during normal operation And the money-care address of the fuse box having an over active top-level low address fuse circuit that will store the money-care processed address to know to which address the low fuse box has been repaired and use it to decode over-active. To control repair information A block redundancy method of a semiconductor memory device. 6. The fuse box according to claim 5, characterized in that the fuse box uses a fuse by means of a money-careed address when overactive so that an output of the fuse can be used to determine to which address value the fuse box is repaired. A block redundancy method of a semiconductor memory device. 6. The method of claim 5, wherein if one redundant block for a predetermined number of normal blocks is in the defect array normal array block, a signal repair control signal combining a plurality of low fuse box outputs disables the normal word line so as to disable the redundant block. And at least two repair control signals per predetermined number of normal blocks when the spare word line in the spare word line can be enabled.