KR950000428B1 - Redundancy circuit of memory device - Google Patents

Abstract

The circuit minimizes the occurance of racing by disabling the output of X+ predecoder for preliminary status. This circuit comprises a row address signal generating unit (SREi) which is for operating the selection of spare row by combining normal row signal (RRi,n) with some normal row enable timing signal (RAE), a spare row address signal (SREj) which is for operating spare row selection by combining the normal row enable timing signal (RAE) with normal row signal (RRj,n), the first logic unit which outputs a row disable signal (NRDn) responded by at least one enable operation, the second logic unit which outputs a block row address to a connected node (V3) by responding to the row disable signal (NRDn), a normal row predecoder enable unit which enables a normal row predecoder by transferring a word line transfer signal (X+) to an output node, a level control unit which transfers voltage at the connection node (V3) to the normal row predecoder enable unit and a gate, and a reversing unit which is connected with the input of the connection node (V3).

Description

Redundancy Circuit of Memory Devices

1 is a conventional redundancy circuit diagram.

2 is a block diagram of an address input confirmation signal generator.

3 is an X ⁺ predecoder circuit for normal column selection by FIG.

4 is a timing diagram for explaining the operation of Figures 1 to 3.

5 is a redundancy circuit diagram of a memory device according to the present invention.

6 is an X ⁺ predecoder circuit for normal column selection by FIG.

7 is a timing diagram for explaining the operation of FIG. 5 and FIG.

8 is a CMOS driving circuit diagram.

* Explanation of symbols for main parts of the drawings

B1 and B2: Redundancy Circuit MP1, MP11, MP51: PMOSFET

MN1 to MN18: NMOSFET MN51 to MN66: NMOSFET

The present invention relates to a redundancy circuit of a memory device. In particular, the output of the X ⁺ predecoder for the normal column selection is disabled in the preliminary state, and the X ⁺ predecoder is enabled and redundant when the normal column selection signal is input. The present invention relates to a redundancy circuit of a memory device which minimizes the occurrence of lashing by maintaining a disabled state when a column select signal is input.

Generally, when a wafer probe test is performed on a memory device, some chips perform stable pass operation, but the entire chip cannot be used due to a failure of some bits (columns or rows). There is also. Therefore, the entire chip can be reproduced by embedding an extra memory cell in addition to a predetermined memory cell and replacing a failed bit within the extra bit range. A circuit for performing such an operation is called a redundancy circuit.

1 is a conventional redundancy circuit diagram, in which transistors NM1 to MN18 are connected in the form of a wired-or-wire from the drain terminal of the charging element transistor MP1 for inputting the charge state signal? PPE. Transistor MP2 is a latch-back device that prevents the floating state of node RRi (the output node of the ith redundancy circuit) after transistor MP1 is turned off. The address signals AX8 and AX9 input to the gate terminals of the transistors MN1 and MN2 are memory block selection signals, for example, one of four blocks selected by AX8 and AX9 to reduce power consumption in 4M DRAM. Only block operation). In addition, the NMOS transistors of the transistors MN3 to MN18 have the same connection type. The laser-cut fuses F1 to F16 are connected between the drain electrode and the node RRi, and each gate terminal has a pre-decoding of the X address signals 0 to 7. 16 signals in which AX01, AX23, AX45 and AX67 are combined are input. The series connection structure of the fuses F1 to F16 and the transistors MN2 to MN18 is for programming a row address to be replaced by a failure. That is, blow the fuse corresponding to the binary status of the address. For example, when the binary status of the address of the failed column is 00,01,11,10 as shown in <Table 1>, AX0.1 , AX2.3,]

TABLE 1

The fuse connected to the transistors to which the addresses of AX4.5 and AX6.7 are supplied is blown, and when the input of one of the four combinations of the address signals AX2.3 becomes high, the high state is immediately output. With the RAE (normal thermal enable timing signal) output as the input of the NAND gate G1, RRj (the output node of the jth redundancy circuit) is in an unprogrammed state (i.e. all fuses are still connected) and RRi is programmed with Xi. Assuming that the operation will be described with reference to FIG. 4 as follows.

If the address input is Xi, there is no connection to discharge the high state of charge of the RRi. Therefore, it remains high and the output node of MRDi (NRD redundancy redundancy circuit), which is the disable signal of the normal row, is the moment RAE goes high. ) Transition to a high state. This causes node X5, the input of the X ⁺ predecoder for the normal column decoder in the form of a "NOR" gate, to go high, turning off all X ⁺ predecoder. This occurs when all the state of charge of node V1 is discharged by the " on " of transistor MN25 to be low together with node V2, so that all MN27 transistors are turned off.

In this way, after disabling all normal columns, the pre-built redundant columns (lead columns) are enabled to allow replacement of the failed row. In addition, if the fuse blows, it will be permanently shorted so that redundant rows will continue to be selected for the Xi input.

On the other hand, if the address input is not Xi, the comparison state output RRi is discharged low because there is a discharge connection state consisting of a fuse and an NMOS transistor. Therefore, both NRDi and V5 are low. Thus the X ⁺ predecoder for the normal thermal decoder of FIG. 3 is determined by the states of AX8 and 9, AXO and 1. If selected, all discharge connections are disconnected (MN21 to 25 are all off), so node V2 is charged by the number of Vcc-V, V3 transitions from low to "H", and a strapping effect occurs to node V4. Pass the signal of V3. This selects a column corresponding to the input address among the normal columns. In the above description, the note strapping effect is that the note Vx is precharged as Vcc-Vtn and then the node. In the 0V it means that the effect of X ⁺ potential is delivered sufficiently to the Vcc or held in the NMOS when raised to more potential rises to Vcc-Vtn + 0V by strapping effect "Vt- loss" X ⁺ predecoder without .

Here, V1 selected at Xi input (i.e. selected by AX8,9,0,1) will go off until T ₁ time NRD transitions to "H" so that no normal column selection occurs when selecting redundant columns ( In order to prevent lashing from occurring, the V3 node must be enabled high at a safe time after T ₁ . Therefore, it is a technique that carries the risk of time loss and lashing.

In addition, in the case of using the CMOS driving circuit as shown in FIG. 8, the X ⁺ predecoder for the normal column is not enabled in the standby state, and thus this method cannot be used.

Therefore, in the present invention, all the X ⁺ predecoder is turned off during the charging state, and the selected X ⁺ predecoder is enabled when the normal heat is input, and the off state is maintained as it is when the redundant heat is input. It is an object of the present invention to provide a redundancy circuit of memory elements that is minimized.

The redundancy circuit of the memory device of the present invention comprises a spacing open-dress signal generating means for generating an extra open-dress signal SREi by combining a normal column signal RRi, n and a normal column enable signal, and the plurality of normal columns. First logic means for logicing a signal, second logic means for logicing an output signal and a block selection signal from the first logic means, first inverting means for inverting an output signal from the second logic means, and Level adjusting means for maintaining the output signal from the first inverting means at a constant level, and a normal column for enabling the normal column predecoder by transmitting a word line transfer signal X ⁺ according to the output signal from the level adjusting means. Predecoder enable means, second inverting means for inverting the output signal from said first inverting means, and output of said second inverting means According to a call is characterized in that the configuration for the normal column pre-decoder enabled by normal column predecoder means disabling means for enabling display.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The circuits of FIGS. 5 and 6, which are circuits using the principles of the present invention, will be described in connection with the operation waveform of FIG. As previously described in the prior art, RRi, n is programmed with the Xi address and RRj, n is unprogrammed.

Different from the prior art, the comparison output terminals RRi, n are connected directly to one input of the normal X ⁺ predecoder without being affected by the address input confirmation signal RAE. In the standby state, since both RRi and n are "H" due to the low of PRE, NRDn, 62 is kept low, and all normal X ⁺ predecoder is off. (I.e. MN73 is on to disable X ⁺ predecoder 61 at 0V)

Here, if an address input corresponding to an extra column occurs (that is, Xi input), RRi, n remains high even after AXij is selected, so all X ⁺ predecoder remain off in standby state, and RAE As it transitions high, the SREi, an extra column enable signal, goes high, and the extra columns are selected and the normal columns become inactive.

In the case of Ax ≠ Xi, the selected X ⁺ predecoder is operated at the time when RRi, n and RRj, n are discharged and NRDn transitions high.

Therefore, all X ⁺ predecoders are controlled regardless of the address input confirmation signal and RAE input, and after checking that they are not normal column selection (RRi, n and RRj, n discharge), the normal X ⁺ predecoder is operated so that There is no danger at all.

As described above, according to the present invention, since all the states are determined by the address input state, fast and stable operation is possible, and it is convenient to use a CMOS word line driver.

Claims (1)

In a redundancy circuit of a memory device that performs a defect repair operation by enabling an extra column in response to an internal program operation corresponding to a predetermined defective address input, in response to an input of the defective address when an external address is input. The normal column signal RRi, n that is enabled is generated internally in response to the program operation, and the normal column signal RRi, n is combined with a predetermined normal column enable timing signal REA to select a spare column. Means for generating an extra open-dress signal SREi for driving, and internally generating a normal column signal RRj, n that is enabled in response to the input of the defective address upon input of an external address in response to the program operation; This normal column signal RRj, n is combined with the normal column enable timing signal REA to provide a spare for driving the selection of the spare column. Means for generating an address signal SREj and a thermal disable for inputting the normal column signals RRi, n and the normal column signals RRj, n, respectively, and responding to an enable operation of at least one of the two normal column signals. A first logic means for outputting a signal NRDn, an open dress for selecting a specific normal column predecoder, and a block string address for selecting a block to which a particular column belongs, respectively, and input this input to the column disable signal. Second logic means for outputting to a predetermined connection node V3 in response to an input of (NRDn), a gate connected to the connection node V3, and a predetermined word in response to a voltage level of the connection node V3. A normal column predecoder enable means for transmitting a line transfer signal (X ⁺ ) to an output node to enable a normal column predecoder, and a gate between the connection node V3 and the normal column predecoder enable means. four Level adjustment means for boosting the voltage applied to the connection node V3 and transferring the voltage to the gate of the normal column predecoder enable means, and an inverting means connected to an input terminal of the connection node V3. And a normal column predecoder disabling means for discharging the voltage applied to the output node in response to an output signal of the inverting means, the gate being connected to the inverting means and having a channel formed between the output node and the ground terminal. In response, when at least one of the normal column signals RRi and n or the normal column signals RRj and n occurs, the memory device performs an operation of disabling the output operation through the output node. Redundancy circuit.