KR100242719B1 - Semiconductor device having row fail restoration circuit - Google Patents

Abstract

A semiconductor memory device having a row defect recovery circuit for improving repair efficiency is disclosed. The apparatus includes a plurality of row fault recovery circuits having a fuse fuseable to the spare word line driver and enables only one selected spare word line to be activated even if at least two or more row fault recovery circuits respond to the same address. do.

Description

Semiconductor memory device with low fault recovery circuit {SEMICONDUCTOR DEVICE HAVING ROW FAIL RESTORATION CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a volatile semiconductor memory device such as a DRAM having a row defect recovery circuit for improving repair efficiency.

In general, a volatile semiconductor memory device such as a dynamic random access memory (DRAM) having a plurality of memory cells as an array in a matrix form and accessing data in a selected memory cell in synchronization with a clock input from an external device is normally used. The memory cells in the memory cell array are designed and manufactured to have redundant redundant memory cells for replacing normal memory cells in case of defective or defective memory cells.

To prevent such semiconductor memory devices manufacturing plant the degradation of before shipping, a good and at the same time ensuring the reliability of the chip and exposing the device that potential defects in Sikkim device after manufactured, defects in a wafer state or a pack keji state Screening operations to detect memory cells that are present are generally performed in the art. As a representative screening method, a burn-in test method that is capable of simultaneously realizing both field acceleration and temperature acceleration is commonly used. In the burn-in test method, also referred to as a stress test , the normal memory cells in the semiconductor memory device are placed in a state where the test voltage is set higher than the voltage practically used in operation and the temperature is set higher than the temperature practically used. Tested

When a defect of a memory cell located in a normal memory cell array is detected in the test step , the detected defective memory cell is replaced by a cell unit or a cell block unit as a redundancy cell. In the replacement operation, a low redundancy scheme for salvaging defective memory cells in the row direction of the memory cell array and a column redundancy scheme for salvaging in the column direction are well known in the art. By completing a low redundancy scheme that typically employs a row address fuse box that is blown by laser cutting or the like, upon application of a repaired row address, the redundancy row decoder provides a word line drive signal and an enable signal to the normal word line driver. It operates in place of a normal row decoder that provides a redundancy wordline driver. The redundancy word line driver typically provides a voltage type signal to the selected redundancy word line to drive each of the access transistors of the redundant memory cells connected to the same row. Therefore, in accordance with the above replacement operation, the redundancy memory cell replaces the read and write operations of the defective normal memory cell permanently in normal operation after shipping.

As described above, the normal row decoder and the redundancy row decoder respond in response to the applied row address so that the redundant memory cells replaced by the presence or absence of normal memory cells are selected or deselected in the row direction during the operation of the chip. Each word line driver should be properly controlled. A normal word line disable unit and a spare word line driver for providing a disable signal to the redundancy row decoder and the normal word line driver may be used. A row fault recovery circuit is formed.

1 is a block diagram related to row selection of a conventional DRAM. The row fault recovery circuit includes a redundancy row decoder 9, a normal word line disable unit 10, and a spare word redundancy driver 12 that provide a disable signal to a normal word line driver 11. 2 is an operation timing diagram of each part of FIG. 1 during a memory cell repair.

Referring to FIG. 1, a memory cell array includes a normal memory cell array 1 having a plurality of normal memory cell NMCs in a matrix form, and a spare memory cell array 2 having a plurality of spare memory cell SMCs arranged in a matrix form. . One memory cell includes one access transistor and one storage capacitor. A gate of the access transistor is connected to a word line in a row direction and a drain or source of the transistor is connected to a bit line in a column direction. A plurality of word lines and bit lines are orthogonal to each other to form a matrix structure, and each memory cell has an array structure intersected by one at each intersection point of the matrix. The word line connected to the normal memory cell NMC is referred to as a normal word line NWL, and the word line connected to the spare memory cell SMC is referred to as a spare word line SWL.

The / RAS buffer 3 receives the row address strobe signal / RAS applied from a control unit such as a central processing unit and outputs an output signal PR. The output signal PR is output as a logic level " low " when the chip is in a standby state and as high when in the active state as shown in the operation timing of FIG. The row address buffer 5 buffers and outputs the address A0-An input from the outside in response to the output signal PR as the row address signal RAi (where i is a natural number such as 0, 1, 2, etc.) and the complementary row address signal RAiB . . Here, the row address signals RAi and RAiB are both output as "low" when the chip is in a standby state, and either one is output as high depending on the input address when the chip is in the active state. The PXP generator 6 inputs the signal PR and outputs a signal PXP for precharging the row decoder. The signal PXP has the same phase as the PR as a true signal of the PR.

The row predecoder 7 predecodes the row address signal RAi and the complementary row address signal RAiB to output a decoded row address signal DRAij and a decoded complementary row address signal DRAiBjB. The row predecoder 7 is a block designed to compensate for the reduction in the level of the row address caused by the loading to the row decoder at a later stage. The normal row decoder 8 decodes the decoded row address signal DRAij and the decoded complementary row address signal DRAiBjB again to provide a decoded signal to the normal wordline driver 11 to select a wordline for driving a normal memory cell. An internal configuration of the normal word line driver 11 is shown in FIG.

On the other hand, has a plurality of fuses therein, the decoder bonded row address signal DRAij and decode bonded FIG redundancy row decoder 9 for outputting a redundancy signal REDi for receiving the complementary row address signals DRAiBjB driving the spare word line driver 12 3 Has the same configuration as An internal configuration of the spare wordline driver 12 is shown in FIG. The normal word line disable unit 10 which provides the disable signal to the normal word line driver 11 when the defect is repaired has the configuration as shown in FIG. 4 to receive the redundancy signal REDi and generate the signal PRRE. The redundancy row decoder 9 configured as RED0-n indicates that the normal word lines corresponding to the number of REDi may be replaced, where i is a natural number of 1 or more.

Referring to FIG. 3, the redundancy row decoder 9 includes a plurality of fuses 29 for programming an address of a defective memory cell , PMOS transistors P1, P2, inverters I1, 30, 31, and gates that input a power supply voltage to a source . It can be seen that the redundancy signal REDi is output as a high or low level by being composed of the NMOS transistors N1, N2, and N3 that input the decoded row addresses DRA2B3B, DRA23B..DRAijN .

The signal PXP of FIG. 2 generated by the PXP generator 6 shown in FIG . 1 is applied to the gate of the PMOS transistor P1 of the redundancy row decoder 9. The level of node N1 in FIG. 3 is determined according to the melting state of fuse 29 and the switching states of transistors N1-N3 that input the decoded row address DRAijN as a gate . At least one of the transistors N1-N3 inputting the decoded row addresses DRA2B3B, DRA23B..DRAijN is " turned on " in the case where there is no blown operation of the fuse, that is, there are no defects of the memory cells located in one row. . Accordingly, the "high" level potential precharged to the node N1 by "turning on" of the PMOS transistor P1 is discharged to the ground by the " turning on" operation of the NMOS transistor. This operation causes the output of inverter 31 to go "low" to enable the normal word line.

On the other hand, when a defect occurs in the normal memory cell , if fuses 29 in the redundancy row decoder 9 shown in FIG. 3 are melted with a laser corresponding to the address of the defective memory cell, the row address for selecting the defective memory cell is determined. Even when the last decoded row address DRAijN is activated, the "high" level potential precharged at the node N1 is maintained without being discharged to ground. Thus, the signal REDi is output as a "high" level. The signal REDi is applied to the normal word line disable unit 10 of FIG. 4 and the spare word line driver 12 of FIG. 6.

Referring to FIG. 4, it can be seen that the normal word line disable unit 10 including the NOR gate 32a, the inverter 32b, and the inverter 32c inputs the redundancy signal REDi to generate the signal PRRE. Noah gate 32a of FIG. 4 receives the signal REDi from a plurality of redundancy row decoders. When at least one of the input signals RED0-REDn is " high ", the output of the NOR gate 32a is " low & quot ; so that the normal word line disable signal PRREi output through the inverters 32b and 32c is also " low ""to be. Therefore, the normal word line driver 11 in FIG. 5 outputs the output NWEi as "low" during the redundancy operation to disable the normal word line.

5, the normal word line drivers 11 yen Mohs transistor for inputting a power supply voltage coat agarose transistors P1, P2, an inverter 33E, enter the decoder bonded row address to the gate N1, N2, the gate above the normal word line D. It can be seen that the transistor N3 is configured to input the sable signal PRREi . Therefore, when the normal word line disable signal PRREi is input as logic "low", the normal word line driver 11 configured as shown in FIG. 5 outputs the normal word line enable signal NWEi as "low" to activate the normal word line NWLi. To prevent.

Referring to FIG. 6, which is a detailed diagram of the spare word line driver 12 according to the related art, an enMOS transistor 34a for inputting a PMOS transistor P1, P2, an inverter 34b, and the signal REDi as a gate is shown. In the configuration and operation of FIG. 1 as described above, a conventional low fault recovery circuit including a redundancy row decoder 9 and a normal word line disable unit 10 and a spare word line driver 12 that provides a disable signal to a normal word line driver is provided. The operation timing relationship is shown in Fig. 7, which will be described below for the conventional defect recovery problem.

When the normal cell NMC in Fig. 1 is found to be a fail cell due to a process defect, the fuses 29 in Fig. 3 are melted in correspondence with the defect address. Accordingly, upon application of the repaired row address, the redundancy row decoder 9 operates in place of the normal row decoder 8 to drive the spare wordline driver 12. By this operation, the normal word line NWLi is disabled and the spare word line SWLi is activated. The timing by such a redundancy operation is shown by the dotted line in FIG. 2, and the waveform of the solid line which coexists with the waveform of the dotted line is the timing in the normal case without a defect.

2, it can be seen that the spare word line SWLi is activated when the repair is completed. However, the problem is that when the spare word line SWLi is selected by repairing the defect, the defect may also exist in the spare memory cell SMC. In this case the chip turns out to be a final failure and is discarded. If double fuse recovery is attempted by cutting another fuse of the decoder in the redundancy row decoder 9 and enabling a spare word line adjacent to the replaced spare word line as shown in FIG. 7, two words are stored in the same bit line. This results in the line being enabled, resulting in a read or write error. As described above, when the spare cell is defective, there is a problem in that it cannot be recovered again. The reason for this is that due to the configuration of the spare word line driver 12 in the row defect recovery circuit, a plurality of word lines are inevitably enabled for the same bit line during double defect recovery. Therefore, in the conventional low redundancy scheme, there is a problem in that defect relief cannot be performed when the replaced cell is defective.

SUMMARY OF THE INVENTION An object of the present invention is to provide a defect recovery circuit of a semiconductor memory device which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a semiconductor memory device having a row defect recovery circuit for improving repair efficiency.

Another object of the present invention is to provide a semiconductor memory device capable of performing a dual repair.

It is still another object of the present invention to provide a semiconductor memory device having a low defect recovery circuit capable of performing fault recovery to another redundancy cell by activating only one spare word line for the same bit line even in the case of a defective redundant cell. Is in.

According to the present invention for achieving the above object, a spare selected even with a low defect recovery circuit having a carpet fuse in the spare word line driver of a number, and the at least two low-defect repair circuit in response to the same address Only the word line is activated.

1 is a block diagram of a row selection of a typical DRAM.

FIG. 2 is an operation timing diagram of each part of FIG. 1 during a memory cell repair. FIG.

3 is a concrete diagram of the redundancy row decoder 9 in FIG. 1;

4 is a detailed view of a normal word line disable unit 10 in FIG. 1.

FIG. 5 is a detailed view of the normal wordline driver 11 of FIG. 1. FIG.

FIG. 6 is a detailed view of a spare wordline driver 12 according to the related art of FIG. 1.

7 is an operation timing diagram of a row defect recovery circuit according to the prior art.

8 is a detailed diagram of a spare wordline driver 12 in accordance with the present invention.

9 is an operation timing diagram of a row fault recovery circuit according to the present invention.

10 is an example diagram showing dual defect recovery by operation of a row defect recovery circuit according to the present invention.

Hereinafter, a row defect recovery circuit of a semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. Like reference numerals in the accompanying drawings indicate elements having the same configuration and function as much as possible. In the following description, the detailed items for such configurations are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, features and functions of well-known semiconductor basic devices are not described in detail in order not to obscure the present invention.

First, a technical gist of the present invention will be described. A row defect recovery circuit for performing row-by-row repairs may be configured as the redundancy row decoder 9 of FIG. 3 and the normal word line disable unit 10 of FIG. 4. The driver 12 is not configured as shown in FIG. 6 but configured as shown in FIG. 8 so that only one selected spare word line is activated even if at least two or more row fault recovery circuits respond to the same address. In other words, the internal structure of the spare word line driver 12 in the defect recovery circuit is simplified as shown in FIG. As a result, the salvaged chips will contribute to higher yields and lower the cost of the product.

8, a spare word line driver 12 according to the present invention is shown. This configuration has the carpet fuse F1, unlike the configuration of FIG. Here, the fuse F1 is made to the manufacture of carpet in a conventional polysilicon is blown by a laser. When spare word line SWLi is enabled, fuse 29 of transistor N3 in FIG. 3 is trimmed and the redundancy signal REDi is applied as " high ". Accordingly, the spare word line SWLi driving NMOS transistor NM1 of FIG. 8, which inputs the redundancy signal REDi as a gate, is turned on and discharges the potential of the node 35a-1 to the ground. As a result, the output of the inverter I1 becomes "high" and is output as the spare word line enable signal SWEi. However, if the spare cell present in the corresponding spare word line is defective, the fuse F1 in Fig. 8 is laser cut. Accordingly, even when the signal REDi is applied as high, the spare word line enable signal SWEi is output as low. Instead, programming the fuse in another redundant row decoder 9 configured as shown in FIG. 3 in response to a fault address makes the output of another spare wordline driver 12 "high" to enable only one adjacent spare wordline. This is shown in the timing diagram of FIG. 9. Referring to FIG. 9, it can be seen that only one selected spare word line is activated even in response to the same address. In this case, SWL0 is disabled and SWL1 is enabled.

10 shows that the dual defect recovery is performed by the operation of the row defect recovery circuit according to the present invention. The normal memory cell array 1 is disposed on the left side and the spare memory cell array 2 is disposed on the right side based on the line L3. For example, when the normal memory cell NMC0 in the first row is defective, the operation flow M1 is performed by the redundancy scheme and replaced with the spare memory cell SMC0. However, if the spare memory cell SMC0 is defective, it is changed back to the spare memory cell SMC1 on the line L6. This is by operation flow M2. M2 is performed after the fuse blowing of FIG. 8 is performed.

As described above, the present invention is a semiconductor memory device having a row defect recovery circuit for performing row-by-row repair, comprising: a plurality of row defect recovery circuits having a fuse fuseable in a spare word line driver, Even if the row fault recovery circuit responds to the same address, only one selected spare word line can be activated so that more than one fault recovery can be performed.

Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. . For example, it will be apparent that the configuration in the spare word line can be varied as well as the configuration of the defect recovery circuit can be changed as the case allows.

As described above, according to the present invention, even when the replaced redundancy cell is defective, only one spare word line is activated for the same bit line, thereby performing defect recovery to another redundancy cell.

Claims (3)

A semiconductor memory device having a row defect recovery circuit for performing row-by-row repair, A plurality of redundancy row decoders having a plurality of fuses for programming the addresses of the defective memory cells and generating redundancy signals in response to input of the row addresses of the defective memory cells; A plurality of spares having a fused fuse and connected to an output of the redundancy row decoder, enabling a spare wordline for accessing a spare memory cell in response to activation of the redundancy signal and disabling by the carpet of the fuse A row having a wordline driver, wherein the spare wordline is operated by an unfused spare wordline driver, even if at least two row decoders generate a redundancy signal in response to the same defective address. A semiconductor memory device having a fault recovery circuit. 2. The spare word line driver of claim 1, wherein the spare word line driver connects the internal node according to a logic state of a control signal connected to a source-drain channel between a power supply voltage and an internal node and delayed activated by activation of a row address strobe signal. A transistor precharged to a power supply voltage level, a programming fuse and an enMOS transistor connected in series between the internal node and ground, and an inverter for enabling a spare word line by reversing a pulldown voltage of the internal node. And lowering the voltage level of the internal node in response to a redundancy signal, and disabling the spare wordline driver by the fuse of the fuse. The device of claim 2, wherein the fuse is formed of polysilicon material.