KR100733215B1 - Row repair circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low repair circuit of a semiconductor memory device, and to improve the low access time by generating a repair address in synchronization with an external command before a clock rises, and to simplify logic using a self delay modeling circuit. do. To this end, the low repair circuit of the semiconductor memory device includes a low repair address strobe generator that generates a repair address strobe signal and a normal address strobe signal in synchronization with external commands before an internal clock rises, and a low address input from an external device. A low repair address generator that receives a repair address strobe signal and a normal address strobe signal to generate a normal address and a repair address, and outputs a low repair fuse signal corresponding to the match when the repair address is input and matches the address to be repaired. A plurality of row repair fuses, an address set fuse box that outputs a normal block enable signal when a row repair fuse signal corresponding to a match is input from the plurality of row repair fuses, and a normal address strobe signal A self-delay modeling circuit that receives a delay and outputs a block driving signal, a block for selecting a block to receive and output an output signal of a low repair address generator, an output signal of a self-delay modeling circuit, and an output signal of an address set fuse box. A selection circuit is provided.

Description

ROW REPAIR CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

1 is a circuit diagram showing a conventional low repair address strobe generator,

2 is a circuit diagram showing a conventional delay circuit;

3 is a diagram illustrating a conventional low repair address generation timing;

4 is a block diagram showing a low repair path according to the present invention;

5 is a circuit diagram illustrating a low repair address strobe generator shown in FIG. 4;

6 is a circuit diagram illustrating a row repair address generator illustrated in FIG. 4;

FIG. 7 is a circuit diagram illustrating a row repair fuse unit for one address shown in FIG. 4;

8 is a circuit diagram illustrating an address set fuse box shown in FIG. 4;

9 is a circuit diagram illustrating a self delay modeling circuit shown in FIG. 4;

10 is a diagram illustrating a timing for generating a repair address according to the present invention.

<Description of Symbols for Major Parts of Drawings>

100, 500: Roo Repair Address Strobe Generator                 

200, 600: Roo repair address generator 700: Roo repair fuse unit

800: address set fuse box 900: self-delay modeling circuit

1000: block selection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low repair circuit of a semiconductor memory device, and in particular, to separate a normal address path and a repair address path to improve a low access time, and to simplify logic by using a self-modeling delay circuit corresponding to the repair address path. The present invention relates to a low repair circuit of a semiconductor memory device.

In general, in a semiconductor memory device, when a memory cell is checked as defective, the repair is to replace the defective cell with a redundancy cell prepared in advance and use the chip without discarding the chip. These repairs include row repairs to replace wordlines and column repairs to replace columns. In order to perform such repair, an address of a bad cell is stored, and when this address is input, a redundancy cell is selected instead of the bad cell.

Therefore, if any one address is input, if this is the address of a bad cell, a time and a circuit for enabling a redundancy cell to perform a repair are required. This repair time has been a cause for increasing the time for accessing the cell.

As described above, the reason why the time for accessing the cell is increased is to generate a low repair address strobe signal in synchronization with the internal clock.

In addition, since the low repair address strobe signal is generated in synchronization with the internal clock, the time for enabling the block driving signal is long, and a large delay circuit is required.

Hereinafter, the conventional problem will be described in more detail with reference to the accompanying drawings.

1 shows a conventional low repair address strobe generator 100. The low repair address strobe generator 100 includes a low active command (CST, CASB, RAST, WEB) and an external bank address (BS1K, BS0K). Is inputted, it shows a circuit diagram for generating a row repair address strobe signal (ACTI, XRAEBI) in synchronization with the internal clock (CLK).

The row repair address strobe generator 100 is enabled by receiving a row active command (CS = LOW, RAS = LOW, CAS = HIGH, WEB = LOW) and a bank address (BS0K, BS1K). Among the names of the ROH active commands (RAST, CASB, CST, WEB), T means high when the input pin is low, and B means high when the input pin is high.

First, when high is output from the logic circuit 110 that receives and logically combines these external commands (RAST, CASB, CST, WEB, BS0K, BS1K), node 1 is set high. Next, when the internal clock CLK goes from low to high, the tri-state inverter I2 is enabled and stored in the latch circuits I3 and I4, and then output. Of the signals output from the latch circuits I3 and I4, the signal ACTI output through the inverters I5 and I7 is used to form a normal address, and the signal XRAEBI output through the inverter I6 is output. Is used to make repair dress.

That is, the row repair address strobe generator 100 drives a row repair strobe signal when an external command (RAST, CASB, CST, WEB, BS0K, BS1K) is input in synchronization with an internal clock CLK to set a row repair address. As a result, there is a disadvantage in that the time delay is increased by the time synchronized with the internal clock, thereby increasing the time for accessing the cell.

2 is a circuit diagram illustrating a conventional delay circuit 200.

The delay circuit 200 shown in FIG. 2 is connected to delay units 210 and 220 for receiving and delaying the normal address strobe signal ACTI and to the delay units 210 and 230, and It is composed of a switching unit 230 for adjusting the output value.

The delay circuit 200 shown in FIG. 2 receives the normal address strobe signal ACTI generated by the row repair address strobe generator 100 and outputs a block driving signal XEDI. The output block driving signal XEDI is input to a block selection circuit (described later). When the block selection signal XEDI becomes high, the block is selected directly by the normal address, and thus the block selection signal XEDI. The time that is enabled requires a large delay circuit since it must wait until the address detects whether it is an address to be repaired via a fuse.

3 shows a conventional low repair address generation timing.

Referring to FIG. 3, since the low repair address strobe signals ACTI and XRACEI are generated after the external commands RAST, CASB, CST, WEB, BS0K, BS1K are input in synchronization with the internal clock CLK, the repair address BXARI. It can be seen that the generation time of h) is delayed by the time t1.

Accordingly, the present invention has been made in view of the above-described problems, and an object thereof is to improve a row access time by generating a repair address in synchronization with an external command before the internal clock rises.

Another object of the present invention is to simplify the logic using a self delay modeling circuit.

The low repair circuit of the semiconductor memory device of the present invention for achieving the above object includes a low repair address strobe generator for generating a repair address strobe signal and a normal address strobe signal in synchronization with external commands before an internal clock rises; When the external address and repair address strobe signal and the normal address strobe signal are input from the external repair address generator to generate the normal address and the repair address, and the repair address is inputted and matches the address to be repaired, the correspondence is matched. A plurality of row repair fuse sections for outputting a row repair fuse signal, an address set fuse box for outputting a normal block enable signal when a row repair fuse signal corresponding to a match is input from the plurality of row repair fuse sections; The self-delay modeling circuit receives the delayed multi-address strobe signal and outputs the block driving signal, the output signal of the low repair address generator, the output signal of the self-delay modeling circuit, and the output signal of the address set fuse box. A block selecting circuit for selecting a block is provided.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

4 illustrates a low repair circuit of a semiconductor memory device for improving a low access time.

In FIG. 4, when the plurality of external commands RAST, CASB, CST, WEB, BS0K, and BS1K transition to a low level before the internal clock rises, the low repair address strobe generator 500 performs the low repair address strobe signal ACTI, XRAEBIs are generated, and the low repair address generator 600 receives the low address BXA and the low repair address strobe signals ACTI and XRAEBI that are externally input, and the normal addresses BXATI and BXABI and repair addresses. BXARI), and the 11 low repair fuse unit 700 receives the repair address BXARI and outputs a low level low repair fuse signal when it matches the address to be repaired by cutting the fuse. The fuse box 800 may output the normal block enable signal HIT when the low repair fuse signals HIT2-HIT11 and HIT14 of the low repair fuse unit 700 are all low level. The self delay modeling circuit 900 receives and delays the normal address strobe signal ACTI until the normal block enable signal HIT is generated using the low repair address strobe signal. XEDI), and the block selection circuit 1000 outputs the normal addresses BXATI and BXABI of the row repair address generator 600, the block driving signal XEDI of the self delay modeling circuit 900, and the address set. The normal block is disabled by receiving the block enable signal HIT of the fuse box 800 and driving the repair block.

FIG. 5 is a circuit diagram illustrating the row repair address strobe generator 500 shown in FIG. 4.

The row repair address strobe generator 500 shown in FIG. 5 receives a logic combination by receiving an inverter I11 which receives an internal clock CLK and inverts it, and an external command CST, CASB, RAST, WEB, BS0K, BS1K. A logic circuit unit 510, a three-state inverter I12 that receives and stores an output signal of the logic circuit unit, an output signal of the three-state inverter I12, the internal clock CLK, and the inverter I11. A latch circuit unit 520 for receiving and latching an output signal of an output signal) and an output buffer for outputting a normal address strobe signal ACTI by logically combining the output signals of the internal clock CLK and the latch circuit unit 520. And an inverter I15 for receiving the inverted output signal of the latch circuit unit 520 and inverting it to output the repair address strobe signal XRAEBI.

Here, the logic circuit unit 510 may include a NAND gate ND11 that receives and logically combines the external commands CST and CASB, and a NAND gate ND12 that receives and logically combines the external commands RAST and WEB. And a NAND gate ND13 that receives and logically combines the external commands BS0K and BS1K, and a NOR gate NR11 that receives and logically combines output signals of the NAND gates ND11, ND12, and ND13. The output buffer unit 530 receives the output signals of the internal clock CLK and the latch circuit unit 520 and logically combines the NAND gate ND14 and the output signal of the NAND gate ND14. It consists of the inverter I16 which inverts.

Hereinafter, the operation of the row repair address strobe generator 500 according to the present invention will be described.

The low repair address strobe generator 500 shown in FIG. 5 generates the repair address strobe signal XRAEBI in synchronization with the external commands CST, CASB, RAST, WEB, BS0K, BS1K before the internal clock CLK rises. (Path D).

In more detail, the row repair address strobe generator 500 has a node 2 high when all the row active commands CST, CASB, BS0K, BS1K, RAST, and WEB are input high, and the internal clock CLK rises. Node 4 goes high before leaving the tri-state inverter I12 enabled. Therefore, the state of node 2 is transmitted to node 3 before the internal clock CKL rises, and the repair address strobe signal XRAEBI is transmitted to the external commands CST, CASB, RAST, WEB, BS0K, BS1K before the internal clock rises. Will be generated in synchronization with Subsequently, when the internal clock CLK is raised, the NAND gate ND14 is opened to transmit the normal address strobe signal ACTI. At this time, the three-state inverter I12 separates the pin and node 3 of the external command (CST, CASB, BS0K, BS1K, RAST, WEB) so that the external pin is not affected internally even if it moves. In addition, the tri-state inverter I12 stores the state of the node 3 and keeps storing the loo active state until the next internal clock rises even when disconnected from the outside.

As described above, since the repair address strobe signal XRAEBI is activated faster than the normal address strobe signal ACTI, the repair address BXARI input to the row repair fuse 700 shown in FIG. 4 is generated faster (BXAR2). -10, BXAR14), it can be seen that the row access time of the entire circuit is improved (only BXAR2-10 and BXAR14 are used in the circuit design).

FIG. 6 is a circuit diagram illustrating the row repair address generator 600 shown in FIG. 4.

The low repair address generator 600 shown in FIG. 6 uses the low repair address strobe signals ACTI and XRAEBI generated by the low repair address strobe generator 500 to generate the normal addresses BXATI and BXABI and the repair address BXARI. Circuit for making

The low repair address generator 600 shown in FIG. 6 includes an inverter I17 for receiving and inverting a normal address strobe signal ACTI, an inverter I18 for receiving and inverting an output signal of the inverter, and a low address BXA. ), A three-state inverter I19 for receiving and storing the output signal of the inverter I17 and the output signal of the inverter I18, the output signal of the three-state inverter I19, and the output signal of the inverter I17. An output signal and a latch circuit unit 610 for receiving and latching an output signal of the inverter I18, an output signal of the latch circuit 610, an output signal of the inverter I17, and a repair address strobe signal XRAEBI ) Is configured as an output buffer unit 620 for outputting a logical combination.

Here, the output buffer unit 620 receives the output signal of the inverter I17 and the output signal of the latch circuit unit, and logically inverts the NOR gate NR12 and the output signal of the NOR gate NR12 to normalize it. Inverter I22 for outputting address BXATI, NOR gate NR13 for receiving and logically combining the signal of node 5 and the output signal of inverter I17, and inverting the output signal of NOR gate NR13 The inverter I23 outputting the normal address BXABI, the NOR gate NR14 for receiving and logically combining the repair address strobe signal XRAEBI and the output signal of the latch circuit unit 610, and the NOR gate ( Inverter I24 outputs the repair address BXARI by inverting the output signal of NR14.

Hereinafter, the operation of the row repair address generator 600 according to the present invention will be described.

The low address BXA input from the external address pin arrives only to node 5 before the normal address strobe signal ACTI is enabled. When the normal address strobe signal ACTI is enabled, the low address BXA is disconnected from the external address pin. The address of the node 5 is latched in the latch circuit 610 and output.

The repair addresses BXAR2 to 11 and BXAR14 generated by the row repair address generator 600 are input to the eleven row repair fuse circuits 700 shown in Fig. 4, respectively.

7 illustrates a row repair fuse circuit 700 for one address in accordance with the present invention.

The low repair fuse circuit 700 illustrated in FIG. 7 includes an NMOS transistor having a fuse F1 connected to an ambient voltage Vperi and a fuse pulse signal FSS as a gate and a drain connected to the fuse F1. N1 and NMOS transistors N2 and N3 connected to the peripheral voltage Vperi and connected in series between the NMOS transistor N1 and the ground voltage, and the fuse F1 and the NMOS transistor N1. The NMOS transistor N4 connected between the common node and the ground voltage, the inverter I25 connected to the common node of the fuse F1 and the NMOS transistor N1, and the output signal of the inverter are inverted. A transfer gate T1 connected to an inverter I26 and a repair address BXARI to receive and transfer an output signal of the inverter I25 and an output signal of the inverter I26, and a repair address of the repair address BXARI. Inverter (I27) for receiving the output signal and inverting the phase, Is connected to the inverter (I27) and is composed of a transfer gate (T2) to transfer receives the output signal of the output signal and the inverter (I26) of said inverter (I25).

The low repair fuse circuit 700 configured as described above receives the repair addresses BXAR2-11 and BXAR14 and the fuse pulse signal FSS, and the repair address is cut and cut by the fuse F1. If R1 matches the address to be repaired, the low repair fuse signals HIT2-11 and HIT14 are output low.

8 is a circuit diagram illustrating an address set fuse box 800 according to the present invention.

The address set fuse box 800 illustrated in FIG. 8 includes a first NOR gate NR15 for receiving and logically combining the first and second low repair fuse signals HIT2 and HIT3 output from the low repair fuse circuit 700. And a second NOR gate NR16 for receiving and logically combining the third, fourth, and fifth row repair fuse signals HIT4, HIT5, and HIT6 output from the row repair fuse circuit 700; A third NOR gate NR17 for receiving and logically combining the sixth, seventh, and eighth low repair fuse signals HIT7, HIT8, and HIT9 output from the low repair fuse circuit 700, and the low repair A fourth NOR gate NR18 for receiving and logically combining the ninth, tenth, and eleventh row repair fuse signals HIT10, HIT11, and HIT14 output from the fuse circuit 700, and the first and second gates. NAND gates that receive and logically combine the output signals of the third, third, and fourth NOR gates NR15, NR16, NR17, and NR18. ND15, a NOR gate NR19 for receiving and logically combining an output signal of the NAND gate ND15 and a test mode signal (TWRNI) for testing a row repair, and the NOR gate ( And an inverter I28 for inverting the output signal of NR19 and outputting the normal block enable signal HIT.

In this figure, when the eleven low repair fuse signals HIT2-11 and HIT14 are all low, the output signal HIT of the address set fuse box is low and the normal block in the block selection circuit 1000 shown in FIG. Is disabled and the repair block is driven.

9 shows a self delay modeling circuit 900 in accordance with the present invention.

The self-delay modeling circuit 900 includes a plurality of inverters I29, I30, I31, and I32 for receiving and inverting a normal address strobe signal ACTI, and switches SW1 and SW2 connected to an output of the inverter I30. And a logic combination of receiving the signal from the switch SW1, the transfer gate T3 for transmitting the output signal of the inverter I32, the output signal HIT of the transfer gate T3, and the switch SW1. The NAND gate NR20, the NAND gate ND16 for receiving and logically combining the output signal of the NOR gate NR20 and the peripheral voltage Vperi, the output signal of the NAND gate ND16, and the switch SW2. A NOR gate NR21 for receiving and logically combining a signal from a signal, an inverter I33 for inverting an output signal of the NOR gate NR21, an output signal of the inverter I33, and a peripheral voltage Vperi are inputted. NAND gate ND17 to receive and logically combine, and output of the NAND gate ND17 Inverter I34 for inverting the signal, NOR gate NR22 for receiving and logically combining the output signal of the inverter I34 and the signal from the switch SW3, and the output signal of the NOR gate NR22. It consists of a plurality of inverters I35 and I36 which invert and output the block drive signal XEDI.

The time for driving the block drive signal XEDI output from the self delay modeling circuit 900 shown in FIG. 9 is that the repair address BXARI goes to the fuse to generate the output signal HIT of the address set fuse box 800. You must wait before. If it is activated before then, the normal block is activated, causing a malfunction. Therefore, this delay circuit 900 requires accurate timing.

Next, the operation of the self delay modeling circuit 900 will be described.

The self delay modeling circuit 900 delays the normal address strobe signal ACTI until the repair address strobe signal XRAEBI generates the normal block enable signal HIT.

The self-delay modeling circuit 900 has LDRBXBT modeling in which a normal address strobe signal ACTI is input and a repair path strobe signal XRAEBI is modeled to a fuse of a low repair fuse part. This modeling uses a large number of fuses and therefore has a very long fuse box. Therefore, you must model the address path that drives the farthest fuse. The address entered into the fuse is sent low if the external address matches the fuse address depending on whether the fuse is cut or not. The logic modeling this is the LDRFSCMP modeling section.

If all of the single addresses are low, then the normal path must be disabled because all external addresses match the addresses to be repaired. This path is a path (LDRFSS modeling) that causes the output signal HIT of the address set fuse box to be low when it matches the address. If the output signal HIT of the address set fuse box is low, the block drive signal XEDI on the normal path side is low. It consists of LDRXDE modeling to disable).

10 shows timing of generating a ROH repair address according to the present invention.

Referring to FIG. 10, since the repair address BXARI is generated in synchronization with the external commands CST, CASB, BS0K, BS1K, RAST, and WEB (it takes time t2 to generate the repair address), It can be seen that the generation time of the repair address is shortened by the time, thereby improving the row access time of the entire circuit.

As described above, since the repair address strobe signal is generated in synchronism with an external command before the internal clock rises, the row repair address setup time is increased, thereby improving the row access time.

In addition, the use of self-delay modeling circuitry can eliminate unnecessary option circuitry and simplify logic.                     

In addition, the delay change of the repair path circuit due to the power supply voltage level, the temperature, and the process (PMOS, NMOS threshold voltage, saturation current, etc.) moves as it is by using the self delay modeling circuit described above. , NOR gate, etc.) can be adjusted automatically.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, and such modifications should be regarded as falling within the scope of the following claims. something to do.

Claims (7)

In the low repair circuit of a semiconductor memory device for improving the low access time, A low repair address strobe generator for generating a repair address strobe signal and a normal address strobe signal in synchronization with external commands before the internal clock rises; A low repair address generator configured to receive a low address input from the outside, the repair address strobe signal, and the normal address strobe signal to generate a normal address and a repair address; A plurality of row repair fuses configured to receive a repair address and output a row repair fuse signal corresponding to the matching when the repair address is received; An address set fuse box configured to output a normal block enable signal when the row repair fuse signal corresponding to the match is input from the plurality of row repair fuses; A self delay modeling circuit configured to receive the delay of the normal address strobe signal and output a block driving signal; And And a block selection circuit configured to select a block to be driven by receiving an output signal of the row repair address generator, an output signal of the self delay modeling circuit, and an output signal of the address set fuse box. Roo repair circuit. The method of claim 1, The row repair address strobe generator, A logic circuit unit for receiving and logically combining the external commands; A first reversing device receiving the internal clock and inverting the internal clock; A three-state inverter that receives and stores an output signal of the logic circuit unit, the internal clock, and an output signal of the first inverting device; A latch circuit unit configured to receive and latch an output signal of the three-state inverter, the internal clock, and an output signal of the first inverting device; An output buffer unit configured to receive an output signal of the internal clock and the latch circuit unit and to logically combine the output signal to output the normal address strobe signal; And a second inverting element configured to receive the inverted output signal of the latch circuit unit and invert the output signal to output the repair address strobe signal. The method of claim 2, The logic circuit portion, A plurality of first logic elements for receiving and logically combining the external commands; And a second logic element configured to receive and logically output the output signals of the plurality of logic elements. The method of claim 2, The output buffer unit, And a third logic element configured to receive and logically combine the clock signal and the output signal of the latch circuit unit, and a third inversion element configured to receive and invert the output signal of the third logic element. Repair circuit. The method of claim 1, The row repair address generator, A first inverting element which receives the normal address strobe signal and inverts it; A second inverting element which receives the output signal of the first inverting element and inverts it; A three-state inverter for receiving and storing the output signal of the first inverting element, the output signal of the second inverting element, and the row address; A latch circuit unit configured to receive and latch an output signal of the three-state inverter, an output signal of the first inverting element, and an output signal of the second inverting element; And a output buffer unit configured to receive the output signal of the latch circuit unit, the output signal of the first inverting element, and a repair address strobe signal and logically combine the output signals to output the normal address and the repair address. Repair circuit. The method of claim 5, The output buffer unit includes a first logic element for receiving and logically combining the output signal of the first inverting element and the output signal of the latch circuit; A third inversion element for inverting an output signal of the first logic element to output a normal address; A second logic element configured to receive and logically combine an output signal of the first inverting element and an output signal of the three-state inverter; A fourth inversion element for inverting the output signal of the second logic element to output the normal address; A third logic element configured to receive and logically combine an output signal of the latch circuit and the repair address strobe signal; And a fifth inverting element which inverts the output signal of the third logic element to output the repair address. The method of claim 1, The self delay modeling circuit, Means for modeling a path for the repair address strobe signal to a fuse; Means for modeling a path that emits a low level when an external address coincides with a fuse address according to whether a fuse is cut or not; Means for modeling a path that makes the output signal of the address set fuse box low level if the external address matches the address to be repaired; Means for modeling a path for disabling the block driving signal on the normal path side when the output signal of the address set fuse box is low; And receiving and delaying the normal address strobe signal until the normal block enable signal is generated using the repair address strobe signal.

Images