KR19990011067A - Redundancy circuit and semiconductor device having same - Google Patents

Abstract

Disclosed are a redundancy circuit in which the number of fuses used is small and the current consumption is reduced, and a semiconductor device having the same. The redundancy circuit includes a repair address determiner and a redundancy enable signal generator. The repair address determination unit may latch a repair address in advance and compare an input address with the latched repair address to determine whether the input address is the same as the repair address. The redundancy enable signal generator generates a redundancy enable signal in response to output signals of the repair address determiner. The semiconductor device including the redundancy circuit further includes an address blocking unit in addition to the repair address determining unit and the redundancy enable signal generating unit. The address blocking unit blocks the input address from being transferred to the address input buffer when the input address is the same as the repair address.

Description

Redundancy circuit and semiconductor device having same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an improved redundancy circuit and a semiconductor device having the same.

Semiconductor devices, in particular semiconductor memory devices, have redundancy circuits to replace defects in normal memory cells. The redundancy circuit generally includes redundancy memory cells and redundancy fuse boxes. The redundancy memory cells are intended to be used in place of defective memory cells. The redundancy fuse boxes are configured to recognize when an address of defective memory cells is input and to generate a redundancy enable signal for driving the redundancy memory cells.

1 is a circuit diagram of a redundancy enable signal generator in a conventional redundancy circuit.

Referring to FIG. 1, the conventional redundancy enable signal generator includes a discharge unit 101, a precharge unit 103, and a buffer unit 105.

The discharge unit 101 discharges the output node ND1 in response to the input addresses A0, A0B, A1, A1B, ..., Ai, AiB. The discharge unit 101 is an address storage block for storing a repair address (or also referred to as a defective address) in advance, that is, a redundant fuse box, and includes the input addresses A0, A0B, A1, A1B, ..., Ai, AiB) for comparing with the previously stored repair address. Here, the repair address means an address of a defective memory cell. A0, A1, ..., Ai represent each bit of the input address, and A0B, A1B, ... AiB represent each bit of the complementary address for the input address. The precharge unit 103 precharges the output node ND1 in response to a control signal PCLKD. The buffer unit 105 generates a redundancy enable signal RENi by buffering a signal output from the output node ND1.

The discharge unit 101 includes a plurality of fuses F0, F0B,..., Fi, and FiB each of which one end is connected to the output node ND1, and the other end of the fuse corresponding to each drain. Are connected and each bit (A0, A0B, A1, A1B, ..., Ai, AiB) of the input address or complementary address corresponding to each gate is connected and a ground voltage VSS is applied to each source. A plurality of NMOS transistors N0, N0B, ..., Ni, NiB are included. In addition, the precharge unit 103 includes a PMOS transistor P1 having a power supply voltage VDD applied to a source, a control signal PCLKD applied to a gate, and a drain connected to the output node ND1. An inverter I1 for inverting the voltage of the output node ND1, a power supply voltage VDD is applied to a source, an output signal of the inverter I1 is applied to a gate, and a drain is supplied to the output node ND1. The PMOS transistor P2 connected to is comprised. The buffer unit 105 includes an even number of inverters I2 and I3 connected in series.

The operation of the discharge unit 101, which is a repair address storage block, will be briefly described as follows. A repair address is recorded by cutting a corresponding fuse among the plurality of fuses F0, F0B, ..., Fi, and FiB in advance. Accordingly, the discharge unit 101 compares the input addresses A0, A0B, A1, A1B, ..., Ai, AiB sequentially sequentially input with the stored repair address to determine whether the discharge address is the same as the repair address. do. That is, when the input address is not the same as the repair address, at least one of the plurality of NMOS transistors N0, N0B, ..., Ni, NiB is turned on so that the voltage of the output node ND1 is turned on. The level is discharged to a logic low state. Accordingly, the redundancy enable signal RENi becomes logic low so that no redundant memory cells are accessed. On the other hand, when the input address is the same as the repair address, the voltage level of the output node ND1 is not discharged by the cut fuse to maintain a logic high state. Accordingly, the redundancy enable signal RENi becomes logic high so that redundancy memory cells are accessed. That is, a redundant memory cell that is accessed instead of a defective memory cell is used.

However, since the redundancy enable signal generator of the conventional redundancy circuit has two fuses for each bit of an address, the total number of fuses increases, resulting in a large chip size. There is a disadvantage of increasing the current.

It is therefore an object of the present invention to provide a redundancy circuit of a semiconductor device in which the number of fuses used is small and the current consumption is reduced.

Another object of the present invention is to provide a semiconductor device which uses the redundancy circuit and reduces current consumption during redundancy operation.

1 is a circuit diagram of a redundancy enable signal generator in a conventional redundancy circuit;

2 is a circuit diagram of a redundancy circuit according to an embodiment of the present invention.

3 is a view including an address blocking unit according to an exemplary embodiment of the present invention.

A redundancy circuit according to the present invention for achieving the above object comprises: a repair address determination unit which latches a repair address in advance and compares an input address with the latched repair address to determine whether the input address is the same as the repair address; And a redundancy enable signal generator for generating a redundancy enable signal in response to output signals of the repair address determination unit.

The repair address determination unit includes a latch unit for latching the repair address, a comparison unit for generating output signals of the repair address determination unit by comparing the output signal and the input address of the latch unit, and a control unit for controlling the latch unit. do. The redundancy enable signal generator may include: a discharge unit configured to discharge an output node in response to an output signal and a control signal of the repair address determination unit; a precharge unit configured to precharge the output node in response to the control signal; And a controller for generating the control signal by inputting an address strobe signal and a clock signal, and a buffer unit for buffering a signal output from the output node to generate the redundancy enable signal.

In addition, the semiconductor device according to the present invention for achieving the above another object is a semiconductor device having a redundancy repair structure, latching a repair address in advance, and compares the input address and the latched repair address, the input address is A repair address determining unit determining whether the repair address is the same as a repair address, a redundancy enable signal generating unit generating a redundancy enable signal in response to output signals of the repair address determining unit, and when the input address is the same as the repair address And an address blocking unit for blocking the input address from being transferred to the address input buffer.

The repair address determination unit includes a latch unit for latching the repair address, a comparison unit for generating output signals of the repair address determination unit by comparing the output signal and the input address of the latch unit, and a control unit for controlling the latch unit. do. The redundancy enable signal generator may include: a discharge unit configured to discharge an output node in response to an output signal and a control signal of the repair address determination unit; a precharge unit configured to precharge the output node in response to the control signal; And a controller for generating the control signal by inputting an address strobe signal and a clock signal, and a buffer unit for buffering a signal output from the output node to generate the redundancy enable signal. The address blocking unit may further include a transmission gate configured to transfer the input address to the address input buffer in response to the redundancy enable signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a redundancy circuit of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the redundancy circuit includes a repair address determining unit 201 and a redundancy enable signal generator 203.

The repair address determination unit 201 writes and repairs a repair address in advance, and compares the input addresses A0, A1, ..., Ai with the latched repair address to obtain the input addresses A0, A1,. It is determined whether Ai) is the same as the repair address. Here, the repair address means an address of a defective memory cell. The redundancy enable signal generator 203 generates a redundancy enable signal RENi in response to the output signals FREN0 to FRENi and PMAST of the repair address determiner 201.

The repair address determination unit 201 includes a latch unit 201a for latching the repair address, output signals O0 to Oi of the latch unit 201a, and the input addresses A0, A1, ... A comparison unit 201b for generating output signals FREN0 to FRENi of the repair address determination unit, and a column address strobe signal CASB, a clock signal CLK, and a control signal PR. The control part 201c which controls the said latch part 201a is provided.

The latch unit 201a includes fuses F01 to Fi1 and Fx having one end connected to a power supply voltage VDD, and other ends of the fuses F01 to Fi1 and Fx connected to a source and connected to a gate, respectively. PMOS transistors P01 to Pi1 and Px to which an output signal of the controller 201c is applied, and drains of the PMOS transistors P01 to Pi1 and Px are respectively connected to drains, and the control unit 201c is connected to a gate. NMOS transistors N01 to Ni1 and Nx to which an output signal is applied and a ground voltage VSS is applied to the source, and PMOS transistors P01 to P1 and Px and NMOS transistors commonly connected. And latches L0 to Li and Lx for latching signals output from the drains of N01 to Ni1 and Nx and outputting the output signals as output signals O0 to Oi and Ox of the latch unit. In this case, when a defective memory cell exists, a repair address is written by cutting a corresponding fuse among the fuses F01 to Fi1. In addition, the fuse Fx associated with the master signal PMAST is cut when a defective memory cell exists and is not cut when a defective memory cell does not exist.

The comparison unit 201b may include transfer gates T0 to Ti that transfer respective bits of the input addresses A0, A1, ..., Ai in response to the clock signal CLK, and the transfer gates. The repair address determination unit compares each bit of the input addresses A0, A1, ..., Ai transmitted through T0 to Ti with each output signal O0 to Oi of the latch unit 201a. Inverter Ix that generates the master signal PMAST by inverting the exclusive ogates XOR0 to XORi generating the output signals FREN0 to FRENi and the output signal Ox of the latch unit 201a. It is configured to include.

The control unit 201c includes an inverter I4 for inverting the column address strobe signal CASB, a NAND gate and an inverter ND1 for logically multiplying the low address strobe chain master signal PR and the output signal of the inverter I4. And a NAND gate ND2 for generating a control signal for controlling the latch unit 201a by NAND-gating the output signal and the clock signal CLK of the inverter I5.

In addition, the redundancy enable signal generator 203 discharges the output node ND2 in response to the output signals FREN0 to FRENi and PMAST and the control signal CT of the repair address determination unit. And a precharge unit 203b for precharging the output node ND2 in response to the control signal CT, and a column address strobe signal CASB and a clock signal CLK as inputs. A control unit 203c for generating a CT and a buffer unit 203d for buffering the signal output from the output node ND2 to generate the redundancy enable signal RENi.

The discharge unit 203a includes NMOS transistors to which the output node ND2 is connected to each drain and to which the output signals FREN0 to FRENi and PMAST of the repair address determiner corresponding to each gate are respectively applied. (N02 to Ni2, Nx2) and a drain connected to the sources of the NMOS transistors N02 to Ni2 and Nx2, the control signal CT is applied to a gate, and a ground voltage VSS is applied to the source. It is comprised including NMOS transistor Na.

The precharge unit 203b includes a PMOS transistor P3 having a power supply voltage VDD applied to a source, a control signal CT applied to a gate, and a drain connected to the output node ND2. An inverter I7 for inverting the voltage of the output node ND2, a power supply voltage VDD is applied to a source, an output signal of the inverter I7 is applied to a gate, and a drain is applied to the output node ND2. It includes a PMOS transistor P4 connected to it.

The control unit 203c may generate an inverter I8 for inverting the clock signal CLK, and output an output signal of the inverter I8 and the column address strobe signal CASB to generate the control signal CT. It is comprised including the generated noah gate NR1. The buffer unit 203d includes an even number of inverters I9 and I10 connected in series.

Hereinafter, a brief description of the operation of the redundancy circuit of the present invention shown in FIG. First, the fuses are cut in advance only when each bit of the repair address is logic high so that the repair address is latched to the latches L0 to Li and Lx of the latch unit 201a by the repair address determination unit 201. Thus, for example, when the fuse F01 is not disconnected, the PMOS transistor P01 is turned on and latched when the column address strobe signal CASB is logic low and the clock signal CLK is transitioned from logic low to logic high. The output signal O0 of L0 becomes logic low. When the fuse F01 is cut off, the NMOS transistor N01 is turned on by the previous state, that is, the logic low clock signal CLK, so that the output signal O0 of the latch L0 becomes logic high. The output signal O0 of the latch L0 is then compared with the input address bit A0 transmitted through the transfer gate T0 at the exclusive or gate XOR0 to generate the output signal FREN0. In the same manner, the values of the output signals O1 to Oi and Ox of the latches L1 to Li and Lx are determined according to whether the remaining fuses F11 to Fi1 and Fx are disconnected, and the signals O1 to Oi are determined. The exclusive oragates XOR1 to XORi are compared with the input address bits A1 to Ai, respectively, to generate output signals FREN1 to FRENi. The signal Ox is inverted in the inverter Ix to generate an output signal PMAST that is a master signal.

Therefore, if the input addresses A0, A1, ..., Ai are equal to the repair address, that is, the input addresses A0, A1, ..., Ai are output signals of the latches L0 to Li. If the output signals FREN0 to FRENi of the repair address determination unit 201 are all logic low and the master signal PMAST is also logic low, the redundancy enable signal is generated. The NMOS transistors N02 to Ni2 and Nx2 of the discharge unit 203a in the unit 203 are all turned off. As a result, the voltage level of the output node ND2 is not discharged, thereby maintaining a logic high state, and the redundancy enable signal RENi becomes logic high so that the redundant memory cells are accessed. That is, a redundant memory cell that is accessed instead of a defective memory cell is used.

On the other hand, if the input addresses A0, A1, ..., Ai are not the same as the repair address, i.e., the input addresses A0, A1, ..., Ai are set to If not the same as the output signals (O0 to Oi), at least one of the output signals (FREN0 to FRENi) of the repair address determination unit 201 is a logic high, the NMOS transistors of the discharge unit 203a At least one of (N02 to Ni2, Nx2) is turned on. At this time, since the NMOS transistor Na is turned on by the control signal CT, the voltage level of the output node ND2 is discharged and becomes logic low, and the redundancy enable signal RENi becomes logic low and the redundancy memory cell. Are not accessed.

3 is a diagram illustrating an address blocking unit of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, an address blocking unit 301 is connected to an input terminal of the address input buffer 303. When the input addresses A0, A1, ..., Ai are the same as the repair address, the address blocking unit 301 has the address input buffer (A0, A1, ..., Ai). 303) to block delivery.

The address blocking unit 301 stores each bit of the input addresses A0, A1, ..., Ai in response to the redundancy enable signals REN0 to RENi. It includes the transmission gates (T03 to Ti3) for transmitting to (B0 to Bi). Therefore, when the input addresses A0, A1, ..., Ai are equal to the repair address, that is, when the redundancy enable signals REN0 to RENi are activated to be logic high, the input addresses A0, A1, Ai is blocked from being transferred to the address input buffer 203.

As described above, the present invention has been limited to one embodiment, but not limited thereto. It is obvious that various modifications to the present invention can be made by those skilled in the art within the scope of the spirit of the present invention. .

Therefore, in the redundancy circuit of the semiconductor device according to the present invention, the number of fuses used is reduced to 1/2 compared to the prior art, thereby reducing chip area and reducing current consumption. In addition, the address blocking unit according to the present invention can reduce the current consumption by stopping the operation of the address input buffer and the rear end by blocking the transfer of the input address to the address input buffer when the input address is the same as the repair address. .

Claims (22)

A repair address determining unit which latches a repair address in advance and compares an input address with the latched repair address to determine whether the input address is the same as the repair address; And a redundancy enable signal generation unit configured to generate a redundancy enable signal in response to output signals of the repair address determination unit. The display device of claim 1, wherein the repair address determination unit comprises: a latch unit for latching the repair address; a comparison unit configured to generate output signals of the repair address determination unit by comparing an output signal of the latch unit and the input address; A redundancy circuit of a semiconductor device, comprising a control unit for controlling a unit. The PMOS transistor of claim 2, wherein the latch unit comprises: a fuse having one end connected to a power supply voltage; a PMOS transistor connected at a second end of the fuse to a source; and an output signal of the controller applied to a gate; The latch of the NMOS transistor connected to the drain of the transistor, the output signal of the controller is applied to the gate, and the ground voltage is applied to the source, and the signal output from the drains of the PMOS and NMOS transistors connected in common. A redundancy circuit of a semiconductor device, comprising: a latch for outputting as a negative output signal. 3. The repairing unit of claim 2, wherein the comparison unit compares a transmission gate transferring the input address in response to a clock signal with an output signal of the latch unit by comparing the input address transmitted through the transmission gate with an output signal of the latch unit. A redundancy circuit of a semiconductor device, comprising: an exclusive ogate for generating a signal. 3. The control circuit according to claim 2, wherein the control unit comprises: an inverter for inverting a column address strobe signal, an AND gate for ANDing a low address strobe chain master signal, and an output signal of the inverter, and an output signal and a clock signal of the AND gate. And a NAND gate for generating a control signal for controlling the latch unit by NAND gating. The redundancy enable signal generator of claim 1, wherein the redundancy enable signal generator comprises: a discharge unit configured to discharge an output node in response to an output signal and a control signal of the repair address determination unit; and a precharge configured to precharge the output node in response to the control signal. And a charging unit, a control unit for generating the control signal by inputting a column address strobe signal and a clock signal, and a buffer unit for buffering a signal output from the output node to generate the redundancy enable signal. Redundancy circuit of semiconductor device. The NMOS transistor of claim 6, wherein the discharge unit includes a plurality of NMOS transistors to which the output node is connected to each drain, and an output signal of the repair address determination unit corresponding to each gate is applied, and the drain is the NMOS transistor. And an NMOS transistor connected to the sources of the transistors, the control signal applied to a gate, and a ground voltage applied to the source. The semiconductor device of claim 6, wherein the precharge unit is configured to invert a voltage of the first PMOS transistor having a power supply voltage applied to a source, a control signal applied to a gate, and a drain connected to the output node. And an inverter and a second PMOS transistor to which a power supply voltage is applied to a source, an output signal of the inverter is applied to a gate, and a drain thereof is connected to the output node. The semiconductor device of claim 6, wherein the controller comprises an inverter for inverting the clock signal, and a nod gate for generating the control signal by generating an output signal of the inverter and the column address strobe signal. Redundancy circuit of the device. The redundancy circuit of claim 6, wherein the buffer unit comprises an even number of inverters connected in series. In a semiconductor device including a redundancy repair structure, A repair address determination unit which latches a repair address in advance and compares an input address with the latched repair address to determine whether the input address is the same as the repair address; A redundancy enable signal generator for generating a redundancy enable signal in response to an output signal of the repair address determination unit; And And an address blocking unit for blocking the input address from being transferred to the address input buffer when the input address is the same as the repair address. 12. The apparatus of claim 11, wherein the repair address determination unit comprises: a latch unit for latching the repair address; a comparison unit for comparing output signals of the latch unit with the input address to generate output signals of the repair address determination unit; And a control unit for controlling the unit. The PMOS transistor of claim 12, wherein the latch unit comprises: a fuse having one end connected to a power supply voltage; a PMOS transistor having a second end connected to a source; and an output signal of the control unit applied to a gate; The latch of the NMOS transistor connected to the drain of the transistor, the output signal of the controller is applied to the gate, and the ground voltage is applied to the source, and the signal output from the drains of the PMOS and NMOS transistors connected in common. And a latch for outputting as a negative output signal. The repairing unit of claim 12, wherein the comparing unit compares a transmission gate transferring the input address in response to a clock signal, an output signal of the latch unit by comparing the input address transmitted through the transmission gate with an output signal of the latch unit. A semiconductor device comprising an exclusive orifice for generating a signal. 13. The apparatus of claim 12, wherein the control unit comprises: an inverter for inverting a column address strobe signal, an AND gate for ANDing a low address strobe chain master signal, and an output signal of the inverter, and an output signal and a clock signal of the AND gate. And a NAND gate for generating a control signal for controlling the latch unit by NAND gating. 12. The apparatus of claim 11, wherein the redundancy enable signal generator comprises: a discharge unit configured to discharge an output node in response to an output signal and a control signal of the repair address determination unit; and a precharge configured to precharge the output node in response to the control signal. And a charging unit, a control unit for generating the control signal by inputting a column address strobe signal and a clock signal, and a buffer unit for buffering a signal output from the output node to generate the redundancy enable signal. Semiconductor device. 17. The NMOS transistor of claim 16, wherein the discharge unit comprises: a plurality of NMOS transistors to which the output node is connected to each drain, and an output signal of the repair address determination unit corresponding to each gate is applied; And an NMOS transistor connected to the sources of the transistors, the control signal applied to a gate, and a ground voltage applied to the source. The first PMOS transistor of claim 16, wherein the precharge unit is configured to invert a voltage of the output node and a first PMOS transistor to which a power supply voltage is applied to a source, the control signal is applied to a gate, and a drain is connected to the output node. And an inverter, and a second PMOS transistor having a power supply voltage applied to the source, an output signal of the inverter applied to a gate, and a drain connected to the output node. 17. The semiconductor device according to claim 16, wherein the controller comprises an inverter for inverting the clock signal, and a nod gate for generating the control signal by nominating the output signal of the inverter and the column address strobe signal. Device. The semiconductor device according to claim 16, wherein the buffer unit includes an even number of inverters connected in series. The semiconductor device of claim 11, wherein the address blocking unit includes a transfer gate configured to transfer the input address to the address input buffer in response to the redundancy enable signal. 22. The semiconductor device of claim 21, wherein the address blocking unit blocks the input address from being transferred to the address input buffer when the redundancy enable signal is activated.