KR20020082535A - Column redundancy circuit - Google Patents

Abstract

PURPOSE: A column redundancy circuit is provided, which is further stable by blocking an unnecessary current flow. CONSTITUTION: According to a redundancy circuit of a semiconductor memory device, a flag generation fuse box unit(501) inputs a block address and outputs a column redundancy flag signal. A fuse box unit(502<1:4>) inputs the block address, and also receives the column redundancy flag signal as an another input, and outputs a fuse address signal. A comparison unit(503<1:4>) is controlled by the column redundancy flag signal, and inputs the fuse address signal as one input and compares the fuse address signal with an external column address. And an enable signal generation unit(504) outputs a signal to determine an enable of a spare column address by performing a NAND and a SUM operation of the output of the comparison unit. And an enable signal transfer unit(505) receives the output of the enable signal generation unit and transfers it to the spare column address.

Description

Column redundancy circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect repair circuit used in a semiconductor memory device. More particularly, the present invention relates to a low-power circuit by reducing a current used in a fuse box in a normal situation in which a column repair is not performed on a fuse circuit. It relates to column redundancy circuitry that can be implemented.

In general, a large number of fine cells exist in a memory device such as a dynamic random access memory (DRAM), and if any one of these cells fails, the memory device becomes a defective product while failing to serve as a defect. do. However, as the integration of DRAM gradually increases, there is a high probability that defects will occur only in a small number of cells. However, treating the entire device as a defective product and discarding it is an inefficient treatment method that lowers the yield of the product. I can do it. Therefore, a method of increasing the mass production rate by replacing a defective cell by using an extra cell provided in the DRAM cell in advance is commonly used. The circuit used here is a redundancy circuit.

In addition, a repair algorithm that can repair such defective cells can be divided into row repair and column repair. In the case of column repair, the column fuse can be repaired according to a specific row block. A block address is entered into the box, and then the algorithm accepts the column address and compares the output address of the fuse with the externally input column address.

1 is a structural diagram of a cell according to the prior art and the present invention, Figure 2 shows a block diagram of a column redundancy fuse box according to the prior art.

Referring to FIG. 1, an example of a cell mesh (Cell MAT) having four loo blocks (Block <0: 3>) and 16 Yis, and in the case of a memory having such a structure, a row block selection address (Row) Two block selection addresses can be decoded and only four column addresses can be decoded. For example, the case where the block selection address is baxAB <0: 3>, which is a decoding of A and B, and the column address is Col <1: 4> will be described as follows.

When a column defect occurs in the cell mesh of FIG. 1, the column redundancy fuse box is repaired using the column redundancy fuse box in the example of FIG. 2. The column redundancy fuse box is a plug generation fuse box unit 21 that generates a column redundancy flag signal yr_frag. <1: 4> and each circuit are composed of four fuse box sections 22 <1: 4> corresponding to column addresses, and yrhit <1, which is an output signal of the comparison section 23 <1: 4>. It consists of an enable signal generation unit 24 for determining whether or not the redundancy operation by Nand Sum (4: 4), the plug generation fuse box unit (21 <1: 4>) and the fuse box unit 22 Inside the circuit of <1: 4>, there are as many fuses as there are blocks.

The detailed structure of the column redundancy fuse box will be described. A flag generation fuse box 21 for inputting the block address BaxAB <0: 3> and outputting the column redundancy flag signal yr_flagb, and the block address BaxAB < 0: 3> is input and fuse box portions 22 <1: 4> arranged in parallel by the number of columns to output fuse address signal yra <1: 4> are outputted by the column redundancy flag signal yr_flagb. A comparison unit 23 <1: 4> which is controlled and compares the fuse address signal yra <1: 4> as one input and an external column address col <1: 4> as a type force; An enable signal generator 24 and a signal for outputting the signal yrhit <1: 4> for determining the enable of the spare column address Yi by NAND and island output of the unit 503 <1: 4>. The output of the generator 24 is input to the spare column address sy. The enable signal and a transmission unit 25 for transmission.

The operation of the column redundancy fuse box having the above configuration will be described in detail.

First, when a column defect occurs in a specific block, the flag corresponding fuse box 21 cuts the fuse corresponding to the block in which the defect occurs. At this time, the column redundancy flag signal yr_flagb is enabled as "logic low". Here, when the column redundancy flag signal yr_flagb is normally "logic low" and any one of the block addresses baxAB <0: 3> is input, the fuse corresponding to the block address baxAB <0: 3> is not cut. Disabled to " logic high " and remain enabled for " logic low " if the fuse is cut.

On the other hand, each fuse box portion 22 <1: 4> cuts the corresponding fuse of the defective block of the fuse box portion 22 <1: 4> whose defective column address corresponds to "logic high". In this case, the comparator 23 <1: 4> has a fuse address signal yra <1: 4> which is an output of the fuse box part 22 <1: 4> and Col <1 which is an external column address. By comparing: 4>, if the column addresses col <1: 4> and yra <1: 4> are the same, redundancy is operated to enable the spare column address sy. In this case, the column redundancy flag signal yr_flagb is used as a signal for controlling the comparator 23 <1: 4>. If no fuse is cut because there is no block in which a column defect has occurred, the comparator 23 <1: 4>), and all of the outputs of the comparator 23 <1: 4> yrhit <1: 4> are " logic low ".

Here, the operation of the flag generation fuse box unit 21 and the fuse box unit 22 <1: 4> is performed in a low path operation. Therefore, when the fuse address signal yra <1: 4> is already enabled in the low pass and the column path operation, for example, the read or write operation, the external column address Col <1: 4> enters, At this time, the operation of the rear end of the comparison unit 23 <1: 4> is performed.

However, when the fuse of the flag generation fuse box unit 21 is not cut, the column redundancy flag signal yr_flagb controls only the comparison unit 23 <1: 4>, so that the fuse box unit 22 <1: 4>), no control. In this case, the fuse box portions 22 <1: 4> do not need to operate because they are considered to be free of column defects, and the fuse box portions 22 <1: 4> of the fuse box portions 22 <1: 4> are not operated. The current flowing through the operation becomes unnecessary.

3A to 3B are detailed circuit diagrams illustrating a flag generation fuse box unit and a fuse box unit, respectively, among the column redundancy fuse box circuits according to the related art.

4 is a timing diagram showing the operation characteristics of the signals of the redundancy circuit in the normal state without blowing the fuse according to the prior art.

Here, 'wclb' is a signal that is enabled as "logic low" when low precharge and is disabled by "logic high" when low active, and the precharge of the flag generation fuse box unit and the fuse box unit is performed. Precharge standby for nodes node0 and node1.

Referring to FIG. 3A, a flag generation fuse box unit according to the related art includes a precharge node node0, a precharge signal wlcb for determining logic of the precharge node node0, and the precharge signal wlcb as a gate input. A PMOS transistor P1 having a source connected to the voltage VDD and having a drain connected to the precharge node node0, a first inverter I1 for inverting the output of the precharge node node0, and the first inverter A second inverter I2 for forming a feedback loop to the precharge node node0 with the output of (I1) as an input, and a column redundancy flag signal yr_flagb for outputting the output of the first inverter I1 as an input; Fuses f1 to f4 and the block addresses baxAB <0: 3> connected in parallel to the third to fourth inverters I3 to I4 and the precharge node node0 as the number of columns are used as gate inputs. f4) Group includes a pre-charging series connected NMOS transistors (N1 ~ N4) to the node node0.

In addition, referring to FIG. 3B, the fuse box unit according to the related art has a precharge node node1, a precharge signal wlcb for determining logic of the precharge node node1, and the precharge signal wlcb as a gate input, and a power supply voltage. PMOS transistor P31 having a source connected to VDD and a drain connected to the precharge node node1, an inverter I31 for inverting the output of the precharge node node1, and the first inverter I31. A second inverter I32 which forms a feedback loop to the precharge node node1 and an output of the first inverter I31 as the input, and outputs the delayed and inverted fuse address signal yra as an input. Fuses f31 to f34 and the block addresses baxAB <0: 3> connected in parallel to the third to fifth inverters I33 to I35 and the precharge node node1 as the number of columns are used as gate inputs. f34) Group connected in series to the precharge node node1 yen and a MOS transistor (N31 ~ N43).

The operation characteristics of the plug generation fuse box unit and the fuse box unit having the above-described structure will be described in detail.

If a column fault occurs in the plug-generated fuse box section and the fuse of the block is blown, even if the block address is input, the column redundancy flag signal yr_flagb remains "logic low" and at the same time the block address baxAB <0: The output yra <1: 4> of the fuse box portion where the fuse is blown at the time when 3> enters is kept "logic high", and the yra <1: 4> which is not blown by the fuse transitions to "logic low".

However, if one of the block addresses baxAb <0: 3> is enabled as "logic high", if the plug generation fuse box part is not fuse cut, the column redundancy flag signal yr_flagb is set to "logic low". "Logic High" Rochon is disabled and column redundancy is disabled.

At this time, the fuse box also transitions the fuse address signal yra <1: 4> from "logic high" to "logic low" when the block address baxAB <0: 3> is enabled as "logic high".

The redundancy circuit according to the prior art as described above has the following problems.

If the column redundancy flag signal is disabled as "logic high", the logic level of the fuse address signal is "logic high" since logic for comparing the column address in the fuse box state is disabled regardless of the state of the fuse address signal. Or "logic level" has nothing to do with it. Therefore, when the transition of the fuse address signal state occurs in a normal operation situation instead of a redundancy situation, unnecessary current is consumed in the operation of the fuse box unit.

In addition, as the chip area and the cell density increase, the number of the fuse box parts used for column redundancy also increases, so the amount of current used here may be negligible.

That is, as shown in FIG. 4, since the operation of the plug generating fuse box unit and the operation of the fuse box unit operate at the same block address, the operation of the fuse box unit cannot be controlled by the column redundancy flag signal. This is because the timing of the column redundancy flag signal is later than the operation time of the fuse box unit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a more stable column redundancy circuit by preventing unnecessary current flow.

1 is a block diagram illustrating a column redundancy cell mesh;

2 is a block diagram illustrating a column redundancy fuse box according to the prior art;

3A is a detailed circuit diagram illustrating a plug generation fuse box unit according to FIGS. 2 and 5;

3B is a detailed circuit diagram illustrating a fuse box unit according to FIG. 2;

4 is a timing diagram showing a waveform of each signal according to FIG. 2;

5 is a block diagram illustrating a column redundancy fuse box according to the present invention;

6 is a detailed circuit diagram illustrating a fuse box unit according to FIG. 5;

7 is a timing diagram showing waveforms of each signal according to FIG. 5;

<Description of the symbols for the main parts of the drawings>

501: plug generation fuse box

502 <1: 4>: Fuse box part

503 <1: 4>: comparison unit

504: enable signal generator

505: enable signal transmission unit

In order to achieve the above object, the redundancy circuit according to the present invention is a column redundancy circuit of a semiconductor memory device, comprising: a flag generating fuse box section for inputting a block address and outputting a column redundancy flag signal; A fuse box unit arranged in parallel by the number of columns to be a single input, the column redundancy flag signal as a type force, and an output of a fuse address signal, and controlled by the column redundancy flag signal, A comparator which performs one input and compares an external column address as a type force; an enable signal generator for outputting a signal for determining the enable of the spare column address by NAND and island output of the comparator; Spare using the output of the enable signal generator as an input It includes an enable signal transmission unit for transmitting a signal to the column address.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

5 is a block diagram of a column redundancy circuit according to the present invention, in which a block address BaxAB <0: 3> is input and a flag generation fuse box unit 501 outputting a column redundancy flag signal yr_flagb; A fuse box arranged in parallel by the number of columns so that the block address BaxAB <0: 3> is a single input, the column redundancy flag signal yr_flagb is a type force, and the fuse address signal yra <1: 4> is an output; Controlled by the unit 502 <1: 4> and the column redundancy flag signal yr_flagb, the fuse address signal yra <1: 4> is input as one input, and the external column address col <1: 4> is inputted. A signal yrhit <1 for determining the enable of the spare column address Yi by NAND and Summing the comparator 503 <1: 4> to compare as an input and the output of the comparator 503 <1: 4>. Enable signal generator 504 and phase Comprises for the enable signal delivery unit 505 to deliver the output signal to the spare column address sy to the input of the enable signal generation unit 504. The

3A illustrates a detailed circuit diagram of a flag generation fuse box unit according to an exemplary embodiment of the present invention, and includes a precharge node node0, a precharge signal wlcb for determining logic of the precharge node node0, and a precharge signal wlcb. A PMOS transistor (P1) whose input is connected to a power supply voltage (VDD) and whose drain is connected to the precharge node node0, a first inverter (I1) for inverting the output of the precharge node node0, and the A second inverter I2 that forms a feedback loop to the precharge node node0 with the output of the first inverter I1 as an input, and the column redundancy flag signal yr_flagb as the input of the output of the first inverter I1 as an input. The third to fourth inverters I3 to I4 to be output, the fuses f1 to f4 connected in parallel to the precharge node node0 by the number of columns, and the block addresses baxAB <0: 3> are used as gate inputs. A's in the (f1 ~ f4) intermediate series-connected to said precharge node node0 yen and a MOS transistor (N1 ~ N4).

6 is a detailed circuit diagram illustrating a fuse box of the present invention, wherein a precharge node node2, a precharge signal wlcb for determining logic of the precharge node node2, and the precharge signal wlcb are used as gate inputs. A PMOS transistor P61 whose source is connected to the voltage VDD and whose drain is connected to the precharge node node2, a first inverter I61 for inverting the output of the precharge node node2, and the first inverter A second inverter I62 which forms a feedback loop to the precharge node node2 with the output of I61 as an input, and a delayed and inverted fuse address signal yra as an input of the output of the first inverter I61 as an input. The third to fifth inverters I63 to I65 to be output, the fuses f61 to f64 connected in parallel to the precharge node node2 by the number of columns, and the block address baxAB <0: 3> as one input type The column redundant The block address selection unit 60 controlled by the time flag signal yr_flagb to output the block address selection signal baxAB_sel <0: 3>, and the block address selection signal baxAB_sel <0: 3> as a gate input, and the fuse ( NMOS transistors N61 to N64 connected in series to the precharge node node2 via f1 to f4,

The block address selector 60 is configured to invert the baxABd <0: 3> delay unit 62 for delaying the block address signal baxAB <0: 3> by a predetermined amount, and the inverting column redundancy flag signal yr_flagb. The delayed block address baxABd <0: is obtained by setting the sixth inverter I66 and the column redundancy flag signal yr_flagb as the input of the PMOS gay terminal, and the output of the sixth inverter I66 as the input of the NMOS gate terminal. 3> is controlled to output the block address selection signal baxAB_sel <0: 3> and the pass gate 61 and the column redundancy flag signal yr_flafb as gate inputs, and an output terminal and a drain of the pass gate 61 are connected. The source includes an NMOS transistor N65 grounded.

7 is a timing diagram of each signal of the Y fuse box in the steady state without breaking the fuse according to the present invention.

The most preferred embodiment of the present invention will be described with reference to FIGS. 5, 3A, 6, and 7 described above.

Referring to FIG. 5, unlike the above-described conventional technology, not only the comparison unit 503 <1: 4> is controlled by the column redundancy flag signal yr_flagb, but also the fuse box unit 502 <1: 4> may be controlled. It is unnecessary in the fuse box part 502 <1: 4> in the normal state if it is input to the fuse box part 502 <1: 4> and the input part of the fuse box part 502 <1: 4> is adjusted. To prevent the current from being used.

On the other hand, since the column redundancy flag signal yr_flagb is a signal generated by the block address baxAB <0: 3>, it cannot be enabled earlier than the block address baxAB <0: 3>.

Therefore, as shown in FIG. 6, a delay is applied to the block address signals baxAB <0: 3> input to the fuse box unit so as to be used later than the column redundancy flag signal yr_flagb. The used delay unit 61 which inputs the block address baxAB <0: 3> of FIG. 6 inputs the delay timing from the block address baxAB <0: 3> to the column redundancy flag signal yr_flagb as shown in FIG. 3A. Is logic. Therefore, baxABd comes in later than the column redundancy flag signal yr_flagb and can close a pathgate switch using the column redundancy flag signal yr_flagb.

In the case of repairing, the pass redundancy flag switch is kept open because the column redundancy flag signal yr_flagb is kept in the "logic low" enabled state. In the normal state other than the repair state, the column redundancy flag signal yr_flagb receives the block address baxAB <0: 3> in the "logic low" state and is disabled as "logic high". The block address baxAB <0: 3> is disabled. Closes the passgate 61 switch before it is enabled as "logic high" and is passed to baxABd0: 3>, so that the passgate 61 output signal baxAB_sel <0: 3> remains "logic low" do. In this case, since the CMOS connected to the fuses f1 to f4 in the fuse box part is not enabled, the fuse address signal yra continues to be "logic high" and there is no current consumption.

As shown in FIG. 7, after the precharge signal wlcb, which was precharging the Y fuse boxes by bank active when the fuse is not cut, is disabled as "logic high", the block address baxAB < 0: 3> when any of the logic logic is enabled, the precharge node node0 of FIG. 3A becomes "logic low", and the column redundancy flag signal yr_flagb passes through three inverters I1 to I3. High ". BaxABd <0: 3> is a signal delaying the block address baxAB <0: 3> and is enabled later than the column redundancy flag signal yr_flagb, and at this time, the column redundancy flag signal yr_flagb is already displayed as "logic high". Since the passgate 61 is blocked because the switch is enabled, the block address selection signal baxAB_sel <0: 3>, which is the passgate output, remains "logic low" and the precharge node node2 or the fuse address at the fuse stage. The signal yra has no change. Therefore, since there is no current in the fuse box parts 502 <1: 4> due to the transition of the block address signals baxAB <0: 3>, the overall current in the Y fuse box is saved.

Also, when baxABd <0: 3> is made by delaying the block address signal baxAB <0: 3>, the operation speed is slowed by the delayed time, but there is no problem because the plug generating fuse box and the fuse box part are signals generated in the low pass. Does not occur.

In the above-described exemplary embodiment of the present invention, the passgate switch circuit, that is, the block address selector has been described using the passgate, but may be implemented using a NAND gate, a noah gate, or an inverter, and the level of the column redundancy flag signal is increased. It may be generated as a pulse to control the block address selector.

Although the technical spirit of the present invention has been described in detail according to a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the redundancy circuit according to the present invention, by controlling the fuse box part by the column redundancy flag signal, current consumption can be prevented and a more stable redundancy circuit can be provided.

Claims (4)

In the redundancy circuit of a semiconductor memory device, Flag generation fuse box means for inputting a block address and outputting a column redundancy flag signal; A fuse box means arranged in parallel by the number of columns so that the block address is one input, the column redundancy flag signal is a type force, and a fuse address signal is output; Comparison means controlled by the column redundancy flag signal and comparing the fuse address signal as one input and an external column address as a type force; Enable signal generation means for NAND and island output of the comparison means to output a signal for determining the enable of the spare column address; And Enable signal transmission means for transmitting a signal to a spare column address with the output of the enable signal generation means as an input; Column redundancy circuit comprising a. The method of claim 1, The flag generation fuse box means, A first precharge node; A precharge signal for determining logic of the first precharge node; A PMOS transistor having the precharge signal as a gate input, a source connected to a power supply voltage, and a drain connected to the first precharge node; A first inverter for inverting the output of the first precharge node; A second inverter configured to form a feedback loop to the first precharge node using the output of the first inverter as an input; Third to fourth inverters configured to output a column redundancy flag signal by using the output of the first inverter as an input; A fuse connected in parallel to the first precharge node by the number of columns; And An NMOS transistor connected in series with the first precharge node through the fuse via a block address as a gate input. Column redundancy circuit comprising a. The method of claim 1, The fuse box means, A second precharge node; A precharge signal for determining logic of the second precharge node; A PMOS transistor having the precharge signal as a gate input, a source connected to a power supply voltage, and a drain connected to the second precharge node; A first inverter for inverting the output of the second precharge node; A second inverter configured to form a feedback loop with a precharge node using the output of the first inverter as an input; Third to fifth inverters configured to output a delayed and inverted fuse address signal as an input of the first inverter; A fuse connected in parallel to the second precharge node by the number of columns; And Block address selection means which uses the block address as one input and is controlled by the column redundancy flag signal having a type force and outputs a block address selection signal; The NMOS transistor connected in series with the precharge node via the fuse using the block address selection signal as a gate input. Column redundancy circuit comprising a. The method of claim 3, wherein The block address selection means, A delay unit for delaying the block address signal by a predetermined amount; A sixth inverter for inverting the column redundancy flag signal; A pass gate configured to control the delayed block address by outputting the column redundancy flag signal as an input of a PMOS gay terminal and an output of the sixth inverter as an input of an NMOS gate terminal to output a block address selection signal; And An NMOS transistor having the column redundancy flag signal as a gate input, an output terminal of the pass gate and a drain connected thereto, and a source of which is grounded Column redundancy circuit comprising a.