KR100649970B1 - Redundancy circuit - Google Patents

Abstract

The present invention relates to a redundancy circuit, which is one of the representative defect repair circuits used in a semiconductor memory device. In particular, a fuse box comprising a plurality of anti-fuses connected respectively between a plurality of address input means and a predetermined negative potential input terminal applied from the outside. The present invention relates to a redundancy circuit capable of controlling fuse blowout by only a voltage difference induced at both ends of a fuse without expensive laser equipment, thereby realizing cost reduction in a repair operation.

Redundancy, repair, antifuse.

Description

Redundancy Circuit             

1 is a configuration diagram of a redundancy circuit of a conventional laser fuse cutting method;

2 is a configuration diagram of a conventional anti-fuse programmable redundancy circuit for 1-bit repair,

3 is a configuration diagram of an anti-fuse programming redundancy circuit according to the present invention;

4 is a logic circuit diagram for polarity control of an address signal used in the present invention.

<Description of the symbols for the main parts of the drawings>

10: laser fuse 20: cutting selection

22: buffering unit 24: delay

30: precharge means 32: address input means

34: fuse box 36: latch means

The present invention relates to a defect relief circuit used in a semiconductor memory device, and more particularly, to a redundancy circuit of an anti-fuse programming method for controlling whether or not to blow due to a voltage difference between both ends due to an external voltage application.

In general, a large number of fine cells exist in a memory device such as a DRAM, and if any one of these cells is defective, the memory device becomes a defective product while failing to serve as a defect. However, as the integration of DRAMs increases, there is a high probability that defects will occur in only a small number of cells. However, disposing and disposing of the entire device as defective products is an inefficient treatment method that lowers the yield of products. I can do it. Therefore, a method of increasing the mass production rate by replacing a defective cell by using an extra cell provided in the DRAM cell in advance is commonly used, and the circuit used here is a redundancy circuit.

1 is a block diagram of a conventional redundancy circuit of a laser fuse cutting method, which is connected between a power supply voltage applying stage and a precharge node N1 and to which a precharge control signal pcg is applied to a gate terminal. The PMOS transistor MP0 and the precharge node N1 and the ground terminal are connected in parallel with each other via the respective laser fuses f0 to fn, and the corresponding address signals A0 to An are connected to the respective gate terminals. A plurality of input NMOS transistors MN0 to MNn, an inverter IV1 connected to the rearmost end of the precharge node N1, and an output signal of the inverter IV1 are fed back to a gate terminal to supply a power supply voltage. A PMOS transistor MP1 connected between the stage and the precharge node N1 is provided.

The redundancy circuit having the above configuration cuts the laser fuse connected to the corresponding NMOS transistor to which the failed address is input among the input addresses, thereby programming for the repair operation. The programmed fuse box is precharged by a precharge control signal (pcg). The precharge control signal (pcg) is applied as 'logic high' in an active operation mode and 'logic low' in a precharge operation mode. Therefore, the potential of the precharge node N1 is always maintained at 'logic high' before the active address is input, and as a result, the final output signal fuse_out is kept at 'logic low'.

At this time, when the active normal address is input, a current path to ground is formed, and the potential of the precharge node N1 is shifted to 'logic low' so that the final fuse box output signal fuse_out becomes 'logic high'. However, when the active fail address is input, the current path to the ground is cut off by fuse cutting, and the potentials of the precharge node N1 and the output signal fuse_out change the potential in the precharge operation mode. Will remain the same. As such, it is possible to detect an address in which a fail occurs due to the potential difference of the output signal, thereby enabling the redundant word line instead of the normal word line.

However, in the case of a redundancy circuit having the above configuration and performing a repair operation, a test must be performed through a device capable of detecting an address where a fail has occurred and then moved to a laser device to cut a fuse at the corresponding address. There is a problem that comes with the hassle.                         

In order to compensate for this problem, a method of replacing the laser fuse with an anti-fuse is in use, and FIG. 2 illustrates a configuration diagram of an anti-fuse programmable redundancy circuit for 1-bit repair.

Referring to the drawing, a cutting selector 20 for selecting whether to cut a fuse by combining an address signal and an anti-fuse cutting control signal, and an output signal of the cutting selector 20 are applied to the respective gate terminals. PMOS transistor MP0 and NMOS transistor MN0 connected in series by a precharge node N1 between an applied terminal and a ground terminal, and a power-up connected between a power supply voltage applying terminal and the precharge node N1. One end is connected to the other end through the PMOS transistor MP1 to which the control signal pwr_up is applied to the gate terminal and the PMOS transistor MP2 which is always turned on to the precharge node N1. An anti-fuse af1 to which a voltage Vbb having a predetermined negative (-) potential generated through an internal voltage generator is applied, and a buffering unit for buffering the potential of the precharge node N1 ( 22) and the buffer A delay unit 24 for delaying a signal generated through the unit 22 for a predetermined time, and a signal generated through the delay unit 24 is applied to a gate terminal, and a voltage of the voltage applying stage and the PMOS transistor MP0 is applied. The other PMOS transistor MP3 connected between is comprised.

In the case of the redundancy circuit having the above-described configuration, since a separate logic configuration for fuse blowing control is provided per anti-fuse, there is a problem in that it acts as an area burden when using the anti-fuse. In addition, since the above configuration is based on the pre-repair operation after the package, a negative voltage Vbb, which is one side voltage for the anti-fuse af1 blowing, cannot be applied from the outside, but the internal voltage generator is used. As it is supplied, the current path is formed by the anti-fuse that is broken once, and the positive (+) potential on the opposite side of the fuse enters the negative voltage (Vbb) applying node to raise the potential. As a result, it is impossible to supply a strong negative voltage Vbb to the other anti-fuse to be connected due to the breakdown as in the initial operation.

In order to solve this problem, after the fuse is broken, a feedback path is formed for each anti-fuse to control the short circuit between the positive potential supply terminal and the negative potential supply terminal, which increases the design area burden. .

Therefore, the redundancy circuit using the anti-fuse according to the prior art does not cause any problem when the anti-fuse is placed on the data output side for 1-bit repair, but it is used in the row or column redundancy circuit. There is a problem that there are restrictions on use, such as not suitable as a fuse.

The present invention has been made to solve the above problems, and an object of the present invention is to configure a plurality of anti-fuse corresponding to the number of input addresses in the form of a fuse box to perform a repair operation by controlling the blowing or not by an external input voltage. It is to provide a redundancy circuit.

In order to achieve the above object, the redundancy circuit according to the present invention comprises a precharge means for performing a precharge operation by the state of the precharge control signal and the fuse cutting control signal;

A plurality of address input means connected in parallel to the precharge node and switched to receive the respective address signals;

A fuse box comprising a plurality of anti-fuses respectively connected between the plurality of address input means and a predetermined negative potential input terminal applied from the outside;

And a latch means for constantly latching and transferring the potential of the precharge node.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an anti-fuse programming redundancy circuit according to the present invention, and performs a precharge operation by the state of the precharge control signal pcg and the fuse cutting control signal anti_cut. A plurality of address input means 32 connected to the precharge means 30 and a precharge node N1 in parallel with each other, and receiving and controlling the respective address signals A0 to An, and the plurality of address input means 32. A fuse box 34 composed of a plurality of anti-fuses af0 to afn respectively connected between the address input means 32 and a predetermined negative potential Vbb input terminal applied from the outside, and the potential of the precharge node N1; It comprises a latch means 36 for latching and delivering constantly.

The precharge means includes the PMOS transistors MP0 and MP1 connected in parallel between a power supply voltage applying stage and the precharge node N1 while the two control signals pcg and anti_cut are applied to the respective gate stages. ). In addition, the plurality of address input terminals 32 may be implemented with a plurality of PMOS transistors MP2 to MPn + 2 to which corresponding address signals A0 to An are applied to each gate terminal. Replaces the NMOS transistor in the redundancy circuit used. This is because the anti-fuse blowing method is opposite to the conventional laser fuse, i.e., the anti-fuse is not destroyed while inputting a failing address, thereby preventing the formation of current paths at both sides. Implemented using the opposite PMOS transistor.

On the other hand, since the row and column repair operation by the redundancy circuit having the above configuration is performed at the wafer level, the negative potential Vbb applied through one end of the anti-fuses af0 to afn maintains a constant potential externally. Can be applied.

Hereinafter, a repair operation of a redundancy circuit according to the present invention having the above configuration will be described in detail with reference to the accompanying drawings.                     

First, when the fuse cutting control signal anti_cut is activated and applied as 'logic low', a positive voltage is applied to the precharge node N1 while the PMOS transistor MP1 is turned on. At this time, when the inactive addresses of the failing cell maintain the 'logic low' level and are input to the plurality of address input means 32, the corresponding PMOS transistor to which the address is applied to the gate terminal is turned on. The positive voltage is transmitted to one end of the connected anti-fuse. At the same time, the negative voltage Vbb applied through the external voltage generator is transferred to the other end of the antifuse, and the antifuse having a strong current path at both ends is destroyed to connect both ends. At this time, even if the breakdown timing between fuses is slightly different, the voltage across both fuses is a constant voltage applied from the outside. Therefore, if the voltage difference across both ends is large enough, all anti-fuses are the same without any problem. Can be destroyed.

As such, when the fuse programming of the inactive addresses in the failed cell is completed and the normal access operation is performed, the potential of the precharge node N1 is 'logic high' by the precharge control signal pcg. If the address of the normal cell is input, only the active address is enabled and applied to the 'logic low' level, thereby turning on the corresponding PMOS transistor. At this time, since the anti-fuse connected to the turned-on PMOS transistor is already in a broken state, the potential of the precharge node N1 is transferred to 'logic low', and as a result, the potential of the final output signal fuse_out is changed. It will remain 'logic high'.                     

On the other hand, when the address of the cell in which the fail occurred is input, the address activated at the logic low level turns on the PMOS transistor, but since the anti-fuse connected thereto is not broken, the connection is disconnected. The potential of the precharge node N1 remains 'logic high' as it is, and as a result, the potential of the final output signal fuse_out also remains 'logic low'.

The failure of the fuse box output signal (fuse_out) is judged as to whether or not a fail is generated. In the case of a normal cell without fail, the normal word line or the column line is enabled, and in the case of a failed cell, redundancy is performed. The repair operation is performed by enabling the word line or the column line.

4 is an example of a logic circuit diagram for controlling the polarity of an address signal used in the present invention, in which the anti-fuse opposing operation characteristic (anti-fuse connected to an inactive address input terminal in a failed cell is broken and connected Operating characteristics) are required for polarity matching with the address buffer and decoder. Therefore, assuming that the address output through the decoder or address buffer is 'logic high', in the operating mode where fuse destruction is required, the corresponding transistor of the address that is not active is turned on to destroy the anti-fuse connected thereto, In the access operation mode, only the address activated through inverting can be controlled to turn on the transistor.

However, without a separate logic configuration shown in the figure, the output of the buffer or decoder to the 'logic low' level, the anti-fuse breakdown control to perform only those connected to the transistor corresponding to the low active address is performed. You can do it. In this case, after the final output signal anti_out of the anti-fuse box is initially set in the normal state, only when the address of the failed cell is input, the output signal enables repair, that is, redundancy word lines and column lines. Will be controlled.

As described above, according to the redundancy circuit according to the present invention, by replacing an existing laser fuse with an anti-fuse box, no expensive laser equipment is required, and thus, an excellent effect of realizing cost reduction in repair operation can be realized. have.

In addition, the preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, changes, etc. are within the scope of the claims It should be seen as belonging.

Claims (1)

Precharge means for performing a precharge operation according to states of the precharge control signal and the fuse cutting control signal; A plurality of address input means connected in parallel to the precharge node and switched to receive the respective address signals; A fuse box comprising a plurality of anti-fuses respectively connected between the plurality of address input means and a predetermined negative potential input terminal applied from the outside; And a latch unit for latching and transferring the potential of the precharge node in a constant manner.

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