KR100311216B1 - Repair circuit of memory device for preventing stand-by current flow - Google Patents

Abstract

The present invention relates to a repair circuit of an SRAM memory device, which can reduce power consumption by a standby current and reduce chip size when a bit fail occurs.

The present invention provides a repair circuit for a memory device that reduces power consumption by blocking a flow of standby current using a precharge signal and a control signal for replacing a failed memory cell, wherein the bit line and the bit bar of the SRAM memory cell are reduced. Precharge means for precharging a line, and a control unit for blocking the operation of the precharge means when a failure occurs in a memory cell.

Description

Repair circuit of memory device for preventing stand-by current flow

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair circuit of a semiconductor memory device, and is a flow of a standby current caused when a fail occurs in a static random access memory (SRAM) memory cell. It relates to a repair circuit for blocking the.

There are two basic MOS (Metal-Oxide Semiconductor) RAM structures for semiconductor memory devices: DRAM (Dynamic RAM) and SRAM. In the case of DRAM, bit data is stored in a capacitor, whereas SRAM uses a flip-flop structure.

1 shows a circuit diagram of a memory cell of an SRAM. Referring to FIG. 1, a memory cell 10 of an SRAM has a drain connected to a first CMOS transistor 14 including a first PMOS transistor P1 and a first NMOS transistor N1 having drains connected to each other. A second CMOS transistor 15 composed of a second PMOS transistor P2 and a second NMOS transistor N2, so that the output node n1 of the first CMOS transistor 14 is formed of the second CMOS transistor 15. Are connected to the gates of the second PMOS transistor P2 and the second NMOS transistor N2, and the output node n4 of the second CMOS transistor 15 is connected to the first PMOS transistor 14 of the first CMOS transistor 14. P1) and the gate of the first NMOS transistor N1.

In addition, a first access transistor N3 connecting the output node n1 and the bit line 11 of the first CMOS transistor 14 and an output node of the second CMOS transistor 15 may be used. and a second access transistor N4 connecting the n4 and the bit bar line 12. The source of the first PMOS transistor P1 and the second PMOS transistor P2 is connected to a power supply Vcc, and the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded. Is connected to. In addition, the bit lines 11 and the bit bar lines 12 are connected to drains of the precharge PMOS transistors P3 and P4 to which the gates are connected to each other, and to which the precharge signal PE is applied. The power supply Vcc is connected to a source of the precharge PMOS transistors P3 and P4.

When a high state signal is applied to the word line 13, the first access transistor N3 connects the bit line 11 to the drain node n1 and the second CMOS transistor of the first inverter 14. 15 is connected to the gate node n3, and the second access transistor N4 connects the bit bar line 12 to the gate node n2 of the first CMOS transistor 14 and the drain of the second CMOS transistor 15. To node n4.

In order to store or read data in the SRAM memory cell, a voltage of Vcc / 2 is applied to the bit line 11 and the bit through the precharge PMOS transistors P3 and P4 by the precharge signal PE. It must be precharged to the bar line 12, and thus precharged to the bit line 11 and the bit bar line 12 before reading data from the memory cell or writing data to the memory cell. The current flowing by the voltage of Vcc / 2 is called standby-by current.

In this case, a fail may occur in the SRAM memory cell. However, in the case of the above-mentioned case, a spare memory cell capable of replacing a failed memory cell using a fuse may be prepared. I put it. However, among the causes of failing in the memory cells, the A and B portions shown in FIG. 1 are shorted in many cases. When the above short circuit occurs, even if the failed memory cell 10 is replaced with a spare memory cell, the short circuited part of the fail-occurring memory cell 10 is still shorted with the PMOS transistors P3 and P4 for precharge. Through this current flows to ground, resulting in power dissipation.

Conventionally, in order to reduce the power consumption by the standby current as described above, a method of blocking a current flowing between the power supply Vcc and the ground of the memory cell using a fuse is used. A repair circuit diagram is shown. Referring to FIG. 2, the fuses 21 and 22 are connected between the precharge PMOS transistors P3 and P4 connected to the bit line 11 and the bit bar line 12 of the SRAM memory cell 10 and the power supply Vcc. In the case where a fail occurs in the memory cell 10 by inserting the fuses, the fuses 21 and 22 are cut to cut off current flowing from the power supply Vcc to the memory cell 10.

However, when the fuse is used to cut off the current between the memory cell and the failing power source as described above, the fuse box must be inserted between the power supply Vcc and the precharge PMOS transistors P3 and P4. There was a problem that the size (Chip Size) is greatly increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the case where a fail occurs in a memory cell, a precharge signal and a pre-connect connected to the bit line and the bit bar line by using a control signal for replacing the failed memory cell are generated. A repair circuit of a memory device that blocks current from flowing from a power supply to a ground through a memory cell by turning off a charge PMOS transistor is provided.

1 is a circuit diagram of a conventional SRAM memory cell,

2 is a repair circuit diagram of a conventional memory device for blocking the flow of standby current using a fuse;

3 is a repair circuit diagram of a memory device for interrupting the flow of standby current according to an embodiment of the present invention;

(Explanation of symbols for the main parts of the drawing)

10: SRAM memory cell 20: precharge means

30: control unit 11: bit line

12: bit bar line 13: word line

14, 15: CMOS transistors 21, 22: fuses

31: Inverter 32: NAND gate

P1, ..., P4: PMOS transistor N1, ..., N4: NMOS transistor

In order to achieve the above object of the present invention, the present invention provides a memory device for reducing power consumption by blocking the flow of standby current by using a precharge signal and a control signal for replacing a failed memory cell. A repair circuit comprising: precharge means for precharging a bit line and a bit bar line of an SRAM memory cell; and a control unit for blocking the operation of the precharge means when a memory cell fails. It features.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 illustrates a repair circuit of a memory device for interrupting the flow of standby current according to an embodiment of the present invention. Referring to FIG. 3, in the present invention, when the precharge means 20 and the memory cell 10 fail to precharge the bit line 11 and the bit bar line 12, the precharge is performed. The control unit 30 for blocking the operation of the azige means 20 is made.

The precharge PMOS transistor P3 has a drain connected to the bit line 11 and the bit bar line 12 of the memory cell 10 and connected to the power supply Vcc through a source. , P4, wherein the gates of the precharge PMOS transistors P3 and P4 control to block the operation of the precharge means 30 when the memory cell 10 is repaired from the controller 30. Signal is applied.

The controller 30 inputs a precharge signal PE for precharging the SRAM memory cell 10 in advance to the NAND gate 32 through the inverter 31, and to the memory cell 10. When a failure occurs, a control signal (* CS) for replacing a spare cell is input from the controller to the NAND gate 32, and the output signal of the NAND gate 32 is a control signal as the precharge means. To the gate terminal g1 of the precharge PMOS transistors P3 and P4 of (20).

When the SRAM memory cell 10 is normally operated, the control signal (* CS) is input to the NAND gate 32 in a high state in the controller, so that the NAND gate 32 is free according to the precharge signal PE. It will perform the charge operation. At this time, when the precharge signal PE is in a high state, the low state signal inverted through the inverter 31 is input to the NAND gate 32 so that the output signal of the NAND gate 32 is made high. The bit line 11 and the bit bar line 12 are input to the gate terminal g1 of the precharge PMOS transistors P3 and P4, and thus the precharge PMOS transistors P3 and P4 are turned off. Precharge is not performed.

On the contrary, when the precharge signal PE is in the low state, the high state signal inverted through the inverter 31 is input to the NAND gate 32 so that the NAND gate 32 outputs the low state output signal. It is applied to the gate terminal g1 of the precharge PMOS transistors P3 and P4. Therefore, the bit line 11 and the bit bar line 12 are precharged to a voltage of Vcc / 2. As described above, when the SRAM memory cell 10 operates normally, the precharge signal PE is applied to the gate terminal g1 of the precharge PMOS transistors P3 and P4, thereby allowing the bit line 11 and the bit. The power supply Vcc is applied to the bar line 12 to perform normal precharge operation.

However, when a failure occurs in the memory cell 10 and the memory cell 10 is replaced with a spare memory cell, a control signal (* CS) is input to the NAND gate 32 in a low state by a controller. Regardless of the precharge signal PE, an output signal of a high state is output from the NAND gate 32 and applied to the gate terminal g1 of the PMOS transistors P3 and P4 for precharge. The precharge PMOS transistors P3 and P4 are turned off by the signal of the high state applied to the gate terminal g1, so that the power supply Vcc is turned on the bit line 11 and the bit bar line 12. By blocking the application to the power supply, power consumption can be reduced by cutting off the standby current flowing through the memory cell 10 in the case of a short circuit or the like.

In the above, the controller 30 is connected to one memory cell 10 to block the flow of standby current in one memory cell 10, but the output signals of the controller 30 are output to the plurality of memory cells 10. By applying the gate terminal of the precharge PMOS transistor connected to the plurality of defective memory cells can be controlled at the same time.

As described above, according to the repair circuit of the present invention, by controlling the control signal using the NAND gate, the standby current is changed in the memory cell in which the fail occurs without increasing the chip size as in the case of the fuse box. Can reduce power consumption.

Further, in a repair circuit of a memory element for interrupting the flow of standby current, when a failure occurs in a memory cell, power is directly applied to the gate terminal of the precharge PMOS transistor to turn the precharge PMOS transistor on. By turning off, the power consumption can be reduced by blocking the flow of the standby current flowing from the power supply through the memory cell.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (4)

In a repair circuit of a memory device for reducing power consumption by interrupting the flow of standby current by using a precharge signal and a control signal for replacing a failed memory cell, Precharge means for precharging bit lines and bit bar lines of an SRAM memory cell; And a control unit for interrupting the operation of the precharge means when a failure occurs in the memory cell. The method of claim 1, wherein the control unit A memory comprising a NAND gate that receives an inverted precharge signal through an inverter and a control signal for replacing a spare memory cell when a fail occurs in the memory cell and provides an output signal to the precharge means. Repair circuit of the device. The method of claim 1, wherein the precharge means The first and second PMOS transistors are connected to a power supply through a source, and the gates are connected to each other. Thus, a drain and a bit line of the first PMOS transistor are connected, and a drain and a bit bar line of the second PMOS transistor are connected, respectively. And a output signal of the controller is input to the gates of the first and second PMOS transistors for precharge. The repair circuit of claim 1, wherein the repair circuit of the memory device comprises: The output signal of the control unit is applied to the gate terminal of the precharge PMOS transistor constituting a plurality of memory cells, by using a single output signal to cut off the power of the memory cell in which a plurality of failure occurs at a time Repair circuit of the device.