KR970005650B1 - Address latch and matching circuit - Google Patents

Abstract

Address latch and match circuit where disable to the decoder of the normal read-out path and enable to access to the redundancy cell, in case that address that is same to the faulty address which latched in the CAM (contant addressable memory) during the operation of the normal memory device, after faulty address is latched in the CAM in the repair mode.

Description

Address Latch and Matching Circuit

The accompanying drawings show an address latch and matching circuit diagram in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

1A: first transfer circuit 1B: second transfer circuit

2: cross coupled circuit 3: control gate voltage circuit

n ₁ to n ₆ : n MOS transistor p ₁ to p ₄ : p MOS transistor

M ₁ and M ₂ : Contact Addressable Memory (CAM)

The present invention relates to an address latching and matching circuit. In particular, after a faulty address is latched in a contact addressable memory (CAM) in a repair mode, the cam is operated during a normal memory device operation. The present invention relates to a latching and matching circuit of an address which disables a decoder of a normal read path when the same address as a faulty address latched in is input, while allowing access to a redundant cell.

In general, a method of implementing redundancy includes a laser cutting method and a fuse blowing method using a high voltage. In particular, in the field of nonvolatile memory, a technique of latching a repaired address using a memory cell and matching it with an address input during normal addressing has been developed. However, such a technique tends to be complicated by constructing a circuit by separately treating a latch means for latching an address and a matching means for matching an address, and using only one cell per bit line of an address. In this case, there is a problem that the cell current continues to flow during normal memory device operation.

Accordingly, in order to solve the above problem, the present invention normally latches a pearly address in the cam in repair mode, and then inputs the same address as the pulsed address latched in the cam CAM during normal memory device operation. It is an object of the present invention to provide an address latch and matching circuit that disables a read path decoder while allowing redundant cells to access a cell.

The present invention for achieving the above object is an nMOS transistor (n ₅ and n ₆ ) which is respectively operated according to the repair signal (R) and the pulse address (A) input in the repair mode of the RAM (RAM), and repair NMOS transistors n ₃ and n ₄ respectively operated according to the signal R and the inverted pulti address AB, and the pulse address A or inverted according to the operation of the nMOS transistors n ₃ and n ₆ . A cross-coupling circuit ( ₂ ) for storing the pulse address (AB) in the cam (M ₁ or M ₂ ), and a control gate voltage circuit (3) for supplying a gate drive signal to the cam (M ₁ or M ₂ ); And first and second transfer circuits 1A and 1B for supplying an access signal to a redundant cell according to a signal stored in the cam M ₁ or M ₂ during the normal operation of the RAM. And a matching combined circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. The most commonly used stacked flash EERPOM cell was used as the contact addressable memory (CAM) used in the present invention. The program bias condition is, for example, 12V at the control gate terminal and 5V at the drain terminal. It is assumed that a ground potential should be applied to the source terminal, and 5 V should be applied to the control gate terminal during reading. It is assumed that the input signal R has a high potential only in the repair mode and has a low potential else. In the repair mode of RAM, the repair signal R maintains a high potential. When the pulsety address A has a high potential, the nMOS transistors n ₅ and n ₆ are turned on so that the node y maintains the V _ss potential. . Therefore, the gate drive signal of the cross-coupling circuit (2) PMOS transistor (P ₃₎ is turned on is the other hand, the control gate voltage circuit (3) is supplied to the control gate terminal of the cam (M ₁₎ with the cam (M ₁₎ The pearly address A is stored. At this time, since the PMOS transistor P ₄ of the cross-coupled circuit 2 is in an open state, the cam M ₂ maintains an initial state (a state in which data is erased).

On the other hand, in the repair mode, when the pulsed address A has a low potential, the inverted signal AB of the pulsed address A becomes the high potential, so the nMOS transistors n ₃ and n ₄ are turned on so that the node x is turned on. It becomes the V _ss potential. Therefore, the gate drive signal of the cross-coupling circuit (2) PMOS transistor (P ₄₎ is to be turned on while the control gate voltage circuit (3) is supplied to the control gate terminal of the cam (M ₂₎ to the cam (M ₂₎ The inverted pearly address signal AB is stored. In the normal RAM operation after the repair, the repair signal R is at a low potential, and thus the _Vss passages of the nodes x and y are blocked.

For example, in the repair mode, if the pearly address A has a high potential, the node x is in a high potential state, and the node y is kept in a low potential state and then the pearly address (not shown) is removed from the address buffer (not shown). When the same address signal (high potential state) as A) is input to the input terminal K, the high potential signal is the first transfer circuit 1A in which the nMOS transistor n ₁ and the PMOS transistor P ₁ are connected in parallel, and The redundant cell (not shown) is supplied to the redundant cell through the output terminal RED to enable access of the redundant cell, while disabling the decoder of the normal read path although not shown in the drawing. On the contrary, when the signal having the opposite phase (low potential state) is input from the address buffer A from the address buffer, the low potential signal is transmitted to the output terminal RED so that the access operation of the redundant cell is not performed.

In a similar manner, if the pearly address A was at low potential in the repair mode, node x is at low potential, and node y remains at a high potential state and then has the same low potential as the pearly address A from the address buffer. Signal is input terminal ), The low potential signal is supplied to the redundant cell (not shown) through the second transfer circuit 1B and the output terminal RED in which the nMOS transistor n ₂ and the PMOS transistor P ₂ are connected in parallel. This allows access to the redundant cell and disables the decoder of the normal read path. On the contrary, from the address buffer, a signal (high potential state) having a phase opposite to that of the pearly address A is inputted to the input terminal. ), When the low potential signal is transmitted to the output terminal RED, the access operation of the redundant cell is not performed.

For reference, K and The signals input to the terminals remain inverted with each other.

As described above, according to the present invention, in the repair mode, when the pulse address is latched to the cams M ₁ and M ₂ , and the same address as the pulsed address latched in the cam is input during the normal operation of the memory device, the decoder reads the normal read path. By disabling and allowing access to the redundant cell, the problem of cell current consumed in standby mode can be eliminated, and the circuit complexity can be improved.

Claims (3)

NMOS transistors that are operated according to respective repair signals and addresses input in a repair mode of RAM, nMOS transistors that are operated according to the repair signal and the inverted pulsety addresses, respectively, and a pulsety address or according to the operation of the nMOS transistors. A cross-coupling circuit for storing the inverted pulty address in the cam, a control gate voltage circuit for supplying a gate drive signal to the cam, and an access signal to the redundant cell in accordance with the signal stored in the cam during normal operation of the ram. And a latching and matching circuit of an address, comprising: first and second transfer circuits. 2. The latch and matching circuit of an address as claimed in claim 1, wherein the cross-coupled circuit has a PMOS transistor cross-connected with each other. The address latching and matching circuit as claimed in claim 1, wherein the nMOS transistors and the PMOS transistors of the first and second transfer circuits are configured in parallel connection.