KR0170276B1 - Row default fixing apparatus of semiconductor memory apparatus - Google Patents

Abstract

The present invention relates to a semiconductor memory device having a row defect recovery device, comprising: a normal word line selected by an input address signal; A spare word line further provided to be selected in place of the normal word line; A control signal connected to the spare word line and generating a control signal for disabling the defective word line group when a defect occurs in the word line group, and replacing the spare word line group with the defective word line group. Spare decoder means for enabling the selection line; And one decoder means connected to each of the word line groups to enable a word line group according to an input address signal, and to display a defective word line group in response to a control signal generated by the spare decoder means. It comprises a plurality of decoder means for enabling the enable. According to the present invention, there is an advantage in that the repair effect can be increased while minimizing the increase in layout in the semiconductor memory device.

Description

Low defect recovery device of semiconductor memory device

1 is a block diagram of a DRAM having a low-defect recovery device according to the prior art.

FIG. 2 is a detailed configuration diagram of the low address predecoder shown in FIG.

3 is a detailed block diagram of the ψX subdecoder shown in FIG.

4 is a more detailed block diagram of the apparatus involved in row fault recovery shown in FIG.

FIG. 5 is a detailed configuration diagram of the low decoder and the word driver shown in FIG.

6 is a detailed configuration diagram of the spare decoder and program unit shown in FIG.

7 and 8 are timing diagrams for explaining the operation of the program unit shown in FIG.

9 is a block diagram of a conventional memory device.

10 is a more detailed configuration diagram of the apparatus shown in FIG.

11 is a block diagram of a device related to low defect recovery according to the present invention.

12 is a detailed block diagram of the row defect recovery apparatus shown in FIG.

FIG. 13 shows an example of the configuration of one low decoder and four word drivers corresponding to those shown in FIG.

FIG. 14 shows an example of the configuration of the spare decoder, word driver group, and program unit shown in FIG.

15 to 18 are diagrams showing the configuration of embodiments of a program unit according to the present invention.

* Explanation of symbols for main parts of the drawings

112: low decoder group 114: spare low decoder

115: Wonder driver group 116: Memory 쎌 array

117: spare memory array 118: sense amplifier group

119: Column Decoder Group

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device having a low defect recovery device, and more particularly, to a low defect recovery device that can be programmed to replace a defective chip in a row in a row direction of a memory array. will be.

In the semiconductor memory device, if any one of a plurality of memory cells in a normal memory cell array is defective, a low cell is decoded and a spare cell is decoded. A low defect recovery device (or redundancy device) is provided to replace the defective memory cell. The spare array in which the spare arrays (or redundant arrays) are arranged is arranged around the normal array and is provided with decoders necessary for address decoding and selection of the spare array.

FIG. 1 is a block diagram of a 64K dynamic random access memory (DRAM) including a low defect recovery apparatus according to the related art. A configuration of a conventional semiconductor memory device will be described with reference to the drawings.

1 is a memory cell (MC) array, in which a plurality of memory cells MC are arranged in rows and columns, and 256 word lines WL and bit lines BL are arranged. They are arranged in row and column directions, respectively, and memory chips are located at intersections of word lines WL and bit lines BL, and memory chips are controlled by word lines to sense information of memory chips by bit lines. Transfer to amplifier 14.

2 is a spare memory cell array, in which a plurality of memory cells are arranged in a row direction and a column direction. In this example, 1K memory cells are located at the intersection of four spare word lines SWL and 256 bit lines BL, and the spare word lines are word lines arranged in the spare memory array.

4 is a RAS buffer circuit to which RASB is input, outputs ψ R indicating the operating state of the memory device, and ψ R is in the L state when the memory device is in a standby state (RASB = H). When active (RASB = L) ψ R is H.

5 denotes a low address buffer, which receives low addresses A0-A7 and outputs RAi and RAiB corresponding to each address A0-A7, and is controlled by? R. RAi and RAiB are both in the L state when the memory device is in the standby state, and either of the two transitions to the H state in accordance with the state of the address when the memory device is in the standby state.

6 is a ψP generating circuit, which outputs ψP with ψR as an input. ψP is in phase with ψR and is a delayed signal of ψR.

7 is a? X generation circuit, and generally outputs a boosted voltage level to raise the level of the word line controlling the memory 쎌 and is controlled by? R. Techniques for boosting the ψX level as described above are well known.

8 is a sense amplifier controller, which is controlled by ψ R and controls the sense amplifier 14.

9 is a low address pre-decoder, and outputs Xi, Xj, and Xk by inputting the outputs RAi and RAiB of the low address buffer 5. FIG. 2 shows a detailed configuration diagram of the low address predecoder 9 shown in FIG. 1, in which two address buffers 23 are paired and decoded through the predecoder 24 to generate four outputs. Let's do it.

For example, assuming that the address pair is A2 and A3, the two address buffers 23 output RA2, RA2B and RA3, RA3B according to the state of ψR, and the signals output from the buffer are four predecoder 24, respectively. ) To generate four outputs. The circuit of this predecoder consists of two input AND gates, and the four AND gates are respectively inputted with (RA2, RA3), (RA2B, RA3), (RA2, RA3B), and (RA2B, RA3B). X1, X2, X3, and X4 are output. In this precoding method, A2 and A3, A4 and A5, A6 and A7 are paired to decode the address, respectively, and output X1-X4 (Xi), X5 to X8 (Xj), and X9 to X12 (Xk). When the memory device becomes active, only one of each of the groups Xi, Xj, and Xk transitions to H.

10 denotes ψX sub-decoder, which outputs ψXi (ψX1, ψX2, ψX3, and ψX4) with low addresses RA0, RA0B, RA1, RA1B and ψX as inputs. FIG. 3 is a diagram showing the detailed configuration of the ψX subdecoder 10 shown in FIG.

Each subdecoder receives the low address signals RA0, RA1 and the inverted low address signals RA0B, RA1B, respectively, and outputs the subcode signal? Xi in response to the drive signal? X. In the ψX subdecoder, only one subcode signal of ψX1, ψX2, ψX3 and ψX4 becomes H according to the signal level of RA0, RA1, RA0B and RA1B, and the other signals become L.

11 is a row decoder group with 64 low decoders arranged, 12 is a spare row decoder of a programmable low defect device, and 13 is a word driver group. One word line is disposed for each word line. Details of these will be described later with reference to FIGS. 4 through 8.

14 denotes a sense amp group, and outputs information of a bit line. 15 is a CAS buffer circuit to which CASB is input, and controls the column address buffer 16 and the read / write controller 17. 16 and 18 are the column address buffer and the column address predecoder, respectively. 17 is an R / W controller for controlling reads and writes by inputting the output signals of the WEB, OEB and CAS buffers 15. 19 is a column decoder group. 21 is an input / output buffer, which is a circuit for outputting information of the sense amplifier group 14 or writing information to the memory slot array 1 under the control of the R / W controller 17. These components are conventional in semiconductor devices, and their detailed descriptions are omitted since they are not directly related to the present invention.

4 is a more detailed block diagram of the apparatus involved in row defect recovery shown in FIG. In the figure, 40 denotes 12 signal lines of Xi, Xj, Xk group, 41 low decoder group, 42 word driver group, 43 spare spare decoder, 44 word driver, 45 program part, 46 sense amplifier, 47 The column decoder, and 48 represents a memory array.

The Xi, Xj, and Xk signal lines 40 are arranged in the same direction as the low decoder, and the signals are applied to the low decoder 41, the spare decoder 43, and the program unit.

In the low decoder group 41, 64 low decoders are arranged in the column direction next to the memory array 48, and each of the signals of the Xi, Xj, and Xk groups is input as an input and an address for each low decoder is input. The information is different. Another signal ψ P input to the low decoder group 41 represents a precharge signal.

The word driver group 42 inputs the output signal of the low decoder group 41 and the? Xi signal, and its output is connected to the word line WL. There are four word drivers corresponding to each row decoder and one word driver.

The low decoder 41 and the word driver 42 will be described in more detail with reference to FIG.

The spare decoder 43 outputs A3 and A4 with the outputs of Xi, Xj, Xk, ψP and the program unit 45 as inputs. The output signals A3 and A4 of the spare decoder 43 perform the same functions as the output signals A1 and A2 of the low decoder 41. Four word drivers 44 are associated with the spare decoder 43, and the output of each word driver 44 is connected to the spare word line SWL.

The program unit 45 receives the outputs of Xi, Xj, Xk, ψP and the spare decoder 43 as inputs, and outputs an RRE signal. The program unit 45 includes a plurality of fuses, and when recovering low defects, the fuses are disconnected to recover the defects.

The spare decoder 43 and the program unit 45 will be described in more detail with reference to FIGS. 6, 7 and 8.

In memory 48, 488 and 489 indicate that a short has occurred between adjacent word lines. Such a short circuit is caused by imperfections such as particles or etching, and causes a decrease in the yield of the semiconductor memory device.

If a short circuit occurs between adjacent word lines, such as 488, the word line group 481 (which consists of four word lines corresponding to one low decoder) is replaced with a spare word line group 483. Repair operation), the yield of the semiconductor memory device can be improved. This repair operation is performed by cutting the fuse corresponding to the word line where the short circuit occurs.

However, if a short occurs like 489 and the row decoders corresponding to the two word lines are different from each other, the above method cannot be repaired.

As described above, the probability of occurrence of a short circuit in word lines corresponding to different low decoders is about 25%, which is one cause of reducing the yield of the semiconductor memory device. Therefore, a technique for repairing even when such a short circuit occurs has been studied, US Patent No. 4,914,632 discloses one of such techniques, a detailed description thereof will be described with reference to FIG.

FIG. 5 shows a detailed configuration diagram of the row decoder 41 and the word driver 42 shown in FIG. In the figure, 51 shows one low decoder and 53 shows one word driver.

Among the signals input to the low decoder 51, address information is connected to the gate terminals of the N-type MOS transistors (hereinafter referred to as NMOS-TR) 514, 515, and 516, respectively, and the source terminal of the NMOS-TR 516 is connected to ground. The drain terminal of the NMOS-TR 514 is connected to one end of the fuse 517. The other side of the fuse 47 is connected to A2.

Another signal ψ P input to the low decoder 51 is connected to the gate terminal of the P-type MOS transistor (hereinafter referred to as PMOS-TR) 510, and the source and drain terminals of the PMOS-TR 510 are respectively a power supply voltage (VCC). And A2. PMOS-TR 512 and NMOS-TR 513 constitute an inverter, the input of which is connected to A2 and the output of which is connected to A1. Therefore, the levels of the A2 and A1 signals are opposite to each other. The source, gate and drain terminals of the PMOS-TR 511 are connected to VCC, A1 and A2, respectively, to prevent the memory device from floating during active operation. The fuse 517 is a fuse blown by a laser beam, and is generally made of polysilicon.

The word driver 53 inputs? Xi and outputs A1 and A2 of the row decoder 51, and four word drivers are arranged for each row decoder, and a different? Xi is input to each word driver.

The word driver 53 is composed of NMOS-TR 524, 525, and 526, and the source, gate, and drain terminals of 525 are connected to word lines, B0, and ψXi, respectively, and the source, gate, and drain terminals of 524 are A1, It is connected to VCC and B0, and the source, gate, and drain terminals of 526 are connected to ground, A2, and word lines, respectively.

The operations of the low decoder 51 and the word driver 53 are as follows. When the precharge signal ψ P is L, the PMOS-TR 510 is in the on state and the potential of A1 is at the H level. Therefore, the NMOS-TR 526 of the word driver 53 is in the on state and the potential of the word line WL is at the L level. When the precharge signal? P rises to H, the PMOS-TR 510 is turned off. When the row select signals Xi, Xj, and Xk applied to the gates of the NMOS-TRs 514, 515, and 516 are all at the H level, the NMOS-TRs 514, 515, and 516 are all turned on, and the potential of A1 is at the L level. The potential of becomes H level. Thus NMOS-TR 526 is off. When one of the subcode signals? X1-? X4 rises to the H level, the potential of the corresponding word line WL rises to the H level. However, if the fuse is blown, the potential of A1 remains at H level, so that the potential of the word line is also at L level. Therefore, when the fuse is cut in advance, four word lines WL corresponding to the low decoder are not selected.

If there is a fault in the memory or word line, the fuses of the corresponding low decoder are blown in advance. That is, if the fuse 517 is cut off, the word lines are all at L level. If the fuse is not cut off, a word driver that inputs ψ Xi, which transitions to the H level among four ψ Xi, is operated to operate the word line corresponding to the driver. Active at H level.

FIG. 6 shows a detailed configuration diagram of the spare decoder 43 and the program unit 45 shown in FIG. In the figure, 61 shows a spare decoder, 63 shows one and a word driver, and 65 shows a program section.

The spare decoder 61 is composed of TR 610 to 615, and the PMOS-TR 610 and 611 and the NMOS-TR 612 and 613 constitute a two-input NAND circuit, and ψP and RRE are input to the NAND circuit, and the A4 signal is input. Is output. The PMOS-TRs 614 and 615 constitute an inverter and output the A3 signal by inputting the A4 signal. Four word drivers 63 correspond to the spare decoder 61, and the output of each word driver is connected to the spare word line SWL.

The program unit 65 is composed of PMOS-TR 651, 652, twelve NMDS-TR 671, 672, ... 677, and twelve fuses 661, 662 ... 667. The source, gate, and drain terminals of the PMOS-TR 651 are connected to VCC, ψP, and RRE, respectively, and are precharged. The source, gate, and drain terminals of the PMOS-TR 652 are connected to VCC, A4, and RRE, respectively, and fuses are connected. Prevents RRE floating when disconnected.

One connection point of the 12 fuses is connected to the RRE, and the other terminal of the 12 fuses is connected to the drain terminals of the 12 NMOS-TRs, respectively. Ground (VSS) is connected to all 12 NMOS-TR source terminals. The address terminals X1-X12 are connected to the gate terminals thereof, respectively.

In order for the spare decoder to be selected instead of any low decoder, the fuse corresponding to the low decoder among the fuses 661 to 667 of the program unit 65 must be cut in advance. For example, suppose that a spare low decoder should be selected instead of the low decoder shown in FIG. If the fuse 517 is not blown, the row decoder is selected when the row select signals X1, X5, and X9 are all at H level. Therefore, the fuse 517 of the low decoder and the fuses 1, 5 and 9 of the program unit must be cut in advance.

When the precharge signal? P is at the L level, the PMOS-TR 610 is in the on state, the NMOS-TR 612 is in the off state and A1 is precharged to the H level. Therefore A2 has L level. In this case, since PMOS-TR 651 is in the on state, A3 is precharged to the H level so that the PMOS-TR 611 is in the off state and the NMOS-TR 613 is in the on state. When the precharge signal? P rises to the H level, the PMOS-TR 610 is turned off and the NMOS-TR 612 is turned on. Therefore, the potential of A1 becomes L level and the potential of A2 becomes H level. At this time, the PMOS-TR 651 is turned off and the PMOS-TR 652 is turned on. When the row select signals X1, X5 and X9 are all at the H level, the first, fifth and ninth NMOS-TRs of the program unit 65 are turned on. However, since the first, fifth, and ninth fuses of the program unit 65 connected to the first, fifth, and ninth NMOS-TRs of the program unit 65 are cut, the potential of A3 remains at the H level. Therefore, the potential of A1 maintains the L level and the potential of A2 maintains the H level. This state means that the spare decoder 61 has been selected.

When at least one of the row select signals other than X1, X5, and X9 becomes H level, at least one of other NMOS-TRs other than the first, fifth, and ninth NMOS-TRs of the program unit 65 is turned on. Thus, the potential of A3 becomes L level. Therefore, PMOS-TR 611 is on and NMOS-TR 613 is off. As a result, A1 goes to H level and A2 goes to L level. This state means that spare decoder is not selected. In this way, when the first, fifth and ninth fuses of the program section 65 are cut off, the spare decoder is selected instead of the low decoder when the row select signals X1, X5 and X9 become H level.

When repairing (repairing) a low defect, the fuses corresponding to the defective address in the Xi, Xj, and Xk groups may be cut one by one. This operation will be described in more detail with reference to FIGS. 7 and 8.

7 and 8 are timing diagrams for explaining the operation of the program unit 65 shown in FIG. 6, where FIG. 7 is an operation when the fuse is blown, and FIG. 8 is when the fuse is not blown. The operation of the will be described.

Referring to FIG. 7, when the fuse is blown, the output signal RRE is maintained at the H level because the PMOS-TR 651 is turned on because ψP is at the L level when the memory device is in the standby state. Even if Xi is active and Xi is active at H level, the fuse is blown, so the RRE remains at H level. Therefore, A4 and A3 transition from H level to L level and L level to H level, respectively, and spare with ψXi active. The word line SWL is enabled.

Referring to FIG. 8, when the fuse is not blown, the operation is performed when Xi is enabled at the H level, and the NMOS-TR connected to the fuse is turned on so that the RRE transitions to the L level, and A4 and A3 are respectively. By maintaining the H level and the L level, the spare word line SWL is not enabled.

9 shows a block diagram of the memory device disclosed in the above-mentioned US Patent No. 4,914,632, and shows only the configuration related to low defect recovery. Compared to the apparatus shown in FIG. 1, a setting circuit 91 and a switch band circuit 93 are further added around the row deloader group, and the row decoder group 92, the spare decoder 94 and the word driver group are added. The functions of the sense amplifier group 98 and the column decoder group 99 function the same as or similar to those of the components shown in FIG.

FIG. 10 shows a more detailed configuration diagram of the apparatus shown in FIG. In the drawing, reference numeral 110 denotes a setting circuit, 109 a switchband circuit, 101 a low decoder group, 103 a spare decoder, 105 a program unit, 102 a word driver group, 106 a sense amplifier group, and 107 a column decoder group.

Looking at the configuration of the setting circuit 110 is as follows. 1101 is a fuse and both terminals are connected to VCC and AA, respectively. 1102 is a resistor and is connected to AA and VSS. AA is at L level when the fuse is blown, and AA is at H level when the fuse is not blown. 1103 is an inverter, with input and output terminals connected to AA and BB, respectively. The source, gate, and drain terminals of the PMOS-TR 1104 are connected to VCC, AA, and CC, respectively, and the source, gate, and drain terminals of the NMOS-TR 1105 are connected to VSS, BB, and DD, respectively. The switch band 109 is composed of switch elements, and is divided into a group 109a controlled by the AA signal output from the setting circuit 110 and a group 109b controlled by the BB signal output from the setting circuit 110.

If the fuse 1101 is not blown, AA becomes H level, BB becomes L level, the 109a group is ON and the 109b group is OFF. Therefore, when the memory device is activated, the word line is selected by the 108a group among the two types of word line groups 108a and 108b. On the contrary, when the fuse 1101 is blown, AA becomes L level, BB becomes H level, the 109a group is turned off and the 109b group is turned on, and the word line is selected by the 108b group. In this case, the first two word lines do not operate because the CC and DD signals maintain the H level and the L level, respectively, and two word lines should be added to the last word line.

According to this configuration, when a short circuit occurs in an adjacent word line such as 1088 or 1089, the 108a group or the 108b group can be selected as the word line by cutting the fuse 1101 of the setting circuit, thereby increasing the yield.

However, there are the following problems in this configuration. The first problem is an increase in layout area due to the addition of setting circuits, switchband circuits and two word lines. The second problem is that the above embodiment includes one defect recovery device. However, in general, since the semiconductor memory device includes one or more defect recovery devices, if the semiconductor device having two defect recovery devices is provided, the 1088 memory device may be used. If a short circuit of and 1089 occurs at the same time, the defect of the configuration of FIG. 10 is impossible to recover.

Accordingly, it is an object of the present invention to provide a programmable low defect recovery apparatus for minimizing the increase in layout in semiconductor memory devices and for increasing the repair effect when having two or more defect recovery apparatuses.

Another object of the present invention is to provide a semiconductor memory device having a low defect recovery device for minimizing the increase in layout and increasing the repair effect when two or more defect recovery devices are provided.

The low-defect recovery apparatus of the semiconductor memory device according to the present invention for achieving the above object generates a plurality of selection signals for selecting a word line by decoding the input address signal, one selection signal is a plurality of word lines And the selection signal is divided into a first selection signal and a second selection signal, and has a third selection signal for controlling to select one word line among a plurality of word lines controlled by one selection signal. In a memory device, a low-defect recovery apparatus for controlling to recover a defective word line to a spare word line when a defect occurs in a word line selected by the selection signal, wherein the first terminals are connected to each other in common. One of the first selection signals is respectively input to the second terminal, and the third terminal is the number of the third selection signals. A transistor having one terminal connected with the corresponding fuses, the first transistor having a group corresponding to the number of the first selection signal; One terminal is connected to the third terminal of each transistor of the first transistor group, and the other terminal is a fuse unit connected to the first terminal of each transistor of the second transistor group, the transistor unit provided in the first transistor group First fuse groups each corresponding to the number of the third selection signals; A first terminal is connected to the other terminal of the fuse of the first fuse group, one of the third selection signals is input to the second terminal, and a third terminal is a transistor connected to a predetermined power source; A second transistor group provided corresponding to the number of fuses included in one fuse group, wherein each of the third selection signals is input to a second terminal of transistors corresponding to the number of the first selection signals; One terminal may be connected in common to each other to be connected to a first terminal of a transistor of the first transistor group, and another terminal may be connected to a first terminal of a transistor of a third transistor group, respectively. A second fuse group provided correspondingly; And a first terminal is connected to the other terminal of the fuse of the second fuse group, one of the second selection signals is input to the second terminal, and a third terminal is a transistor to which a predetermined power source is connected. And a third transistor group provided corresponding to the number of fuses provided in the second fuse group.

According to another aspect of the present invention, there is provided a semiconductor memory device including a row defect device, comprising: a normal word line selected by an input address signal; A spare word line further provided to be selected in place of the normal word line: connected to the spare word line. When a defect occurs in the word line group, a control signal for disabling the defective word line group is generated, and a spare for enabling the spare selection line in place of the defective word line group. Decoder means; And one decoder means connected to each of the word line groups to enable a word line group according to an input address signal, and to display a defective word line group in response to a control signal generated by the spare decoder means. It comprises a plurality of decoder means for enabling the enable.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

11 is a block diagram showing the configuration of a device related to row defect recovery according to the present invention. In the drawing, 112 denotes a low decoder group, 114 denotes a spare decoder, 115 denotes a word driver group, 118 denotes a sense amplifier group, 119 denotes a column decoder group, 116 denotes a normal memory array, and 117 denotes a spare memory array. Description of each of these components will be described with reference to FIGS. 12 through 18, but the detailed descriptions of the sense amplifier group 118 and the column decoder group 119 which are not directly related to the present invention will be omitted.

Compared with the conventional memory device shown in FIG. 1 or FIG. 9, the memory device according to the present invention directly controls the low decoder group 112 in the spare decoder 114. FIG. In this way, the repair efficiency can be improved without additional circuit configuration as shown in FIG.

FIG. 12 is a diagram showing a detailed configuration of the row defect recovery apparatus shown in FIG. In the figure, 121 denotes a low decoder group, 123 denotes a spare decoder, 125 denotes a program unit, 122 denotes a word driver group, 126 denotes a sense amplifier group, and 127 denotes a column decoder group. Compared with the conventional apparatus shown in FIG. 10, the apparatus according to the present invention shown in FIG. 12 is that the row decoder group 112 is controlled by a predetermined control signal generated in the program unit 125. FIG.

Xj and Xk signals input to the first four low decoders are the same signal and only Xi signals are different. Xj and Xk signals input to the fifth to eighth low decoders are the same signal and only Xi signals are different. Is another signal. That is, the low decoders are grouped into four groups, and the Xj and Xk signals input thereto are the same signals, and only the Xi signals are different signals.

The low decoder group 121 and the word driver group t22 are shown in FIG. 13, the spare decoder 123 and the word driver group 124 are shown in FIG. 14, and the program unit 125 is shown in FIG. This will be explained in more detail through FIG.

FIG. 13 shows an example of the configuration of one low decoder and four word drivers corresponding to those shown in FIG. Compared with FIG. 5 described above, one connection point of the MMOS-TR 1314 which has no fuse 517 and takes X1 as input is connected to A2 instead of being connected to a fuse, and a source of NMOS-TR having X9 as input. The difference is that the NMOS-TR 1317 with an RRE input is further connected between VSSs. Referring to the operation of the circuit, when the RRE (signal output from the program unit) is H level, the word line is enabled in response to the input address. However, when the RRE is L level, the word line is enabled regardless of the input address information. Cannot be enabled.

FIG. 14 shows an example of the configuration of the spare decoder, the word driver group, and the program unit shown in FIG. In the figure, 141 denotes a spare decoder, 143 denotes a word driver group, and 145 denotes a program unit. The configuration of the spare decoder 141 and the word driver group 143 is the same as that of the conventional apparatus shown in FIG.

The program unit 145 is composed of two PMOS-TRs 1451 and 1452, a first program unit 147, and a second program unit 149.

The source, gate, and drain terminals of the PMOS-TR 1451 are connected to VCC,? P, and RRE, respectively, and the source, gate, and drain terminals of the PMOS-TR 1452 are connected to VCC, A4, and RRE, respectively.

The first program unit 147 is composed of four NMOS-TRs, eight fuses, and another eight NMOS-TRs. Looking at these configurations, the four NMOS-TRs have RRE signals connected to their drain terminals in common, Xi signals input to their gate terminals, and two fuses (first fuse and second fuse) at each source terminal. One terminal of) is connected. The drain terminal of one NMOS-TR is connected to the other terminal of each fuse. The RA1 signal is connected to the gate terminal of the NMOS-TR connected to the first fuse, and the RA1B signal is connected to the gate terminal of the NMOS-TR connected to the second fuse, and the source terminals of these NMOS-TR are connected to the ground power supply (VSS). Connected. That is, there are two fuses corresponding to X1, X2, X3, and X4, and one NMOS-TR is commonly connected between one terminal of the two fuses and the RRE, and between the other terminal of the two fuses and the VSS. One NMOS-TR is connected to each other.

Here, the NMOS-TR can be used in place of the PMOS-TR, and thus the connection of the transistor terminals must be changed, and such a connection change can be easily performed by a person skilled in the art. In other words, when the transistors are used as P-type MOS transistors (PMOS-TR), the connection between the source and the drain described above may be changed, and the ground power source VSS may be replaced with the operating voltage power source VCC.

The second program unit 149 is composed of eight fuses and eight NMOS-TRs. Looking at these configurations, the eight NMOS-TRs have Xj or Xk input to their gate terminals, one fuse connected to their drain terminals, and a VSS connected to their source terminals. The other terminals of the fuse are all connected to the RRE signal.

Referring to the operation of the low-defect recovery device having the above configuration as follows.

As shown in FIG. 1288 of FIG. 12, when word lines corresponding to the same low decoder are shorted, both fuses corresponding to X1, X2, X3 or X4 of the Xi program unit 147 are cut. Then, the RRE becomes L, the corresponding word line is disabled, and the 1281 word line group of FIG. 12 is replaced with a spare word line group 1284 and repaired.

When a short occurs between word lines corresponding to different low decoders as shown in 1289 of FIG. 12, that is, when a short occurs between the last word line corresponding to the second low decoder and the first word line corresponding to the third low decoder. The fuse corresponding to RA1 of the two fuses corresponding to Xi of the second low decoder is cut, and the fuse corresponding to RA1B of the two fuses corresponding to Xi of the third low decoder is cut.

On the other hand, if only one fuse corresponding to RA1B is cut out of two fuses corresponding to one Xi (that is, one corresponds to RA1B and the other corresponds to RA1), one of the 1281 word line groups corresponds to ψX1 and ψX2. Only word lines are repaired (see FIG. 3), and if only one fuse corresponding to RA1 is cut, only word lines corresponding to ψX3 and ψX4 in the 1281 wordline group are repaired (see FIG. 3).

However, if a short circuit occurs in a word line between four low decoder groups as shown in 287 of FIG. 12, the repair is not possible in the state where one defect recovery device is provided. Since it is usually provided, it is possible to repair this by repairing two 1281 word line groups.

In the case where two defect recovery apparatuses are provided as described above, even if short circuits such as 1288 and 1289 in FIG. 12 occur at the same time, the configuration of FIG. Has the advantage that recovery is possible.

Therefore, the present invention can improve the repair efficiency by adding only four fuses and eight NMOS-TRs compared to the prior art.

FIG. 15 is a diagram showing the configuration of the second embodiment of the program section according to the present invention. As a variation of the configuration shown in FIG. 14, the program section 155 has two PMOS-TR and first program section 157. ) And a second program unit 159.

The first program unit 157 is composed of four NMOS-TRs, eight fuses, and another eight NMOS-TRs. Looking at these configurations, the four NMOS-TRs have a common RRE signal connected to their drain terminals, a Xi signal input to their gate terminals, and two MMOS-TR drain terminals common to each source terminal. Is connected. The gate terminal of the NMOS-TR is connected with a RA1 signal or a RA1B signal, respectively. One source of each fuse is connected to the source terminal thereof, and the other terminal of the fuse is connected to the VSS. That is, compared with the configuration shown in FIG. 14, the positions of the fuse and the MMOS-TR are changed. The second program unit 159 has the same configuration as that shown in FIG.

FIG. 16 is a diagram showing the configuration of the third embodiment of the program section according to the present invention. As a variation of the configuration shown in FIG. 14, the program section 165 has two PMOS-TRs and a first program section 167. FIG. ) And a second program unit 169.

The first program unit 167 is composed of eight NMOS-TRs, eight fuses, and another eight NMOS-TRs. Looking at these configurations, each fuse has a common RRE signal connected to one terminal thereof, and a source terminal of the NMOS-TR connected to the other terminal thereof. In the NMOS-TR connected to each fuse, the same Xi signal is input to the gate terminal thereof in two units, and the drain terminal of one NMOS-TR is connected to the source terminal thereof. In the lower NMOS-TR, the gate terminal is connected to the RA1 or RA1B signal, and the source terminal is connected to the VSS. The second program unit 159 has the same configuration as shown in FIG.

17 is a diagram showing the configuration of the fourth embodiment of the program unit according to the present invention. This embodiment is to reduce the area of the layout by reducing the number of transistors connected between the fuse and the ground to two compared with the other embodiments described above. The program unit 175 includes two PMOS-TRs, a first program unit 177, and a second program unit 179.

Compared with the configuration shown in Fig. 14, in this embodiment, one NMOS-TR is used as the transistor controlled by RA1, and one NMOS-TR is used as the transistor controlled by RA1B, so that the area of the layout is reduced. It can be reduced, the operation method is the same as described above. This configuration can also be applied in the same way to the embodiment shown in FIG.

18 is a diagram showing the configuration of the fifth embodiment of the program unit according to the present invention. This embodiment is configured to include a plurality of program units that can be programmed by RA1 and RA1B. The program unit 185 includes two PMOS-TRs, a first program unit 187, a second program unit 188, and a third program unit 189.

With the above-described embodiments, repair for a defect such as 1287 shown in FIG. 12 is not possible. However, in this embodiment, the fuse controlled by the upper address Xj can also be selectively programmed by RA1 and RA1B, so that repair is possible even if such a defect occurs. In this case, two fuses controlled by Xi and two fuses controlled by Xj may be cut.

Therefore, according to the present invention, there is an advantage in that the repair effect can be increased while minimizing the increase in layout in the semiconductor memory device.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art.

Claims (16)

Generating a plurality of selection signals for selecting a word line by decoding an input address signal, one selection signal controlling a plurality of word lines, the selection signal being divided into a first selection signal and a second selection signal, In a semiconductor memory device having a third selection signal for controlling to select one word line of a plurality of word lines controlled by one selection signal, when a defect occurs in the word line selected by the selection signal. A low defect recovery apparatus for controlling to recover a defective word line to a spare word line, the first terminal being connected to each other in common, one of the first selection signals is input to the second terminal, and The third terminal includes a transistor in which one terminal of a fuse corresponding to the number of the third selection signals is connected to the number of the first selection signals. A first transistor group including response; One terminal is connected to the third terminal of each transistor of the first transistor group, and the other terminal is a fuse unit connected to the first terminal of each transistor of the second transistor group, the transistor unit provided in the first transistor group First fuse groups each corresponding to the number of the third selection signals; A first terminal is connected to the other terminal of the fuse of the first fuse group, one of the third selection signals is input to the second terminal, and a third terminal is a transistor connected to a predetermined power source; A second transistor group provided corresponding to the number of fuses included in one fuse group, wherein each of the third selection signals is input together to a second terminal of transistors corresponding to the number of the first selection signals; One terminal may be connected in common to each other to be connected to a first terminal of a transistor of the first transistor group, and another terminal may be connected to a first terminal of a transistor of a third transistor group, respectively. A second fuse group provided correspondingly; And a first terminal is connected to the other terminal of the fuse of the second fuse group, one of the second selection signals is input to the second terminal, and a third terminal is a transistor to which a predetermined power source is connected. And a third transistor group provided corresponding to the number of fuses provided in the second fuse group. The device of claim 1, wherein the transistors of the first, second, and third transistor groups are N-type transistors, and the predetermined power source is a ground power source. The semiconductor device of claim 1, wherein the transistors of the first, second, and third transistor groups are p-type MOS transistors, and the predetermined power source is an operating voltage power source. Generating a plurality of selection signals for selecting a word line by decoding an input address signal, one selection signal controlling a plurality of word lines, the selection signal being divided into a first selection signal and a second selection signal, In a semiconductor memory device having a re-selection signal for controlling to select one word line among a plurality of word lines controlled by one selection signal, when a defect occurs in the word line selected by the selection signal. A low defect recovery apparatus for controlling to recover a defective word line to a spare word line, the first terminal being connected to each other in common, one of the first selection signals is input to the second terminal, and The third terminal includes a transistor having one terminal of a fuse corresponding to the number of the third selection signals connected together, and the number of the first selection signals. A first transistor group having correspondingly; One terminal is connected to the third terminal of each transistor of the first transistor group, and the other terminal is a fuse unit connected to the first terminal of each transistor of the second transistor group, the transistor unit provided in the first transistor group First fuse groups each corresponding to the number of the third selection signals; A first terminal is connected to the other terminal of the fuse of the first fuse group, one of the third selection signals is input to the second terminal, and a third terminal is a transistor connected to a predetermined power source; A second transistor group provided corresponding to the number of three selection signals; One terminal may be connected in common to each other to be connected to a first terminal of a transistor of the first transistor group, and another terminal may be connected to a first terminal of a transistor of a third transistor group, respectively. A second fuse group provided correspondingly; And a first terminal is connected to the other terminal of the fuse of the second fuse group, one of the second selection signals is input to the second terminal, and a third terminal is a transistor to which a predetermined power source is connected. And a third transistor group provided corresponding to the number of fuses provided in the second fuse group. The device of claim 4, wherein the transistors of the first, second, and third transistor groups are N-type MOS transistors, and the predetermined power source is a ground power source. 5. The low defect recovery apparatus of claim 4, wherein the transistors of the first, second, and third transistor groups are p-type MOS transistors, and the predetermined power source is an operating voltage power source. Generating a plurality of selection signals for selecting a word line by decoding an input address signal, one selection signal controlling a plurality of word lines, the selection signal being divided into a first selection signal and a second selection signal, In a semiconductor memory device having a third selection signal for controlling to select one word line of a plurality of word lines controlled by one selection signal, when a defect occurs in the word line selected by the selection signal. A low defect recovery apparatus for controlling to recover a defective word line to a spare word line, the first terminal being connected to each other in common, one of the first selection signals is input to the second terminal, and The third terminal may include a transistor to which first terminals of transistors corresponding to the number of the third selection signals are connected together. A first transistor having a group corresponding to the number; A first terminal is connected to a third terminal of the transistor of the first transistor group, one of the third selection signals is input to the second terminal, and a third terminal is a transistor connected to one terminal of the fuse, The transistors included in the first transistor group may be provided corresponding to the number of the third selection signals, respectively, and the third selection signals may be input together to the second terminals of the transistors corresponding to the number of the first selection signals. A second transistor group; One terminal is connected to a third terminal of each transistor of the second transistor group, and the other terminal is provided with a fuse connected to a predetermined power source corresponding to the number of transistors provided in the second transistor group. Fuse group; One terminal may be connected in common to each other to be connected to a first terminal of a transistor of the first transistor group, and another terminal may be connected to a first terminal of a transistor of a third transistor group, respectively. A second fuse group provided correspondingly; And a first terminal is connected to the other terminal of the fuse of the second fuse group, one of the second selection signals is input to the second terminal, and a third terminal is a transistor to which a predetermined power source is connected. And a third transistor group provided corresponding to the number of fuses provided in the second fuse group. 8. The low fault recovery apparatus of claim 7, wherein the transistors of the first, second, and third transistor groups are N-type MOS transistors, and the predetermined power source is a ground power source. 8. The low defect recovery apparatus of claim 7, wherein the transistors of the first, second, and third transistor groups are p-type MOS transistors, and the predetermined power source is an operating voltage power source. Generating a plurality of selection signals for selecting a word line by decoding an input address signal, one selection signal controlling a plurality of word lines, the selection signal being divided into a first selection signal and a second selection signal, In a semiconductor memory device having a third selection signal for controlling to select one word line of a plurality of word lines controlled by one selection signal, when a defect occurs in the word line selected by the selection signal. A low-defect recovery apparatus for controlling to recover a defective word line to a spare word line, wherein a terminal is connected in common, and the other terminal is connected to a first terminal of a transistor. A first fuse group provided corresponding to a product of the number of times and the number of the third selection signals; A first terminal is connected to the other terminal of the fuse of the first fuse group, a second terminal is input one of the first selection signal, respectively, and the third terminal is a transistor connected to the first terminal of the transistor, A first transistor group provided corresponding to the number of fuses provided in the fuse group, wherein each of the first selection signals is input together to a second terminal of transistors corresponding to the number of third selection signals; A first terminal is connected to a third terminal of the transistor of the first transistor group, and one of the third selection signals is respectively input to the second terminal; The third terminal includes a transistor connected to a predetermined power source corresponding to the number of transistors included in the first transistor group, wherein each of the third selection signals corresponds to the number of transistors corresponding to the number of the first selection signals. A second transistor group input together with the second terminal; One terminal may be connected to each other in common and connected to one terminal of the first fuse, and the other terminal may include a fuse connected to the first terminal of the transistor of the third transistor group, corresponding to the number of the second selection signals. A second fuse group; And a first terminal is connected to the other terminal of the fuse of the second fuse group, one of the second selection signals is input to the second terminal, and a third terminal is a transistor to which a predetermined power source is connected. And a third transistor group corresponding to the number of fuses provided in the second fuse group. 11. The low-defect recovery apparatus of claim 10, wherein the transistors of the first, second and third transistor groups are N-type MOS transistors, and the predetermined power source is a ground power source. The device of claim 10, wherein the transistors of the first, second and third transistor groups are P-type MOS transistors, and the predetermined power source is an operating voltage power source. Generating a plurality of selection signals for selecting a word line by decoding an input address signal, one selection signal controlling a plurality of word lines, the selection signal being divided into a first selection signal and a second selection signal, In a semiconductor memory device having a third selection signal for controlling to select one word line of a plurality of word lines controlled by one selection signal, when a defect occurs in the word line selected by the selection signal. A low-defect recovery apparatus for controlling to recover a defective word line to a spare word line, wherein a terminal is connected in common, and the other terminal is connected to a first terminal of a transistor. A first fuse group provided corresponding to a product of the number of times and the number of the third selection signals; A first terminal is connected to the other terminal of the fuse of the first fuse group, a second terminal is input one of the first selection signal, respectively, and the third terminal is a transistor connected to the first terminal of the transistor, A first transistor group provided corresponding to the number of fuses provided in the fuse group, wherein each of the first selection signals is input together to a second terminal of transistors corresponding to the number of third selection signals; A first terminal is connected to a third terminal of the transistor of the first transistor group, one of the third selection signals is input to a second terminal, and a third terminal is a transistor connected to a predetermined power source; A second transistor group provided corresponding to the number of third selection signals; One terminal is connected to each other in common and is connected to one terminal of the fuse of the first fuse, and the other terminal corresponds to the number of the second selection signals, respectively, which are connected to the first terminal of the transistor of the third transistor group. A second fuse group; And a first terminal is connected to the other terminal of the fuse of the second fuse group, one of the second selection signals is input to the second terminal, and a third terminal is a transistor to which a predetermined power source is connected. And a third transistor group corresponding to the number of fuses provided in the second fuse group. The device of claim 13, wherein the transistors of the first, second, and third transistor groups are N-type MOS transistors, and the predetermined power source is a ground power source. 15. The low-defect recovery apparatus of claim 13, wherein the transistors of the first, second, and third transistor groups are P-type MOS transistors, and the predetermined power source is an operating voltage power source. A normal word line selected by an input address signal, and a spare word line further provided to be selected in place of the normal word line; A control signal connected to the spare word line and generating a control signal for disabling the defective word line group when a defect occurs in the word line group, and replacing the spare word line group with the defective word line group. Spare decoder means for enabling the selection line; And one decoder means connected to each of the word line groups to enable a word line group according to an input address signal, and to display a defective word line group in response to a control signal generated by the spare decoder means. And a plurality of decoder means for enabling the semiconductor memory device.