KR100572757B1 - Semiconductor memory device with cluster type decoding structure - Google Patents

Abstract

A semiconductor memory device having a cluster column decoding structure of the present invention is disclosed. The semiconductor memory device of the present invention includes M data input / output lines for transmitting data to and from a plurality of normal memory blocks, redundant memory blocks, selected normal subblocks, or redundant subblocks, where M is a natural number of two or more. Pairs. The M data input / output line pairs may input / output M data in parallel to / from M column pairs belonging to the same normal subblock or the redundant subblock to be replaced. According to the semiconductor memory device having the cluster column decoding structure of the present invention, the constraints on the layout that may occur due to the large number of column decoders embedded in one normal memory block may be relaxed. In addition, even when a defective cell occurs in a plurality of columns in the same normal subblock, efficient repair is possible.

Cluster, column, decoding, memory, data I / O

Description

Semiconductor memory device having a cluster column decoding structure {SEMICONDUCTOR MEMORY DEVICE WITH CLUSTER TYPE DECODING STRUCTURE}             

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a decoding structure of a conventional semiconductor memory device.

FIG. 2 is a diagram illustrating a connection relationship between normal sub blocks and redundant sub blocks of FIG. 1 and data input / output lines.

3 is a block diagram illustrating a semiconductor memory device having a cluster column decoding structure according to an embodiment of the present invention.

4 is a diagram illustrating column decoding of a memory cell array in a semiconductor memory device having a cluster column decoding structure according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a connection relationship between normal subblocks and redundant subblocks of FIG. 4, and data input / output lines.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a decoding structure capable of efficiently repairing a column including a defective cell.

In general, a semiconductor memory device may be classified into a read / write memory and a read-only memory (ROM). The read / write memory includes a DRAM (dynamic RAM), an SRAM (static RAM), and the like. DRAM consists of a unit memory cell composed of one transistor and one capacitor, and is a highly integrated device. The SRAM includes a unit memory cell including four transistors and two transfer transistors forming a latch structure. SRAMs are widely used in applications requiring high speed operation and low power.

On the other hand, in recent years, the density of semiconductor memory devices has increased significantly. As a result, read / write memories such as DRAM and SRAM have a very high probability of containing defective memory cells. In order to improve the yield of the memory device having such a high probability of generating defective cells, a circuit for repair is incorporated in the semiconductor memory device. The term “repair” refers to replacing a defective cell or a column or a row including a defective cell with an extra column or row. However, the decoding structure of a column or a row plays a very important role in the efficiency of such repair.

FIG. 1 is a diagram illustrating a decoding structure of a conventional semiconductor memory device, and illustrates a decoding structure of a memory cell array of an x8 type semiconductor memory device capable of inputting and outputting eight data in parallel. The memory cell array of the semiconductor memory device of FIG. 1 includes eight normal memory blocks BLKL0 to 7 and one redundant memory block RBLKL. Each of the normal memory blocks BLKLi includes eight normal subblocks NBLLK-ij (j = 1 to 8), and four redundant subblocks RBLKL-1 to 4 exist in the redundant memory block RBLKL. . In addition, there are 16 columns, that is, eight column pairs, in each normal and redundant subblock.

FIG. 2 is a diagram illustrating a connection relationship between the normal subblocks of FIG. 1, the columns of the redundant subblocks, and the data input / output lines. The normal subblocks NSBLKL-7i (i = 1 to 8) of the last normal memory block BLKL7 are shown in FIG. And the data input / output lines IO1 to 8 of the redundant sub-block RBLKL-1.

In a conventional semiconductor memory device, data output in the same normal sub block is connected to the same data input / output line. For example, data output from the first normal sub block NSBLKL-71 is transmitted to the first data input / output line IO1 regardless of the column selected. The data output from the last normal subblock NSBLKL-78 is transmitted to the eighth data input / output line IO8 regardless of the column selected. In addition, data of each column output from the redundant sub-block RBLKL-1 is transmitted to different data input / output lines IO1 to 8, respectively. That is, the data output from the eight column pairs are transmitted to the eight data input / output lines IO1 to 8, respectively.

However, in the conventional semiconductor memory device as shown in FIG. 1, since data of each column in one normal subblock is transmitted to the same data input / output line, 64 column decoders for 64 column pairs are included in one normal memory block. Should be built in. Therefore, in the layout of the circuit, the conventional semiconductor memory device is subject to many restrictions.

In addition, in order to repair the selected column, for each normal sub block, a connection fuse between the power supply voltage and the normal sub block must be built in one to one. However, since the column pitch of the memory cell is very narrow, the design rule of the fuse is wide, and thus, the layout is accompanied with difficulty. Therefore, when a large number of defective cells occur in the same adjacent normal subblock, the repair cannot be realized with one redundant subblock. Therefore, the decoding structure of the conventional semiconductor memory device has a problem of low column redundancy repair efficiency.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a semiconductor memory device which minimizes the number of column decoders and improves column repair efficiency in a semiconductor memory device capable of inputting and outputting a plurality of data in parallel. will be.

One aspect of the present invention for solving the above problems of the prior art relates to a semiconductor memory device. A semiconductor memory device having a cluster column decoding structure according to an embodiment of the present invention includes a plurality of normal memory blocks including a plurality of normal sub blocks, each of the plurality of memory cells arranged in a matrix structure having rows and columns. Said plurality of normal memory blocks; A redundant memory block including a plurality of redundant subblocks, wherein the redundant subblock has a plurality of memory cells arranged in a matrix structure consisting of rows and columns, and the redundant memory block capable of replacing the designated normal subblock. ; And M data input / output line pairs for transmitting data input / output to / from the selected normal subblock or the redundant subblock to be replaced, where M is a natural number of two or more. The M data input / output line pairs may input / output M data in parallel to / from M column pairs belonging to the same normal subblock or the redundant subblock to be replaced. The semiconductor memory device may further include a plurality of control fuses connecting the normal sub blocks and a terminal for supplying an external voltage.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

3 is a block diagram illustrating a semiconductor memory device having a cluster column decoding structure according to an embodiment of the present invention. The row select circuit 31 decodes an input row address RA and selects a predetermined row from the memory cell array 33. The column select circuit 37 decodes the data input / output circuit 35, ultimately selecting a column in the memory cell array 33. The data input / output circuit 35 inputs and outputs data to / from the memory cell array 33 through the data input / output lines IO1 to 8. The output buffer 39 buffers and outputs data transmitted from the data input / output circuit 35. The input buffer 41 buffers the input data and transmits the data to the input / output circuit 35.

4 is a diagram illustrating column decoding of a memory cell array in a semiconductor memory device having a cluster column decoding structure according to an embodiment of the present invention. Referring to this, the semiconductor memory device of the present invention also describes an x8 type semiconductor memory device capable of inputting and outputting a plurality of data (for example, eight) in parallel, similarly to the semiconductor memory device of the prior art. . The memory cell array of the semiconductor memory device of FIG. 4 is also composed of eight normal memory blocks BLKN0 to 7 and one redundant block RBLKN, similarly to the conventional semiconductor memory device shown in FIG. Eight normal subblocks NBLKN-ij (j = 1 to 8) exist in each normal memory block BLKNi, and four redundant subblocks RBLKN-1 to 4 exist in the redundant memory block RBLKN. exist. The normal subblock and the redundant subblock include a plurality of memory cells arranged in a matrix structure consisting of rows and columns. In each normal and redundant sub-block, there are 2 M columns, where M is a natural number of 2 or more, that is, M column pairs. In the present specification, for convenience of description, a semiconductor memory device in which 16 columns (ie, eight column pairs) are embedded in each normal and redundant sub-block is described.

FIG. 5 is a diagram illustrating a connection relationship between the normal subblocks of FIG. 4, the columns of the redundant subblocks, and the data input / output lines. The normal subblocks NSBLKN-7i (i = 1 to 8) of the last normal memory block BLKN7 are shown in FIG. And a connection relationship between the data input / output lines IO1 to 8 of the redundant subblock RBLKN-1.

According to the semiconductor memory device having the cluster column decoding structure of the present invention, data output from each column pair in the same normal subblock is transmitted to different data input / output lines. That is, data output from the first column pair of the normal subblock NSBLKN-71 is transmitted to the first input / output line IO1 and data output from the second column pair are respectively transmitted to the second input / output line IO2. In the same way, eight data outputted from eight column pairs in the same normal sub-block are transmitted to eight data input / output lines IO1 to 8, respectively. That is, in the present specification, each normal subblock corresponds to one cluster composed of eight column pairs. Therefore, in the present specification, the normal subblock may be interpreted as a cluster concept.

According to the semiconductor memory device according to an embodiment of the present invention, data output from each column pair in the same normal subblock is transferred in parallel to eight data input / output lines IO1 to 8 even without separate column decoding. Can be. That is, if only eight column decoders are embedded in one normal memory block, the x8 semiconductor memory device may be decoded.

Therefore, according to the semiconductor memory device having the cluster column decoding structure of the present invention, the constraints on the layout that may occur due to the large number of column decoders embedded in one normal memory block may be relaxed.

In addition, in the semiconductor memory device having the cluster column decoding structure of the present invention, the control fuses F1, F2, and B2 may be disposed between the normal subblocks and a terminal for supplying an external voltage (for example, a power supply voltage VCC terminal). ..., F7, F8) are built in. Therefore, even in the case where a defective cell occurs in a plurality of columns within the same normal subblock, efficient repair is possible. That is, the standby current can be minimized by cutting the control fuse corresponding to the normal sub block including the defective cell. That is, generation of leakage current that may occur in the normal subblock replaced by the redundant subblock is blocked, so that stable column repair is possible. In addition, since the semiconductor memory device of the present invention has a cluster column decoding structure, it is easy to layout a control fuse that blocks the leakage current in the replaced normal sub-block.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, an example in which a control fuse is embedded between the normal sub block and the power supply voltage has been described. However, even if the control fuse is embedded between the normal sub-block and the ground voltage, it is obvious to those skilled in the art that the technical idea of the present invention can be implemented. In addition, in the present specification, a semiconductor memory device capable of inputting and outputting eight data in parallel has been described. However, the number of data that can be input and output in parallel can be reduced or expanded. In the present specification, all columns that can be input and output in parallel are described as neighboring examples. However, the present invention can be applied even when the columns are not physically neighboring. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the semiconductor memory device having the cluster column decoding structure of the present invention as described above, constraints on layout that may occur due to a large number of column decoders embedded in one normal memory block may be relaxed. In addition, even when a defective cell occurs in a plurality of columns in the same normal subblock, efficient repair is possible.

Claims (5)

In a semiconductor memory device, A plurality of normal memory blocks including a plurality of normal sub blocks, each of the normal sub blocks having a plurality of memory cells arranged in a matrix structure consisting of rows and columns; A redundant memory block including a plurality of redundant subblocks, wherein the redundant subblock has a plurality of memory cells arranged in a matrix structure consisting of rows and columns, and the redundant memory block capable of replacing the designated normal subblock. ; And And M pairs of data input / output lines for transmitting data to and from the normal subblock to be selected or the redundant subblock to be replaced, wherein M is a natural number of two or more, The M data input / output line pairs M data can be input / output in parallel to / from M column pairs belonging to the same normal subblock or the redundant subblock to be replaced, The semiconductor memory device And a plurality of control fuses connecting the normal sub-blocks with a terminal for supplying an external voltage. The method of claim 1, wherein the M column pair is A semiconductor memory device having a cluster column decoding structure, characterized by neighboring each other. delete The method of claim 1, wherein the external voltage is A semiconductor memory device having a cluster column decoding structure, characterized in that the power supply voltage. The method of claim 1, wherein the external voltage is A semiconductor memory device having a cluster column decoding structure, characterized in that the ground voltage.

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