KR0172349B1 - Semiconductor memory equipment having low redundancy circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION The invention described in the claims relates to a semiconductor memory device that performs redundancy with divided word lines, and in particular, enables repair of a defective memory cell of a subword line divided from a main word line. A semiconductor memory device.

2. Technical problem to be solved by the present invention: Redundancy in a conventional semiconductor memory device having a divided word line repairs a main word line unit when a defect occurs in a memory cell of a subword line divided in a main word line. The efficiency of the redundancy was not good by executing. Therefore, the present invention allows repairing in units of divided word lines.

3. Summary of the Invention: A redundant low-free decoder having means for inputting the least significant bit of a row address to select the minimum unit of a redundant memory cell block and a fusing means for selecting the least significant bit of a defective address of a defective memory cell block. Then, the divided redundant subword lines are individually selected and driven using.

4. Significant use of the invention: Redundancy circuit in semiconductor memory devices.

Description

Semiconductor Memory Device with Low Redundancy Circuit

1 is a schematic block diagram of a semiconductor memory device having a low redundancy circuit according to the prior art.

2 is a circuit diagram of a redundant low free decoder according to the prior art.

3 is a circuit diagram of a redundant low free decoder according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundancy circuit for replacing a defective memory cell with a redundant memory cell and a control method thereof.

In general, when a defect occurs in a memory cell of a normal memory cell array, the semiconductor memory device includes a redundancy circuit that decodes and replaces an address signal corresponding to the defective memory cell with a redundant memory cell. Thus, defective memory cells of a normal memory cell array are repaired by corresponding memory cells in the redundant memory array. At this time, an address signal specifying a defective memory cell is used to specify redundant memory cells that are defectively replaced by a predetermined circuit.

To perform this function, a sensing device such as a fuse circuit capable of detecting a defective address from a defective address signal and a redundant row decoder for selecting a redundant word line of a redundant memory cell array from the detected defective address signal are required. .

1 is a schematic block diagram of a semiconductor memory device according to the prior art. The normal memory cell array 20 and the redundant memory cell array 26 have a plurality of memory cells MC and a plurality of redundant memory cells RMC, respectively. The normal memory cell MC and the redundant memory cell RMC are selected according to a specific address signal designating a predetermined memory cell so that data is written or a read operation is performed. By selecting the main word line MWL and the redundant main word line RMWL, the row addresses of the normal memory cell array 20 and the redundant memory cell array 26 are respectively designated, and the bit line selection causes the nomara memory cell array 20 and the redundant memory cell array. 26 column addresses are specified respectively.

The main word line MWL and the redundant main word line RMWL are lines selected by the outputs of the main row decoder 12 and the redundant row free decoder 22 which decode the row addresses output from the address buffer (not shown). The main row decoder 12 and the redundant row free decoder 22 decode the address supplied from the address buffer and selectively enable the corresponding main word line MWL and the redundant main word line RMWL. A plurality of sub row decoders 14, 14a to 14n located on the row side are connected to the main word line MWL. The redundant main word line RMWL for compensating for defects in the memory cells MC connected to the main word line MWL is enabled terminals of a plurality of redundant sub-row decoders 24, 24a to 24n positioned side by side like the main word line MML. Is connected to.

The sub row decoder 14 has a memory block selection signal BSiD1 to BSiD4 (where i is 0,1) in which one of two terminals is connected to one side of the main word line MWL and supplied from a main free decoder (not shown). Selects a plurality of NAND gates 16a to 16d for inputting a natural number (2,3, etc.) to another terminal, an output terminal of the NAND gates 16a to 16d, and a plurality of memory cells MC located in the normal memory cell array 20; Inverters 18a to 18d connected to the subword lines SWL1 to SWL4, respectively.

The sub row decoder 14 is operated by selecting the main word line MWL. That is, when the main word line MWL becomes logic high, the NAND gates 16a to 16d are enabled and output inverted signals of the block selection signals BSiD1 to BSiD4 respectively input to the other terminals. The inverters 18a to 13d connected to the output terminals of the NAND gates 16a to 16d invert the gating signal to select the corresponding subword lines SWL1 to SWL4. For example, when the main word line MWL is selected and made high and the block select signal BSiD1 is input high, the subword line SWL1 is selected. Therefore, only the memory cells MC connected to the subword line SWL1 in the normal memory cell array 20 are accessed.

Meanwhile, the redundant sub row decoder 24 includes a plurality of NAND gates 28a through 28d and inverters 30a through 30d in the same manner as the sub row decoder 14. The difference between the configuration of the sub row decoder 14 and the redundant sub row decoder 24 is that it is only enabled by the selection of the redundant main word line RMWL of the redundant row free decoder 22. Accordingly, when the redundant main word line RMWL is selected by the operation of the redundant low predecoder 22 and one of the block selection signals BSi1D to BSiD4 or BSj1D to BSjD4 is selected, the redundant sub-row decoder 24 selects the corresponding redundant subword line RWSLi. The redundant memory cell RMC is then accessed.

The redundant row free decoder 22 and redundant sub row decoder 24 are selectively operated when a memory cell MC in the normal memory cell array 20 accessed by the main row decoder 12 and the sub row decoder 14 has failed. The description will make it clearer.

Referring to FIG. 2, the redundancy operation according to the prior art will be described.

FIG. 2 is a diagram showing a circuit of a redundant low free decoder employed in the semiconductor memory memory device of FIG. At least one such redundant low free decoder 22 is provided in the redundant low free decoder 22 of FIG. 1. That is, it is apparent that a plurality of redundant row-free decoders corresponding to the number of redundant main word lines RMWL connected to the plurality of redundant memory cells are provided.

The configuration of the redundant low-free decoder shown in FIG. 2 gates a plurality of NMOS transistors 48 and 58 selectively operated on the address signals RAi to RAj outputted from the address buffer input to the gate, and the inverted address signals RAib to RAjb. A plurality of fuses 46,50,56,60 connected to the plurality of NMOS transistors 52, 62 and drains of the respective NMOS transistors 48, 52, 58, 62, and the plurality of fuses 46, A precharge node N1 for connecting one end of 50, 56, 60 to each other, a precharge control circuit 100 for controlling the precharge state of the precharge node N1 in response to an input of a control signal CSB, and the precharge The outputs of the inverters 66 to 70 connected in series with the charge node N1 and the output of the inverter 66 and the output of the inverter 66 which selects the redundant main word line RMLi are negatively mixed with the outputs of the inverter 66 and the inverter 70. It consists of a NAND gate 74 for generating a signal RRDT for interrupting the operation of the right decoder 12.

In the configuration of FIG. 2, the precharge control circuit 100 includes the PMOS transistors 40, 42 and NMOS transistor 44 connected in series between the power supply voltage Vcc and the ground, and the main fuse 32 which determines the redundant mode. The connection nodes of the PMOS transistor 42 and the NMOS transistor 44 are connected to the precharge node N1, and these transistors are each switched by the precharge control signal CSB supplied to the gate. The gate of the PMOS transistor 40 is connected to a node to which the main fuse 32 and the resistor 34 and the inverter 32 are connected. At this time, the other side of the resistor 34 is connected to ground, and the inverter 32 is connected to the gate of the NMOS transistor 36 connected between the gate of the PMOS transistor and the ground.

In order for the precharge circuit 100 configured as described above to precharge the precharge node N1, the main fuse 32 must be blocked. That is, the fuse 32 is blocked in the redundant mode. When the main fuse 32 is cut off, the inverter 32 inverts a low input to drive the NMOS transistor 36. Therefore, the PMOS transistor 40 whose gate is connected to the drain of the NMOS transistor 36 is driven to transfer the power supply voltage Vcc to the drain of the PMOS transistor 42. The precharge operation of the precharge node N1 is performed at the input of the precharge control signal CSB while the power supply voltage Vcc is supplied as described above. For example, when the precharge control signal CSB is input in a low state, the PMOS transistor 42 is turned on and the NMOS transistor 44 is switched off to precharge the precharge node N1 to a high level. On the contrary, when the precharge control signal CSB is input to the high state, the PMOS transistor 42 is turned off and the NMOS transistor 44 is turned on to discharge the voltage of the precharge node N1.

In the redundant mode, a method of selectively blocking the fuses located in the second drawing includes an electric method and a laser method, which are obvious to those skilled in the art. On the other hand, the fuse used at this time is usually made of polysilicon.

Referring to FIGS. 1 and 2, the redundancy operation according to the prior art will be described.

In the semiconductor memory device as shown in FIG. 1, when a repair is not necessary, that is, when a redundancy operation is not required, all fuses 46, 50, 56, and 60 including the main fuse 32 are not blocked. If the main fuse 32 is not blocked, the redundant low free decoder of FIG. 2 does not operate because the PMOS transistor 40 is turned off.

If a defect occurs in the memory cell MC positioned in the low region of the normal memory cell array 20 in the semiconductor memory device as shown in FIG. 1, as is well known, the redundant memory cell RMC positioned in the row region of the redundant memory cell array 26 is well known. Should be replaced by. That is, it must be repaired. When the repair is required as described above, the main fuse 32 shown in FIG. 2 is cut off, and a row address signal corresponding to a defective memory cell among the plurality of fuses 46, 50, 56, and 60 is input to the gate. A fuse connected to the drain of the NMOS transistors 48 and 58 or a fuse connected to the drain of the NMOS transistors 52 and 62 which inputs the output of the inverter 54, 58 to the gate is cut off. For example, when a defect occurs in the memory cell MC of the normal memory cell array 20 when the row addresses are all 1, the NMOS transistors 48 and 58 that input the signals of the main fuse 32 and the row addresses RAi to RAj as gates are used. By replacing the fuses 46 and 56 connected to the drains of the capacitors, the redundant memory array 26 can be replaced. The row addresses RAi to RAj are row addresses for selecting the redundant main word line RMWL shown in FIG. 1 and address information for selecting memory blocks of four redundant subword lines RSWL. At this time, the fuses 50, 60 connected to the trains of the NMOS transistors 52, 62, which input the outputs of the inverters 54, 64, which invert the signals of the row addresses RAi to RAj, to the gate, should be left as they are.

When the main fuse 32 is cut off as described above, the PMOS transistor 40 in the precharge circuit 100 is turned on to supply the power supply voltage Vcc to the drain of the PMOS transistor 42. The PMOS transistor 42 is turned on in response to the precharge control signal CSB input in a low state supplied from the outside, thereby supplying a power supply voltage Vcc to the precharge node N1. At this time, the precharge node N1 remains low until the defect addresses RAi to RAj are input to the gates of the NMOS transistors 48 and 58 and the inverters 54 and 64. This is because the power supply voltage Vcc supplied from the PMOS transistor 42 to the precharge node N1 flows to the ground through the drain to the source of the NMOS transistors 52 and 62 which are in a conductive state until the defect address signal is input.

In the above state, when the signals such as row addresses RAi to RAj become all 1s as the path of the defective address, the NMOS transistors 52 and 62 whose outputs of the inverters 54 and 64 are connected to the gate are turned off, and the NMOS transistors 48, Since fuses 46 and 56 connected to the drain of 58 are shut off, the potential of the precharge node N1 transitions to the level of the power supply voltage Vcc supplied from the source of the PMOS transistor 42. That is, logically high. The inverter 66 connected to the precharge node N1 supplies a low signal to the inverter 68 and the NAND gate 74. The inverter 68 and the inverter 70 connected in series therewith delay the output of the inverter 66 by a predetermined time and output the same to the NOR gate 72. Accordingly, the NOR gate 72 negatively combines the output of the row of the interleaver 66 with the signals delayed by the inverters 68 and 70 to select the redundant main word line RMWL shown in FIG. 1 as a logic high signal. That is, a high signal is transmitted to the redundant main word line RMWL.

At this time, the NAND gate 74 for inputting a low signal output from the inverter 66 outputs an RRDT signal having a logic high. The RRST signal is useful for stopping the selection of the main word line MWL by stopping the operation of the main row decoder 12 shown in FIG. Here, another input terminal 102 of the NAND gate 74 is an output of another redundant low free decoder.

When the redundant main word line RWML of FIG. 1 is selected by the operation described above, the redundant sub-row free decoder 24 is enabled, and the redundant sub-row decoder 24 is generated by two-bit addresses Ai and Aj of the least significant bit of the row address. The redundant memory cell array 26, i.e., the redundant subword line RSWL1 in the memory block, by the block selection signals BSiD1 to BSjD4 and BSjD1 to BSjD4, which are selectively enabled by the signals Ai, Aib, Aj, and Ajb and the BS as the block selection signal. One of ˜RSWL4 is selected to repair the defective memory cell MC in the normal memory cell array 20. Here, the redundant subword lines RSWL1 to RSWL4 are respectively determined by the lower bits of the address, and each of the redundant subword lines RSWLi is selected by the coding of the lower addresses 00,01,10,11.

However, in the structure of the semiconductor memory device to which the redundant row free decoder as shown in FIG. 2 is applied, the main word line MWL of the normal memory cell 20 runs horizontally as shown in FIG. Subword lines SWL1 to SWL4 of the block of memory cells connected to the decoder. In addition, in order to repair the defective memory cells in the normal memory cell array 20, a plurality of redundant subword lines RSWL1 to RSWL4 are typically generated in the redundant main word line RMWL.

Therefore, in the semiconductor memory device shown in FIG. 1, even if a defect occurs only in the memory cell MC connected to one subword line SWL1 in the normal memory cell array 20, the four redundant subword lines RSWL1 to RSWL4 connected to the redundant main word line RMWL are Selected and repaired at the same time. That is, when the redundancy operation is performed, in the memory device of FIG. 1 to which the redundant low-free decoder such as FIG. 2 is applied, four redundant subword lines RSWL1 to RSWL4 connected to the redundant sub-row decoder 14 connected to the redundant main word line RMWL are simultaneously present. As a result of the repair, the probability of a fault occurring again by a redundant memory cell RMC connected to four redundant subword lines RSWL1 to RSWL4 is very high. That is, although the defect of the memory cell MC of the subword line SWL having a defect in the normal memory cell array 20 is repaired, the redundant memory cell of the other three redundant subword lines RSWL2 to RSWL4 selected by the redundant main wordline RMWL There has been a problem that could lead to another defect by RMC.

Accordingly, another object of the present invention is to provide a semiconductor memory device for selectively repairing only memory cells of one subword line in which a defect occurs in a semiconductor memory device in which a memory cell array is blocked.

Another object of the present invention is to provide a redundant row decoder capable of improving redundancy efficiency of a semiconductor memory device.

The above object is to solve the problems of the conventional circuit, and when repairing using the redundant main word line, it is possible to selectively select a defective sub word line for repair. That is, in a conventional circuit, when a repair is performed using a redundant main word line, when a defect occurs in a memory cell connected to one of the plurality of subword lines connected to the main word line, the redundant main word line is replaced by the redundant main word line. Although it is intended to replace all of the redundant subword lines of, but to selectively select this to provide a technical configuration that can use the redundant subword line.

According to an aspect of the present invention, a memory cell block having at least one or more subword lines to which at least one memory cell is connected, a main word line for selecting the memory cell block, and a selection of the main word line And a sub-row decoding means for decoding a block selection signal and selecting at least one of the subword lines to perform redundancy for replacing defective memory cells in the memory block. An apparatus comprising: a redundant memory cell block having at least one redundant subword line to which at least one redundant memory cell is connected, means for inputting address information for individually selecting the redundant subword line, and the memory cell Faulty memory cell in a block And a redundant row free decoding means including a defective address selecting means for selecting a corresponding row address and selecting a redundant subword line corresponding to the defective address in response to an input of a row address input to the address information input means. It is characterized by.

According to the principle according to the present invention, means for inputting address information for individually selecting the redundant subword lines means for inputting the least significant bit of a row address so as to select a minimum unit of a redundant memory cell block and a defective memory cell And fusing means for selecting the least significant bit of the defective address of.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a redundant low free decoder according to the present invention. The redundant low pre-recorder shown in FIG. 3 is an information input for inputting address information for individually selecting the redundant subword lines RSWL1 to RSWL4 shown in FIG. 3 in the configuration of the redundant low-free decoder shown in FIG. Means are further added. That is, the drain terminals of the NMOS transistors 76, 82 for inputting RDi and RDj, which are the least significant bits of the row address, as the gates, and the drain terminals of the NMOS transistors 78, 84 for inputting the inverted least significant addresses, RDiB, and RDjB, are connected to fuses Fi, FiB, It is connected to the precharge node N1 via Fj, FjB. The NMOS transistors 76 to 84 correspond to address input means, and fuses Fi, FiB, Fj, and FjB correspond to fuse means. The redundant sub-word lines RSWL1 to RSWL4 are individually selected among the semiconductor memory devices shown in FIG. 1 by the configuration of the redundant low-free decoder according to the present invention with reference to FIG. 3 to repair defective memory cells. It is as follows.

Now, in the semiconductor memory device as shown in FIG. 1, if a defect occurs in the memory cell MC located at the subword line SWL1 of the main word line MWL, it should be replaced with the redundant memory cell RMC of the redundant memory cell array 24 as is well known. do.

In order to repair the memory cell MC connected to the subword line SWL1, the main fuse 32 of the redundant low free decoder configured as shown in FIG. 3 should be shut off. NMOS transistors 48, 52, 58, 62, 76, 82 to which address signals corresponding to defective memory cells are applied among the fuses 46, 50, 56, 60, Fi, FiB, Fj, and FjB shown in FIG. Fuses connected to the drains of As described above, the precharge node N1 of FIG. 3 in which the fuse corresponding to the address of the defective memory cell is blocked is precharged to the high level in the active state as described above.

The NMOS transistors 78 and 84 whose gates are connected to the output terminals of the inverters 80 and 86 and the NMOS transistors 76 and 82 in the configuration of FIG. 4 are used to divide four subword lines SWL1 to SWL4 from the main word line MWL. Means for inputting the least significant bit of a row address that is not. The fuses Fi, FiB, Fj, and FjB connected to the drains of the NMOS transistors 76 to 84 are means for selecting an address corresponding to a defective memory cell located at the subword lines SWL1 to SWL4. Here, in the case of the fuses Fi and Fj, the lowest is j and the next lower concept is i. Accordingly, it can be seen that coding for the following memory cell defects is enabled by fuse decoding by the least significant bits RDi and RDj of the row address as shown in Table 1 below.

However, 0 means fuse connect (NOT BLOWN), X means fuse block (BLOWN).

Therefore, when a defect occurs in the memory cell MC connected to the subword line SWL1 in the normal memory cell array 20 shown in FIG. 1 and needs to be repaired, the fuses FiB and FjB connected to the drains of the NMOS transistors 78 and 84 are blocked. . In the above state, the least significant bits RDi and RDj of the row address for selecting the subword line SWL1 connected to the main wordline MWL where the defective memory cell is generated are 0.0 and input to the gates of the NMOS transistors 48, 58, 76, and 82. Then, the NMOS transistors 76, 82 are turned off, and only the NMOS transistors 78, 84, which input the outputs of the inverters 76, 82, are turned on.

If the redundant subword line RSWL1 and the redundant subword line RSWL2 are repaired to the redundant memory cell, the node N1 is determined only by the RDi state regardless of the state of the addresser RDj when the fuse FBB is selected and fused. . That is, since the redundant main word line RMWL is determined by the value of the address RDi, it can be seen that the desired subword line SWLi can be repaired selectively. In this case, since the fuses FiB and FjB connected to the drain terminals of the NMOS transistors 78 and 84 are blocked, the fuses 46, 50, 56, and 60 of FIG. 3 are properly fuse coded as described above with reference to FIG. The redundant row free decoder configured as described above selects the redundant main word line RMWL by inputting the least significant bits RDi to RDj of the row address.

When the redundant main word line RMWL is selected by the combined address decoding as described above, the high subword line selection signal is supplied to the selection terminal of the NAND gate 28a of the redundant sub row decoder 24 illustrated in FIG. In this case, another input terminal of the NAND gates 28a to 28d is selected by the block selection information BSiD1 to BSiD4 and BSjD1 to BSjD4, so that the desired redundant subword line RSWLi can be selected among the redundant subword lines RSWL1 to RSWL4. One of the inverters 30a to 30d selected by the above operation inverts the input of the row to drive the redundant subword line RSWLi to which redundant memory cell RMCs are connected to perform a repair operation on the defective memory cell.

Therefore, even if a defect occurs in a memory cell of a subword line generated from one main word line, the repair operation is performed by selecting only a redundant subword line corresponding to the defective subword line without repairing the entire main word line. It can be seen.

According to the related art, when a defect occurs in a memory cell connected to one of the four subword lines SWL to SWL4 subordinate to the main word line MWL, the redundant main word line RMWL is repaired to repair four redundant subwords. Although the entire memory block is repaired because the lines RSWL1 to RSWL4 are selected, in the present invention, the redundant subword line is individually selected to selectively repair only the memory cells corresponding to the subword line where the defective memory cell is generated. Repair to the line can be prevented. That is, the present invention can improve redundancy efficiency by selectively adjusting the number of repaired subword lines connected to each main word line using one redundant low free decoder. have.

In the above-described embodiment, the address input means is described using an NMOS transistor and an inverter. However, it should be noted that a person skilled in the art may modify the present invention without departing from the spirit of the present invention. That is, the present invention may be easily applied to a redundant row-free decoder composed of a plurality of fuses and a NAND and a NOA gate for coding a transmission gate and a defective address.

As described above, in the semiconductor memory device having a structure in which a word line of a memory cell is divided into a plurality of subword lines around a main word line, a redundant subword line having a defect is selected among the subword lines. By repairing, the redundant memory cells can be used more efficiently, and there is an advantage in that defects caused by redundant memory cells can be prevented during repair on a block basis.

Claims (3)

A memory cell block having at least one subword line to which a plurality of memory cells are connected, a main word line for selecting the memory cell block, and a block selection signal enabled by selection of the main word line 9. A semiconductor memory device having redundancy means for replacing defective memory cells in the memory block by sub row decoding means for selecting at least one subword line among the subword lines, wherein a plurality of redundant memory cells are connected. Means for inputting a redundant memory cell block having at least one redundant subword line, address information for individually selecting the redundant subword line, and selecting a row address corresponding to a defective memory cell in the memory cell block Fault address selection means And a redundant row free decoding means for selecting a redundant subword line corresponding to the defective address in response to a row address inputted to the address information input means. . 2. The apparatus of claim 1, wherein the means for inputting the address information comprises: means for inputting the least significant bit of the row address of the defective memory cell so as to select the minimum unit of the redundant memory cell block and fusing means for selecting the least significant bit. A semiconductor memory device having a low redundancy circuit. The semiconductor memory device of claim 1, wherein the redundant row-free decoder selectively varies the number of redundant sub-row decodings connected to each other by selectively restraining the lowest address supplied to the semiconductor memory device. .