KR960012792B1 - Column redundancy circuit - Google Patents

Abstract

a redundancy address selecting means programming the address selecting a bad column by using a fuse and receiving a column address and a block selecting address as input; a redundancy column free decoding means operating a block selecting pass of a memory block to repair by composing the programmed address output of the redundancy address selecting means; a redundancy logic means disabling the normal column selecting pass selecting the bad column in repair operation; and a redundancy column decoding means enabling the repaired redundancy column.

Description

Column redundancy circuit

1 is a configuration diagram showing an example of a memory block according to the arrangement of spare columns.

2 is a configuration diagram showing another example of a memory block according to the arrangement of spare columns.

3 is a decoding block diagram including a conventional column redundancy circuit.

4 is a decoding block diagram including the column redundancy circuit of the present invention.

5 is a block diagram showing an embodiment of a column redundancy circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

1: row address buffer, 2: block selection address buffer,

3: column address buffer, 4: first row free decoder,

5: first block select predecoder,

6: first column free decoder, second row free decoder,

8,8 ': second block select free decoder, 9,9': second column free decoder,

10: block row decoder, 11: block column decoder,

12,12 ': Redundancy address selection circuit, 13: Master fuse,

14,14 ': redundancy column free decoder, 15: redundancy logic,

16: redundancy block column decoder, 17: column pass gate,

18: redundancy column pass gate, 19: redundancy column.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit of a semiconductor device, and in particular, to prepare a spare cell for column repair in each memory block and to use the peripheral circuit technology to solve the defect in each block. It relates to a column redundancy circuit that allows not only columns but also replacement of bad columns in other blocks.

In general, as semiconductor memory devices are highly integrated, a method of dividing an entire memory array into a plurality of memory blocks in consideration of its performance is becoming more common.

In addition, as the integrated circuit proceeds, the importance of a redundancy circuit that prepares a spare memory cell in advance and replaces it with a spare cell when a defective cell occurs is emerging in terms of production yield.

In general, there are two methods for arranging an extra cell in a redundancy circuit, which is arranged along a row direction (word line) and a column direction (bit line) of a memory array. It relates to the column redundancy circuit arranged.

1 and 2 illustrate a memory block in which spare columns are arranged differently, and FIG. 1 illustrates a method of distributing spare columns in each memory block. FIG. It shows how to arrange spare columns in blocks only.

In the case of FIG. 1, the spare column is properly distributed, so that it may be ideal, but may replace only defective cells in the same block, and defective cells generated in other blocks may not be replaced.

For example, if the entire memory array is divided into four memory blocks, and one spare column is disposed in each block, one bad column may be replaced in each block, but two different addresses may be used. The defective column cannot be replaced.

The method of supplementing the disadvantages of FIG. 1 is shown in FIG. 2. The number of spare columns is the same, but is located in a specific memory block (for example, the fourth memory block). If you select a specific memory block by configuring the column repair logic using technology, you can replace the defective cells by the number of spare columns (four here) in one memory block, and handle the number of different cases of defects that can actually occur. There are advantages to it. However, if there are many spare columns in a particular block, the load on word lines and data bus lines can be increased to induce specific degradation of the product. This can increase the number of spare columns due to the large number of data input / output and memory capacity. The more serious it appears. The above problem may be solved by separately configuring the spare column block, but a load and layout may be additionally provided such as a spare decoder and a spare sense amplifier for configuring the spare column block. ) Increased area, complexity of peripheral circuits are a problem.

Therefore, in the present invention, the arrangement of the spare column is configured as shown in FIG. 1, and the efficiency of the redundancy circuit is improved by adopting a simple method using peripheral circuit technology as shown in FIG. The purpose is to eliminate the problems of the prior art described.

FIG. 3 illustrates a decoding block including a conventional column redundancy circuit, and a configuration and operation principle of a conventional column redundancy circuit will be described with reference to the decoding block.

The address input required for selecting a memory cell includes a row address (Ax) for selecting a word line of the memory cell, a column address (Ay) for selecting a bit line, and a block selection address for selecting each memory block constituting the cell array. Each of the address inputs (Ax, Ay, and Az) passes through the respective address buffers (1, 3, 2) and the positive signal (AX, AY, AZ) and the code signal (/ AX, / AY, / AZ) These outputs are passed through the respective pre decoders 4, 5, 6, 7, 8, and 9 that constitute the address combination, and the block row decoder 10 and the block column decoder 11 for finally selecting the cells of each block. Decoded at The block row decoder 10 selects the word line WL in the corresponding memory block, and the block column decoder 11 selects the bit lines BIT and / BIT through the column pass gate 17, thereby selecting a memo cell. Will be specified.

The read / write operation is performed through the data bus lines DB and / DB connected to the bit lines BIT and / BIT through the column pass gate 17.

Here, the configuration and operation principle of the column redundancy circuit are as follows. AYj and / AYj signals, which are outputs of the column address buffer 3, are inputted through the redundancy address selection circuit 12 and then combined in the redundancy column predecoder 14. Finally, the redundancy column 19 is selected through the redundancy block column decoder 16 and the redundancy column pass gate 18.

The redundancy address selection circuit 12 outputs a signal in a constant state when an address (column address) input from the outside of the device is the same as an address logic of a defective cell to be replaced. A fuse using a polysilicon layer is used. ) By blowing with a laser.

The master fuse 13 is a circuit for determining whether the column redundancy circuit is operated. When the master fuse 13 is turned off in the normal operation state and turned on to operate the repair arc, the master fuse 13 is input to the redundancy column predecoder 14 to provide a redundancy column. The / REDYm signal is output in combination with the output signal RAj of the redundancy address selection circuit 12 which is the other inputs of the predecoder 14. This signal is converted to the signal / REDY via the redundancy logic 15, which is a combination of / REDYm signals, when the input of the address matches the address address that selects the bad cell, and then disables the second column predecoder 9 The normal column is turned off, and the redundancy column 19 is selected through the redundancy block column decoder 16 and the redundancy column pass gate 18.

4 illustrates a decoding block including the column redundancy circuit of the present invention, and the configuration and operation principle of the column redundancy circuit of the present invention will be described with reference to the decoding block.

The arrangement of the spare column is the same as FIG. 1 and the block diagram is the same as that of FIG. 3, which is different from FIG. 3, that is, the parts designed for the present invention.

The redundancy address selection circuit 12 'further includes the block selection addresses AZ1, / AZ1, AZ2, / AZ2 in the existing column addresses AYj, / AYj of the input signal. This is because the block selection addresses AZ1, / AZ1, AZ2, and / AZ2 must be determined to replace the column of the defective cell in which block.

The output of the redundancy address selection circuit 12 'to which the block selection addresses AZ1, / AZ1,, AZ2, and / AZ2 are added goes to the input of the redundancy column predecoder 14' and the output / REDY of the redundancy logic 15. The signal is connected to the input of the second block select free decoder 8 'as well as the second column free decoder 9'. In addition, the output / REDYm signal of the redundancy column free decoder 14 'enters the second block select free decoder 8' as another input, and the / REDY signal is the second column free decoder 9 'and the second block select free. Deactivates the decoder 8 ', and the / REDYm signal operates the redundancy block column decoder 16 and enables the corresponding second block select predecoder 8' in which the redundancy block operates. It is composed.

A circuit related to the present invention is shown in FIG. 5, which shows a circuit diagram of parts necessary for the present invention and description in the block diagram of FIG.

The redundancy address selection circuit 12 'receives the Aj and / Aj signals of the address buffers 2 and 3 as inputs, and if the fuse is not blown, the node N1 is high and the node N2 is low. The transfer gate G1 connected with is turned on and the transfer gate G2 connected with / Aj is turned off. In other words, the positive signal Aj is selected as the redundancy address RAj.

When the fuse is blown, the node N1 is turned low and the node N2 is turned high, so that the transfer gate G2 connected to / Aj is turned on and the transfer gate G1 connected to Aj is turned off. The sub-signal / Aj becomes the redundancy address RAj.

The redundancy address RAj enters the input of the redundancy column predecoder 14 '. If the column address and the block selection address coincide with the redundancy address, RAY1 to RAYj, RAZ1, RAZ2, and MF1 are all' 1 '. The signal becomes '0'.

At this time, whether or not the fuses of the redundancy address selection circuit 12 'which inputs the output of each address in accordance with the redundancy address should be blown in advance by using the laser equipment. The output signal of the master fuse 13 from MF1 to MFm turns off the redundancy column predecoder 14 'regardless of the signal RAj in the' 0 'state when the fuse is not blown, and thus the / REDYm signal at this time. Becomes '1'.

Accordingly, the redundancy block column decoder 16 does not operate, and the second column free decoder 9 'and the second block select free decoder 8' which are normal decoding passes operate normally.

When the fuse is blown, the MFm signal is in a '1' state, thereby enabling the operation of the redundancy column predecoder 14 '. When the redundancy address signal RAj is matched, (REDj = 1), the / REDYm signal is described above. As described, it becomes '0'. In this case, m is equal to the number of column redundancy. For example, in the case of FIG. 1, m = 4, and the block selection addresses are two of AZ1 and AZ2.

The / REDYm (m = 1 ~ 4) signal enters the input of the redundancy logic 15 to produce the output / REDY signal. Even if only one of the / REDYm signals is '0', the / REDY signal is '0'. The / REDY signal enters the input of the second column free decoder 9 'and disables the second column free decoder 9' regardless of the states of the AY1 (/ AY1) and AYj (AYj) signals. The node N3 enters the input of the 2-block select predecoder 8 'and is brought into the state of' 1 'regardless of the output AZ1 (/ AZ1) and AZ2 (/ AZ2) signals of the first block select predecoder 5. Make.

When the current redundancy column is selected along the path of / REDY1 corresponding to the first memory block of FIG. 1, the / REDY1 signal is '0' and the remaining / REDY2 to / REDY4 signals are '1'. Thus, the second block select free decoder 8 'of the first memory block is enabled and the rest are disabled.

The output of the second block select select predecoder 8 ′ controls the block row decoder 10 and is not shown in FIG. 4, but is a write driver, sensor amplifier, and bit used for read / write operations of the block. The column redundancy operation according to the present invention is possible because the block logic for controlling circuits such as line pull-up is controlled by the second block select predecoder 8 '.

As described above, when the column redundancy circuit of the present invention described in FIGS. 4 and 5 is used, the redundancy circuit in each memory block can repair not only the bad columns in each memory block but also the bad columns in other blocks. As the repair efficiency of the cell can be increased to the maximum, the yield of the semiconductor device can be improved.

Claims (1)

In a column redundancy circuit in which a whole memory array of a semiconductor device is divided into a plurality of memory blocks, and one or more redundancy columns are implemented for each block, and a bad column occurs in the block, the redundancy column is repaired to the redundancy column. In order to repair not only the memory block but also the bad column of another memory block as a redundancy column implemented in the block, a column address and a block selection address are inputted, and an address for selecting a bad column using a fuse is programmed. Redundancy column free decoding means for operating a block selection path of a memory block to be repaired by combining a redundancy address selecting means and a programmed address output of the redundancy address selecting means, and the redundancy column free of each memory block; Redundancy logic means for combining the output of the coding means to disable the normal column selection pass for selecting a bad column during a repair operation, and redundancy for enabling the repaired redundant column as an input of the output of the redundant column pre-decoding means. Column redundancy circuitry comprising column decoding means.