KR0149589B1 - Semiconductor memory device having low redundancy - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a low redundancy of a semiconductor memory device.

2. Technical challenges to be solved by the invention:

In the related art, redundancy is performed on a block basis, and redundancy efficiency is lowered, or a large number of fuse boxes are required.

3. Summary of the solution of the invention:

A plurality of memory blocks having a spare memory block in a low redundancy according to the present invention, a plurality of fuse boxes for generating a redundancy select signal and a spare word line control signal for driving spare word lines in the spare memory block; In a semiconductor memory device having a plurality of word line driving circuits for generating a word line driving signal for controlling normal word lines in the memory block, a signal related to the selection of the memory block and at least two different redundancy selection signals are inputted. Means for generating a plurality of redundancy enable signals for controlling the state of the word line drive signal.

4. Important uses of the invention:

As a result, a semiconductor memory device having improved redundancy efficiency and reduced chip area is realized.

Description

A semiconductor memory device having a low redundancy function.

1 is a view showing the general configuration of a semiconductor memory device using the conventional redundancy method.

2 is a diagram showing a schematic configuration of a semiconductor memory device using another conventional redundancy scheme.

3 is a circuit diagram of a word line driver circuit used in FIGS. 1 and 2;

4 is a circuit diagram of a fuse box generally used to perform a redundancy function.

5 is a diagram showing a schematic configuration of a semiconductor memory device using the redundancy method according to the present invention.

6 is a circuit diagram of a word line driver circuit used in FIG.

* Explanation of symbols for main parts of the drawings

MBi: Memory Block RDi: Low Decoder

FBi: Fuse box XGi: Word line driving circuit

13, 74: øX0 generation circuit 14, 76: øX1 generation circuit

15, 78: øX2 generation circuit 16, 80: øX3 generation circuit

20: fuse circuit 24: spare word line control circuit

øREDi: Redundancy selection circuit øREEi: Redundancy enable signal

DRA: Row address decoding signal øXi: Word line drive signal

øDPX: Precharge signal SWLi: Spare word line control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to redundancy of semiconductor memory devices, and more particularly, to low redundancy that replaces word lines connected to coupled normal memory devices with word lines connected to corresponding spare memory cells.

As memory capacity of semiconductor memory devices increases, more memory cells are disposed in the chip. As the number of memory cells increases rapidly, the yield decreases, and together with the increase in the memory capacity constituting the highly integrated and large-capacity semiconductor memory devices, the performance and efficiency of the redundancy function must be increased in parallel. It is important for the redundancy technology of semiconductor memory devices that the number of defective normal memory cells needs to be repaired with a smaller number of spare memory cells because the memory cell array needs more area as it proceeds with high density and large capacity. It becomes a goal. In such a redundancy technique, block redundancy, column redundancy, and redundancy and redundancy of memory cell units can be classified according to the classification of the replacement unit. Block redundancy is inefficient because only one defective normal memory cell exists in one memory block and is replaced by the memory block unit, and the redundancy of each memory cell unit is practically easy in high-density and large-capacity semiconductor memory devices because the area for decoding is increased. It is hard to be used.

Column redundancy replaces the column to which the defective normal memory cell is connected, i.e. the bit line, with the corresponding column of the spare memory cell array, and the low redundancy replaces the row or word line to which the defective normal memory cell is connected, the spare word line in the spare memory cell array. To replace it.

FIG. 1 shows a conventional low redundancy scheme applied to recently used semiconductor memory devices, for example, 8 megabit synchronous graphic DRAM.

1 is a part corresponding to 1/2 of the total memory cell array, and each memory block (MBi: i is one of 0-15) has a storage capacity of 256 kilobits. Although not shown in FIG. 1, each memory block is provided with a spare memory block each having, for example, eight word lines. One fuse box (FBi: i is one of 1-10) generates a redundancy select signal (ΦREDi: i is one of 1-10) for controlling the normal word line, and each of four spare memory blocks Generates a control signal that drives the spare word line. For example, the fuse box FB3 drives four spare word lines corresponding to each of the four spare memory blocks provided to the memory blocks MB2-MB5. In addition, the redundancy select signal Φ RED3 generated from the fuse box FB3 is connected to the NOR gate 1 and the NAND gate 5 in the word line driving circuit XG1 for activating the normal word line of the memory blocks MB0-MB3. At the same time, through the NOR gate and the NAND gate to the word line driver circuit XG2 for activating the normal word line of the memory blocks MB4-MB7. In the fuse box, as shown in FIG. 4, the redundancy select signal? REDi and the spare word line control signals SWLO-SWL3 are generated according to the logic states of the row address decoding signals DRA2B3B-DRA8. In FIG. 4, Φ DPX responds to the low address strobe signal RASB and maintains a low level before the row address decoding signals are input, thereby detecting the sense node 22 and the spare word line control circuit 24 of the fuse circuit 20. Node 20 is precharged and transitioned to a high level when the row address decoding signals are input.

When the row address decoding signals related to the defective memory cell are input and a high level redundancy select signal? REDi is generated from the fuse box FBi, the word line driver circuit XGi: i of FIG. 3 is one of 1-4. ) Is applied with a high level redundancy activation signal? RREi. As a result, as all of the word line driving signals ΦX0-ΦX3 controlling the normal word lines are at the low level, the corresponding normal word lines are deactivated and the spare word lines are activated to perform a low redundancy operation.

In the low redundancy method as shown in FIG. 1, when one fuse box is associated with four memory blocks and one memory block is responsible for 1/2 spare word lines, each memory block is activated by 1/4. No more than two rows per memory block can be saved. In addition, in the conventional method of FIG. 1, even when only the memory blocks MB8 and MB9 need to be rescued, the normals of MB4 and MB5 as well as ΦXi (i is 0-4) controlling the normal word lines of MB8 and MB9 ΦXi (i is 0-4), which controls the wordline, is also undesirably disabled and cannot be used if the memory block is ½ active.

On the other hand, in another conventional low redundancy structure shown in FIG. 2, since the redundancy select signal output from the fuse box is applied to only one word line driving circuit through the NOA and NAND gates, the maximum of one memory block is shown. Only rows can be saved. In the case of FIG. 2, as in FIG. 1, the redundancy select signal ΦREDi generated from one fuse box is not deactivated to the normal word line of the neighboring active memory block which is not the target of relief. Since only one remedy is possible, the redundancy efficiency is not better than in the case of FIG. As a result, in the redundancy scheme shown in FIG. 1 or FIG. 2, when the memory block is ½ activated, a larger number of fuse boxes may be used to increase redundancy efficiency, that is, to relieve more than one row for one memory block. I need it. However, this increases the area occupied by circuits involved in redundancy.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of improving redundancy efficiency without using a fuse box.

Another object of the present invention is to provide a semiconductor memory device having a low redundancy function that does not deactivate normal word lines in neighboring active memory blocks that are not subject to relief.

In order to achieve the object of the present invention, a plurality of memory blocks having a spare memory block, a redundancy select signal in response to a row address decoding signal and a spare word line control signal for driving a spare word line in the spare memory block A semiconductor memory device having a plurality of fuse boxes that are generated and a plurality of word line driver circuits for generating word line driving signals for controlling normal word lines in the memory block, the semiconductor memory device having at least two signals associated with the selection of the memory block. And means for generating a plurality of redundancy enable signals for inputting the redundancy select signal to control the state of the word line drive signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the reference numerals referred to in the following description, the same reference numerals will be used as much as possible for elements having substantially the same configuration and function.

The semiconductor memory device of FIG. 5 to which the present invention is actually applied is a synchronous graphic dynamic ram composed of 128 kilobits x 32 bits x 2 banks, as described above with reference to FIG. 1, and is not shown as shown in FIG. The spare memory block belonging to the memory block has eight spare word lines. In addition, the fuse box FBi used in FIG. 5 shows the same arrangement, configuration, and function as those shown in FIG. 4, and those in which hatched memory blocks are activated.

Referring to FIG. 5, the redundancy select signal Φ FED 1 generated from the fuse box FB1 includes a NAND gate along with a signal in which the row address decoding signal DRA8 related to the selection of the memory block is inverted by the inverter 31. 33). The redundancy select signal? RED2 generated from the fuse box FB2 is input to the NAND gate 35 together with a signal in which the row address decoating signal DRA8 related to the selection of the memory block is inverted by the inverter 32. . The redundancy select signal? RED3 generated from the fuse box FB3 is input to the NAND gate 34 together with the logic inverted signal of the DRA8B. The redundancy select signal? RED4 generated from the fuse box FB4 is input to the NAND gate 36 together with the logic inverted signal of the DRA8B.

The process of generating the redundancy selection signal from each fuse box is the same as that of living with reference to FIG. Thus, the outputs of the NAND gates 33 and 34 are input to the NAND gate 37, and the outputs of the other two NAND gates 35 and 36 are input to the NAND gate 38. The outputs of the NAND gates 37 and 38 are the redundancy activation signals? RRE1 and? RRE2, respectively, and are supplied to the word line driving circuit XG1.

The word line driving signals ΦXi: i 1-4 generated from the word line driving circuit XG1 are simultaneously supplied to four memory blocks MB0, MB1, and MB3.

The configuration of inputting and logically combining the neighboring four redundancy selection signals and the low address decoding signals DRA8 and DRA8B related to the memory block selection is similarly repeated for every four memory blocks. For example, in order to generate the word line driving signal Φ Xi from the word line driving circuit XG3 to control the normal word lines of the four memory blocks MB8, MB9, MB10, and MB11, the fuse box FB5 may be used. The NAND gate 55 for inputting the redundancy select signal? RED5 and the logic inverted signal of the DRA8 generated from the signal; and the redundancy select signal? RED7 and the logic inverted signal for the DRA8B generated from the fuse box FB7. NAND gate 54 for inputting the NAND gate 54, the redundancy select signal? RED8 generated from the fuse box FB8 and the inverted signal of the DRA8B, and NAND for inputting the outputs of the NAND gates 53 and 54; The NAND gate 58 which inputs the gate 57 and the output of the NAND gates 55 and 56 is used.

Thus, for example, in relieving a defective row in the memory blocks MB8 and MB9, the DRA8B is at a high level (DRA8 is at a low level) so that the NAND gates 54 and 56 are inactivated and the NAND gates 53 and 55 are deactivated. Is activated. Eight spare word lines are arranged in the spare memory block belonging to the memory block MB8, and each fuse box generates four spare word line control signals SWLO-SWL3 as shown in FIG. The redundancy select signals? RED5 and? RED6 from the fuse boxes FB5 and FB6 are activated to a high level in order to deactivate the normal wordlines belonging to the subfields MB8 and MB9 and to drive corresponding spare wordlines. At this time, ΦRED7 and ΦRED8 are inactive at the low level. Accordingly, the NAND gates 53 and 55 respectively accept ΦRE5 and ΦRED6 as valid inputs, and in response, the NAND gates 57 and 58 generate valid redundancy activation signals ΦRRE1 and ΦRRE2, respectively. That is, the redundancy activation signals ΦRRE1 and ΦRRE2 respectively corresponding to ΦRED5 and ΦRED6 are applied to the word line driving circuit XG3.

At this time, in the logic combination circuit for the word line composition circuit XG2, even though ΦRED5 and ΦRED6 are input to the NAND gates 44 and 46 at the high level, respectively, the DRA8B is connected to the NAND gates 44, at the low level through the inverter 42. 46 is simultaneously applied, it can be seen that no valid redundancy activation signal is generated.

(In the conventional scheme of FIG. 1, it can be seen that ΦXi, which controls the normal word lines of adjacent active memory blocks MB4 and MB6, besides ΦXi, which controls the normal word lines of MB8 and MB9, is also deactivated.)

Referring to FIG. 6, ΦRRE1 and ΦRRE2 applied to the word line driving circuit XGi respectively input four row address decoding signals DRAOB1B, DRAO1B, DRAOB1, and DRAO1 through the inverters 62. Are input to the field 64 in common. Since ΦRRE1 and ΦRRE2 are high level, all of the NOA gates 64 are inactivated and all of the NMOS pull-down transistors 70 are turned on so that the word line driving signals ΦX0-ΦX3 are all low level. It becomes inactive. Spare word line control generated from the fourth fuse boxes FB5 and FB6 instead of the normal word lines of the corresponding memory blocks MB8 and MB9 are not driven. The redundancy operation is performed by the signals SWL0-SWL3 driving the spare word lines of the spare memory block.

As another example, when performing low redundancy for the memory blocks MB4 and MB5, the redundancy activation signals ΦRRE1 in response to the redundancy select signals ΦRED3 and ΦRED4 generated from the fuse boxes FB3 and FB4. It can be understood that Φ RRE2 is generated and thereby a word line driving signal for deactivating the normal word line of the memory blocks MB4 and MB5 is generated from the word line driving circuit XG2 to activate the corresponding spare word line. have. Also in the case where the active memory blocks indicated by hatching in FIG. 5 are changed by the row address signal RA8 (the active memory blocks become MB2, MB3, MB6, MB7, MB10, MB11, MB14, MB15). As in the same process, the low redundancy operation is performed. For example, when low redundancy is performed on the memory blocks MB10 and MB11, the NAND gates 54 and 56 are activated and ΦRRE1 and ΦRRE2 responding to ΦRED7 and ΦRED8 generated from the fuse boxes FB7 and FB8. Is generated at a high level, whereby the word line configuration signal generated from the word line driver circuit XG3 deactivates the corresponding normal word lines of MB10 and MB11 and spare word line control signals generated from FB7 and FB8, respectively. Spare word lines corresponding to normal word lines deactivated by SWL0-SWL3) are activated.

As described above, the present invention has an effect of solving the problem that redundancy efficiency is lowered by undesirably deactivating even normal word lines of a neighboring memory block in performing low redundancy. In addition, the present invention is advantageous in that it can be applied to a highly integrated semiconductor memory device because it can perform an efficient redundancy function without increasing the number of fuse boxes.

The present invention is not limited to the above-described embodiments, and the present invention may be easily implemented by those skilled in the art by simply changing or adding the structure and the like within the scope of the present invention. will be.

Claims (2)

A plurality of memory blocks having a spare memory block, a plurality of fuse doctors for generating a redundancy select signal in response to a row address decoding signal and a spare word line control signal for driving spare word lines in the spare memory block; A semiconductor memory device having a plurality of word line driving circuits for generating a word line driving signal for controlling normal word lines in a memory block, the semiconductor memory device comprising: receiving a signal related to selection of the memory block and at least two or more redundancy selection signals; And means for generating a plurality of redundancy enable signals for controlling the state of the word line drive signal. 2. The first group of logic gates according to claim 1, wherein the means inputs a first group of logic gates for commonly inputting a first logical state to the signal related to the selection of the memory block, and a second group for inputting a second logical state of the signal. Logic gates, a logic gate for inputting an output of the first group of logic gates to generate a first redundancy activation signal, and a logic for inputting an output of the second group of logic gates to generate a second redundancy activation signal And the redundancy selection signals generated from the fuse boxes having gates and each of the logic gates of the first and second groups are different from each other.